CN101069152A - Electronic device having multi operand arithmetic circuitry - Google Patents
Electronic device having multi operand arithmetic circuitry Download PDFInfo
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- CN101069152A CN101069152A CNA2005800411258A CN200580041125A CN101069152A CN 101069152 A CN101069152 A CN 101069152A CN A2005800411258 A CNA2005800411258 A CN A2005800411258A CN 200580041125 A CN200580041125 A CN 200580041125A CN 101069152 A CN101069152 A CN 101069152A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/499—Denomination or exception handling, e.g. rounding or overflow
- G06F7/49994—Sign extension
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
- G06F7/509—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination for multiple operands, e.g. digital integrators
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/499—Denomination or exception handling, e.g. rounding or overflow
- G06F7/49905—Exception handling
- G06F7/4991—Overflow or underflow
- G06F7/49921—Saturation, i.e. clipping the result to a minimum or maximum value
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Abstract
An electronic device comprising an arithmetic circuitry (AC) for performing at least one of an addition or a subtraction of more than two binary input numbers (BINl - BIN4) is provided, wherein at least two of the binary input numbers differ in their bit-widths. The arithmetic circuitry (AC) comprises an extension means (EUl - EU3) for performing a sign and/or a zero extension of at least one of the binary input numbers (BINl - BIN4). Further, the arithmetic circuitry (AC) comprises at least two two-operand arithmetic units (AUl - AU3), each for calculating an addition and/or a subtraction of two operands being a first and a second binary number, and overflow and saturation means (OSUl - OSU3) for detecting a calculation overflow of at least one two-operand arithmetic unit (AUl - AU3) and for saturating the calculation result of the arithmetic unit (AUl - AU3) in accordance with the detected overflow result.
Description
Technical field
The present invention relates to a kind of electronic equipment with computing circuit, described computing circuit be used for carrying out two above scale-of-two input numbers add deduct at least one.The bit wide of these at least two scale-of-two input numbers is different.The invention still further relates to a kind of method that adds deduct that is used for two above scale-of-two input numbers.In addition, the present invention relates to a kind of method that is used to design computing circuit.The invention still further relates to a kind of data handling system with electronic equipment, this electronic equipment has at least one the computing circuit that adds deduct that is used to carry out plural scale-of-two input number with different bit wides.
Background technology
Be used for the processor of digital signal processor (DSPs), other types or the arithmetic element of microprocessor and special IC (ASICs) and comprise scale-of-two input number with predetermined figure.The figure place of expression scale-of-two input number is a bit wide.Limited bit wide limits the narrow number of representing.Because the narrow number of representing, the scale-of-two input number in the logical block is restricted to maximum denotable value, minimum denotable value and limited quantized value.For avoiding surpassing minimum and maximal value in the computing interval, result of calculation has the bit wide of expansion to cover all possible result.Monitor this result, and generation overflow (or underflow) designator has been violated predetermined bit width with expression.Typically, but overflow or underflow flag are used to represent whether result of calculation expands to the scope of permissible value.In addition, if overflow or underflow take place, represent that then the scale-of-two input number of result of calculation is set to predetermined value, promptly maximum or minimum denotable value.This step is called saturated.
The widely used feature of the operation processing unit that is adopted in DSP, microcontroller and the microprocessor is overflow detection and saturation arithmetic.Saturated for reducing owing to the narrow mistake of representing that number produces in quantification and the Computing is necessary.Scale-of-two input number uses so that symbol and no sign form to be arranged.The general format that symbol scale-of-two input digit is arranged is 2 complement.Complement according to 2, the start bit of negative value (leading) is 1.
The structure of most of processors is based on two operand model.Therefore, always calculate scale-of-two input number with identical binary representation and same bit-width.If must use identical arithmetic operation to plural number, then carry out this computing serially, that is, two numbers are carried out this computing and then the 3rd number carried out this computing.Particularly, current application specific processor often needs more than one computing based on two operands.In addition, even to same arithmetic element, the bit wide of the scale-of-two input number that calculate all may change.About processor, can consider two kinds of scenes: have the processor of arithmetic and logical unit or controller and be generally used for two digital multiplies and the addition of will from storer, obtain; The ASIC that comprises dedicated logic circuit is used for carrying out calculation procedure with more efficient method.
The design of ASIC computing circuit supported by the design software instrument usually, and often is envisaged as with hierarchical approaches and designs.The stage circuit layout strategy starts from more accurate circuit performance definition.In step after this, deviser or design software comprehensively define logic gate and transistor to satisfy performance.At the end of comprehensive step, there be the schematic diagram and the wiring diagram of circuit, be that the basis produces this circuit finally with schematic diagram and wiring diagram.Current, automatically perform each step of designing treatment.Yet after the automatic Synthesis step, the computing circuit that is produced usually can not overall optimumization.Therefore, need make great efforts to find effective notion and rule to come the computing circuit of design optimization.
To the following explanation of the computing of multioperand is to represent about 2 complement of the standard of integer.For simple 2 input arithmetic elements, the identical situation of the bit wide of two inputs wherein, it is well-known detecting for overflowing of adding deduct.Usually, the bit wide of result of calculation is bigger one than the bit wide of scale-of-two input number.In addition, provide carry flag (or bit).This overflow flag is the carry flag of signless integer, or the logical and of right and wrong (negated) carry flag and result's the highest-order bit is being arranged under the symbol situation.Can obtain underflow flag by using same logic.In case the overflow of detecting or underflow will adopt saturated.When saturated, resulting result is replaced by maximum (under the situation of overflow) or minimum (under the situation of underflow) denotable value.
Operand more than two situation under, can't adopt known and direct overflow detection methods.For example, add three times 1111
2Can produce (0) 1101
2Therefore, carry flag is 0.Though this carry flag 0 expression overflow has taken place, and does not detect overflow.Same problem occurs on the operand of symbol.If have the plural operand addition of different bit wides, can produce other problem.For example, 1111
2+ 1111
2+ 11111111
2To produce 100011101
2Even this result is correct for no symbol situation, be incorrect still for the binary number that symbol is arranged.For signed number, correct result is 11111101
2(3
10).In sum, to having the unit of two above input operands, can not detect and saturation arithmetic to realize overflow or underflow in direct mode.
At US 5,917, a kind of arithmetic element is disclosed in 739, the n bit that wherein calculates four integer operation numbers that symbol or signless n bit arranged in an instruction cycle is average.Described a kind of can be in order to the Method and circuits of the mean value that obtains four numbers, wherein this four number has identical bit wide.The method and circuit are not contained saturated.Expanded intermediate result, but do not mentioned saturated.
US 2003/0140072 relates to two input additions.Two inputs all have identical bit wide.
US 6,321, and 248 disclose the overflow detection of two input computings.For dyadic operation, mentioned the special case of two operands with different bit wides.
At " Overflow detection in multi-operand addition (multioperand addition overflow detection) ", International Journal of Electronics, Vol.73, No.3, pp.461-469,1992, disclose a kind of among the Pai and Tran in order to detect the computing of the overflow in the multioperand addition.Expand this computing to support the chip of the computing totalizer that generality is commercial.This is used for combining with the carry save adder of multioperand and the serial adder of multioperand, to detect overflow.In addition, in these circuit, be provided with to comprise the subtraction of operand.Be the checking computing, the use cad tools comes the logic in the simulation hardware.According to Pai and Tran, all inputs all have identical bit wide.It is intended to calculate according to the number of input the number of needed carry output.
For the terseness of this instructions, term " overflows (overflow) " and comprises " underflow ".Therefore, relate to the situation that any " overflowing detection " and the place of saturated accordingly (maximal value) all are understood to include " underflow detection " and saturated accordingly (minimum value).
Summary of the invention
The purpose of this invention is to provide a kind of improved and effective electronic equipment with computing circuit, this computing circuit is carried out calculation operations to two above scale-of-two input numbers, and wherein at least two scale-of-two input numbers have different bit wides.Another object of the present invention provides a kind of method for designing to produce improved computing circuit, and this computing circuit is carried out calculation operations to two above scale-of-two input numbers, and wherein at least two scale-of-two input numbers have different bit wides.
This purpose by according to the electronic equipment of claim 1, according to the data handling system of claim 6, according to claim 7 be used to calculate N scale-of-two input number and or the method for difference and being used to according to Claim 8 the method that designs computing circuit solved.
Therefore, provide a kind of at least one electronic equipment of computing circuit that adds deduct that is used for carrying out two above scale-of-two input numbers that comprises, wherein, at least two scale-of-two input numbers have different bit wides.This computing circuit comprise be used for carrying out scale-of-two input number at least one symbol and/or the expanding unit of zero expansion.In addition, computing circuit comprises: at least two two-operand arithmetic units, each two-operand arithmetic units are calculated adding and/or subtract as two operands of first and second binary numbers; Overflow and saturation device, the calculating that is used to detect at least one two-operand arithmetic units is overflowed, and makes the result of calculation of arithmetic element saturated according to the detected result of overflowing.
Therefore, all the time two scale-of-two input arrays are closed to obtain middle or net result.Overflow and detect and the saturated result of calculation that is applied to each two operand independently.Just in time net result is calculated in two inputs.Like this, two operands overflow and detect and saturated general rule can be recycled and reused for each two-operand arithmetic units.According to the present invention, expanding unit is set when needed, be extended to and have identical bit wide scale-of-two is imported number in the computing interval.Expanding unit can be disposed in the input end of computing circuit so that all scale-of-two input numbers are extended to identical bit wide.In addition, expanding unit can be used for before the output of main two-operand arithmetic units is imported into next two-operand arithmetic units, with its expansion between two two-operand arithmetic units.Overflow the result of calculation of controlling two-operand arithmetic units with saturation device, detection computations is overflowed, and is set to maximum or minimum value according to the detected result's of overflowing result of calculation.Overflow the output with all two-operand arithmetic units of saturation device may command,, then overflow the output that only to control some two-operand arithmetic units with saturation device if be scheduled to can not overflow in the moment of circuit.Sign extended is used to have under the situation of symbolic operation, and zero expansion is used to not have under the situation of symbolic operation.The arithmetic element that is proposed can have the input that has different bit wides more than two, also can detect overflow or underflow and make the result correctly saturated.Whether this expanding unit detects input operand needs symbol or zero expansion, and correspondingly expands this operand.
According to aspects of the present invention, computing circuit comprises the input media that is used at least one scale-of-two input number is input to expanding unit.If provide more than one scale-of-two input number to input media, these numbers can be imported in parallel mode.For many application, it is favourable comparing with serial mode with parallel mode input number, and serial mode only allows one by one or imports number by bit.
According to another aspect of the present invention, a plurality of expanding elements are provided in computing circuit, come at bit wide each scale-of-two input number littler, the symbol and/or zero expansion of at least one in the execution scale-of-two input number than the bit wide of scale-of-two input number with maximum bit wide.A kind of very efficient method is to use the expanding unit of a plurality of expanding elements to replace certain to concentrate.Preferably each expanding element is placed in input block near computing circuit.By this way, each expanding element can be specifically designed to the scale-of-two input number that expansion has the bit wide littler than maximum bit wide.Therefore, determine to have the bit wide of the scale-of-two input number of maximum bit wide, and other scale-of-two input numbers with less bit wide are extended to have maximum bit wide.This expanding element needn't be placed in the input end of computing circuit, but also can be positioned at the somewhere of computing circuit.
According to another aspect of the present invention, all expanding elements all provide the input that is used for input control signal, and this control signal represents that the scale-of-two input number that is delivered to expanding element has symbol or no sign form.Therefore, expanding element is controlled by the input that typically is single bit control input, so that in response to the form of represented scale-of-two input number, binary number is carried out symbol or zero fat binary number.
According to another aspect of the present invention, electronic equipment comprises a plurality of overflowing and saturation unit, and each calculating that is used to detect single two-operand arithmetic units is overflowed, and according to the detected result of overflowing, the result of calculation of this two-operand arithmetic units is saturated.A plurality of uses of overflowing with saturation unit cause quite independently computing, help the computing velocity and the efficient of whole computing circuit.For example, if each two-operand arithmetic units and then special use overflow and saturation unit, realize overflowing and can overflow with each logical circuit of saturated flow process that to be used for the situation of a plurality of two-operand arithmetic units simple with saturation device than one.
The invention still further relates to a kind of be used to calculate N scale-of-two input number and and/or the method for difference, wherein N greater than 2 and at least two scale-of-two input numbers have different bit wides.The method comprises step: at least one scale-of-two input number that will have less bit wide expands to have and the identical bit wide of second scale-of-two input number.In another step, calculate two scale-of-two and import numbers and and/or poor.This calculation procedure is carried out by using N-1 two-operand arithmetic units, and wherein each two-operand arithmetic units is used to calculate adding and/or subtract as two operands of first and second binary numbers.In addition, detect at least one the overflowing of result of calculation in the two-operand arithmetic units, and carry out the saturated of this result of calculation according to the detected result of overflowing.Because this calculation procedure is limited to two-operand arithmetic units, so calculate, overflow and detect and other solutions of saturation ratio are fast and complexity is low.
The invention still further relates to a kind of method that is used to design computing circuit, this computing circuit is used to carry out adding of N scale-of-two input number and/or subtracts, wherein N greater than 2 and at least two scale-of-two input numbers have different bit wides.In the overall treatment according to computing circuit of the present invention, must provide following entity: input media is used for N scale-of-two input number is input to computing circuit; Expanding unit, the symbol and/or zero expansion of at least one in the execution binary number input number; N-1 two-operand arithmetic units, each is used to calculate adding and/or subtract as two operands of first and second binary numbers; Overflow and saturation device, the calculating that is used to detect at least one two-operand arithmetic units is overflowed, and makes the result of calculation of arithmetic element saturated according to the detected result of overflowing; And input media, expanding unit, arithmetic element and overflow and saturation device between connection.The computing circuit designed according to top design procedure is lower and more effective than traditional circuit complexity.
According to another aspect of the present invention, the method that is used to design computing circuit comprises step: the concatenation operation circuit makes each output of N-1 two-operand arithmetic units all be connected to and overflows and saturation device.
Description of drawings
With reference to following described enforcement and the following drawings, these and other aspects of the present invention will be apparent, and be illustrated, wherein:
Fig. 1 shows the block scheme according to the three-operand arithmetic circuitry of the first embodiment of the present invention;
Fig. 2 shows the block scheme of multioperand circuit according to a second embodiment of the present invention;
Fig. 3 shows the block scheme of the multi operand arithmetic circuitry of a third embodiment in accordance with the invention.
Embodiment
Fig. 1 shows the block scheme according to the three-operand arithmetic circuitry of the first embodiment of the present invention.Three scale-of-two input number BIN1, BIN2, BIN3 are input to computing circuit AC.First and second scale-of-two input number BIN1, BIN2 have bit wide bw1, the bw2 littler than the 3rd binary number BIN3.First and second scale-of-two input number BIN1, BIN2 are input to the first and second expanding element EU1, EU2.In expanding element EU1, EU2, scale-of-two input number BIN1, BIN2 carry out symbol or zero expansion respectively, so that have the identical bit wide bw3 with the 3rd scale-of-two input number BIN3.These two sign extension units EU1, EU2 are connected to the input end of the first two-operand arithmetic units AU1.This arithmetic element AU1 carries out calculation procedure to two input.This calculation procedure can be subtracting or add or arbitrarily similarly computing two input operands.The output of this first two-operand arithmetic units AU1 is overflowed with saturation unit OSU2 by first and is controlled.This overflows the output of checking the first two-operand arithmetic units AU1 with saturation unit OSU1, detects possible overflowing, and makes result of calculation saturated according to detected overflowing.For example, if the bit wide bw3 of the 3rd scale-of-two input number BIN3 is 8 bits, scale-of-two input number BIN1 that has then expanded and bit wide bw4, the bw5 of BIN2 also are 8 bits.Then AU1 is output as 9 bits or 10 bit widths.Overflow with saturation unit OSU1 the result is restricted to 8 bits.The output of OSU1 has bit wide bw7, and bw7 equates with the bit wide bw3 of scale-of-two input value BIN3.In OSU1,, first output of overflowing with saturation unit OSU1 is input to the second two-operand arithmetic units AU2 by after saturated.Second input of the second two-operand arithmetic units AU2 is the 3rd scale-of-two input number BIN3, and it is carried out arithmetic operation.Because bw7 equals bw3, so two inputs have identical bit wide.This is because the first and second expanding element EU1, EU2 and OSU1, the first and second expanding element EU1, EU2 with first and second scale-of-two input number BIN1, BIN2 expands to and the 3rd the identical bit wide of scale-of-two input number BIN3.Overflow with saturation unit OSU2 is detected according to second and to overflow, control and saturated is overflowed in the output of the second two-operand arithmetic units AU2.The bit wide bw8 of the output of AU2 is 9 bits or 10 bits.In OSU2, overflow with saturated control after, this result is restricted to the bit wide of 8 bits once more.If calculating subsequently or the processing stage can handle more than 8 bits, then can omit OSU2.
All carry out under the situation of addition at two two-operand arithmetic units AU1 and AU2, second overflow output with saturation unit OSU2 be the correct of three scale-of-two input number BIN1, BIN2 and BIN3 and.All carry out under the situation of subtraction at two two-operand arithmetic units AU1 and AU2, second to overflow output with saturation unit OSU2 be the correct poor of three scale-of-two input number BIN1, BIN2 and BIN3.
Fig. 2 shows the block scheme of the second embodiment of the present invention.Four scale-of-two input number BIN1-BIN4 are input to arithmetic element AC.Provide four input block IU1-IU4 to be respectively applied for four scale-of-two inputs of input number BIN1-BIN4.Input block IU1-IU4 be input pin or equal connection or or even latch etc., be input to computing circuit AC in order to scale-of-two is imported number BIN1-BIN4.Four input block IU1-IU4 can be arranged on the identical or different sides of computing circuit AC.In addition, four input block IU1-IU4 can be used as a module and realize, wherein input pin or connection or latch are reused for the two or more binary number BIN1-BIN4 of input.Scale-of-two input number BIN1-BIN3 has little bit wide bw1, bw2, the bw3 of bit wide bw4 than the 4th scale-of-two input number BIN4.The output of input block IU1, IU2, IU3 has bit wide bw5, bw6, bw7 respectively, and typically, bw5, bw6, bw7 equal bw1, bw2, bw3.This do not get rid of binary input signal input block by become the symmetry.For the scale-of-two input number BIN1-BIN3 that has bit wide bw5, bw6, bw7 respectively provides expanding element EU1-EU3 respectively.The scale-of-two input number BIN1 that has expanded has identical bit wide bw8 and bw9 with BIN2, and is added deduct in the first two-operand arithmetic units AU1.The output of the first arithmetic element AU1 has bit wide bw12, and overflows with saturation unit OSU1 by first and to overflow and saturated control.Expand to bit wide bw16 in the 3rd expanding element EU3 after, the output that the 3rd scale-of-two input number BIN3 and first overflows with saturation unit OSU1 combines.The output of the second arithmetic element AU2 is overflowed with saturation unit OSU2 by second and is overflowed and saturated control.The output of overflowing with saturated control is passed to the 3rd two-operand arithmetic units AU3.This unit overflows with output and the 4th scale-of-two of saturation unit OSU2 second imports number BIN4 execution computing.The output of the 3rd two-operand arithmetic units AU3 is overflowed with saturation unit OSU3 by the 3rd and is overflowed and saturated control.
All carry out under the situation of addition at three all two-operand arithmetic units AU1-AU3, the 3rd overflow output with saturation unit OSU3 be the correct of four scale-of-two input number BIN1-BIN4 and.Yet,, can realize configuration and corresponding results that some are different if carry out different calculation operations or the scale-of-two input number BIN1-BIN4 that symbol is arranged is handled as three arithmetic element AU1-AU3.The output of the first arithmetic element AU1 has bit wide bw12, little one or two bit of this bit wide bw8, bw9 than two input operands of arithmetic element AU1.Bit wide bw12 is defined as bw13 in OSU1, equal bw10.The output of the second arithmetic element AU2 has bit wide bw14, and bw14 is defined as bit wide bw15 in OSU2.Bw15 equals bw11.Bw11 equals bw4.Two binary numbers with bit wide bw15 and bw11 are fed to arithmetic element AU3.Output has a bit wide bw16, than bit wide bw15 and big one or two bit of bw11 of the input of AU3.The output of AU3 is fed to OSU3,, it is defined as bit wide bw17 at OSU3.Bw17 equals bw4.Bw17 may be than big one or two bit of bw4.
Fig. 3 shows the block scheme of the third embodiment of the invention of the optional embodiment that forms second embodiment.Four scale-of-two input number BIN1-BIN4 are imported into computing circuit AC.Provide four input block IU1-IU4 to be respectively applied for four scale-of-two inputs of input number BIN1-BIN4.Input block IU1-IU4 be input pin or equal connection or or even latch, impact damper etc., be input to computing circuit AC in order to scale-of-two is imported number BIN1-BIN4.Four input block IU1-IU4 can be arranged in respectively on the identical or different sides of computing circuit AC.In addition, four input block IU1-IU4 can be used as a module and realize, wherein input pin or connection or latch are reused for two or more scale-of-two of input and state BIN1-BIN4.Scale-of-two input number BIN1-BIN3 has little bit wide bw1, bw2, the bw3 of bit wide bw4 than the 4th scale-of-two input number BIN4.Therefore, provide expanding element EU1-EU3 for scale-of-two input number BIN1-BIN3.Expanding element EU1-EU3 has the control input of individual bit alternatively.If the control of individual bit is input as " height ", then symbol expanding element EU1, EU2 or the expansion of EU3 DO symbol.If the control of individual bit is input as " low ", then symbol expanding element EU1, EU2 or EU3 carry out zero expansion.If used such sign extended control, whether then all expanding element EU1-EU3 must must carry out the prosign signal controlling that symbol is arranged or do not have symbolic operation by expression.The scale-of-two input number BIN1 and the BIN2 that have expanded are added deduct in the first two-operand arithmetic units AU1.The output of AU1 has bit wide bw12.Third and fourth scale-of-two input number BIN3 and BIN4 are added deduct in the second two-operand arithmetic units AU2.Output with the first and second arithmetic element AU1 of bit wide bw12, bw13 and AU2 is overflowed with saturation unit OSU1 and OSU2 by first and second and is overflowed and saturated control, and is defined as bit wide bw14 and bw15 respectively.Overflow with the output of saturated control and have identical bit wide bw15 and bw16, and be passed to the 3rd two-operand arithmetic units AU3.This unit calculates the first and second two-operand arithmetic units AU1 and AU2 two and overflows with the output of saturated control and or poor.The output of the 3rd two-operand arithmetic units AU3 has bit wide wb16, and overflows with saturation unit OSU3 by the 3rd and to overflow and saturated control.The bit wide of the output of OSU3 is bw17.Bw17 equals bw4, perhaps can handle under the wide situation of multidigit more at subsequently calculating or processing unit, and bw17 is than big 1 to 2 bit of bw4.
All carry out under the situation of addition at three all two-operand arithmetic units AU1-AU3, the 3rd overflow output with saturation unit OSU3 be the correct of four scale-of-two input number BIN1-BIN4 and.Yet,, can realize configuration and corresponding results that some are different if carry out different calculation operations or the scale-of-two input number BIN1-BIN4 that symbol is arranged is handled as three arithmetic element AU1-AU3.
According to another embodiment of the present invention, provide a kind of method for designing that is used to design computing circuit AC.Especially, the computing circuit of the correspondence of first, second shown in Fig. 1,2 and 3 and the 3rd embodiment can be used as the result that automatic or semi-automatic design synthesis is handled.The rule of importing the design cycle of numbers at 4 scale-of-two with variable bit width can be as giving a definition.At first, provide input block IU1, IU2, IU3, the IU4 that is used for 4 scale-of-two input number BIN1-BIN4 are input to computing circuit.In addition, provide three expanding element EU1, EU2, the EU3 that is used for binary number BIN1, BIN2, BIN3 DO symbol or zero expansion.In another design procedure, three two-operand arithmetic units AU1, AU2, AU3 are provided.About arithmetic element AU1-AU3, provide three that the calculating that is used to detect three two-operand arithmetic units AU1, AU2, AU3 overflows to overflow and saturation unit OSU1, OSU2, OSU3, wherein overflowed with saturation unit OSU1, OSU2, OSU3 and make the result of calculation of arithmetic element AU1, AU2, AU3 saturated according to the detected result of overflowing.At last, provide input block IU1, IU2, IU3, expanding element EU1, EU2, EU3, arithmetic element AU1, AU2, AU3 and overflow and saturation unit OSU1, OSU2, OSU3 between connection.Carry out the step that all are mentioned, make and to make example shown in Fig. 2 or 3 based on schematic diagram or wiring diagram as a result.
According to another embodiment of the present invention, provide be used to calculate 4 scale-of-two input number BIN1, BIN2, BIN3, BIN4's and or the use of the two-operand arithmetic units AU1-AU3 of difference.The bit wide difference of scale-of-two input number BIN1, BIN2, BIN3.At first step, binary number BIN1-BIN3 is extended to has the identical bit wide with the 4th scale-of-two input number BIN4.Use three two-operand arithmetic units AU1, AU2, AU3, wherein each is used to calculate adding deduct of two operands.In another step, the overflowing of the result of calculation of detection calculations unit AU1-AU3, and make result of calculation saturated according to the detected result of overflowing.
All embodiment that mention of the present invention can comprise the input block that is used to import scale-of-two input number.Yet input block is not the necessary part of embodiment.Each input block can provide single bit control input, so that in response to the control input value, switches between symbol and zero expansion.
Scope of the present invention is not limited to any special format or the expression of scale-of-two input number, and can be integer or floating-point format, can be that symbol or signless expression are arranged.
Though the foregoing description has been described in the expression with the complement of the standard 2 of integer, the present invention should not be considered to be limited to this scale-of-two numerical representation.
It should be noted, above the embodiment illustration mentioned and and unrestricted the present invention, and under the prerequisite of the scope that does not depart from claims, those skilled in the art can design many optional embodiments.In the claims, any Reference numeral between the bracket should not be construed as restriction the present invention.Speech " comprises " does not get rid of the element listed in the claim or the existence of element outside the step or step.The existence that speech " " before the element or " one " do not get rid of a plurality of this elements.Enumerate in the equipment claim of multiple arrangement at meter, some in these devices can be embodied by same item of hardware.Unique fact is that some measure that is arranged in the dependent claims that differs from one another does not represent that the combination of these measures can not produce beneficial effect.
In addition, any Reference numeral in the claim should not constitute the scope of restriction claim.
Claims (10)
1. electronic equipment comprises:
-computing circuit (AC), be used for carrying out two above scale-of-two input numbers (BIN1, BIN2, BIN3, BIN4) add deduct at least one, wherein, at least two scale-of-two input numbers (BIN1, BIN2, BIN3, BIN4) have different bit wides,
Computing circuit (AC) comprises
-expanding unit (EU1, EU2, EU3), be used for carrying out scale-of-two input number (BIN1, BIN2, BIN3, BIN4) at least one symbol and at least one in zero expansion,
-at least two two-operand arithmetic units (AU1, AU2, AU3), each be used for calculating as two operands of first and second binary numbers add and subtract at least one,
-overflow and saturation device (OSU1, OSU2, OSU3), the calculating that is used to detect at least one two-operand arithmetic units (AU1, AU2, AU3) is overflowed, and is used for making the result of calculation of two-operand arithmetic units (AU1, AU2, AU3) saturated according to the detected result of overflowing.
2. electronic equipment as claimed in claim 1, wherein, computing circuit (AC) also comprises:
-input media (IU1, IU2, IU3, IU4) is used at least one scale-of-two input number (BIN1, BIN2, BIN3, BIN4) is input to expanding unit (EU1-EU3).
3. electronic equipment as claimed in claim 1 or 2, wherein, described computing circuit (AC) comprising:
-a plurality of expanding elements (EU1, EU2, EU3), be used at bit wide each scale-of-two input number littler, at least one in symbol of at least one in the execution scale-of-two input number (BIN1, BIN2, BIN3, BIN4) or zero expansion than scale-of-two input number with maximum bit wide.
4. electronic equipment as claimed in claim 3, wherein, in the expanding element (EU1, EU2, EU3) at least one provides input, be single bit input specifically, in order to receive control signal, described control signal represents that scale-of-two input number (BIN1, BIN2, BIN3) is signed binary or no symbol binary number.
5. as the described electronic equipment of one of claim 1 to 4, wherein, computing circuit (AC) comprising:
-a plurality of overflowing and saturation unit (OSU1, OSU2, OSU3), each calculating that is used to detect a two-operand arithmetic units (AU1, AU2, AU3) is overflowed, and is used for making the result of calculation of two-operand arithmetic units (AU1, AU2, AU3) saturated according to the detected result of overflowing.
6. a data handling system comprises that at least one is according to the described electronic equipment of one of claim 1 to 5.
One kind be used for calculating N scale-of-two input number (BIN1, BIN2, BIN3, BIN4) and with at least one method of difference, wherein, N greater than 2 and at least two scale-of-two input numbers (BIN1, BIN2, BIN3, BIN4) have different bit wides, described method comprises:
-at least one first scale-of-two input number (BIN1, BIN2, BIN3, BIN4) that will have a shorter bit wide is extended to have and the identical bit wide of second scale-of-two input number (BIN1, BIN2, BIN3, BIN4);
-use N-1 two-operand arithmetic units (AU1, AU2, AU3), each be used for calculating two operands add and subtract at least one, and carry out this calculating;
-detection computations result's overflows; And
-make result of calculation saturated according to the detected result of overflowing.
8. method that is used to design computing circuit (AC), described computing circuit be used for carrying out N scale-of-two input number (BIN1, BIN2, BIN3, BIN4) add and subtract at least one, wherein, N is greater than 2, and at least two scale-of-two input numbers have different bit wides, and described method comprises:
-be provided for N scale-of-two imported the input media (IU1, IU2, IU3, IU4) that number is input to computing circuit (AC),
-expanding unit (EU1, EU2, EU3) is provided, be used for carrying out scale-of-two input number (BIN1, BIN2, BIN3, BIN4) at least one symbol and at least one in zero expansion,
-N-1 two-operand arithmetic units (AU1, AU2, AU3) be provided, each be used for calculating as two operands of first and second binary numbers add and subtract at least one,
-provide and overflow and saturation device (OSU1, OSU2, OSU3), the calculating that is used to detect at least one two-operand arithmetic units (AU1, AU2, AU3) is overflowed, and make the result of calculation of arithmetic element (AU1, AU2, AU3) saturated according to the detected result of overflowing
-input media (IU1, IU2, IU3), expanding unit (EU1, EU2, EU3), arithmetic element (AU1, AU2, AU3) are provided and overflow and saturation device (OSU1, OSU2, OSU3) between connection.
9. method according to claim 8 comprises step: provide connection in computing circuit (AC), make each input of N-1 two-operand arithmetic units (AU1, AU2, AU3) link to each other with described overflowing with saturation device (OSU1, OSU2, OSU3).
10. a computer program comprises program code devices, is used for when described computer program moves on computers, makes the step of computing machine execution as claim 7 or 8 described methods.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP04106211 | 2004-12-01 | ||
| EP04106211.8 | 2004-12-01 |
Publications (1)
| Publication Number | Publication Date |
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| CN101069152A true CN101069152A (en) | 2007-11-07 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2005800411258A Pending CN101069152A (en) | 2004-12-01 | 2005-11-28 | Electronic device having multi operand arithmetic circuitry |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP1820092A2 (en) |
| JP (1) | JP2008522304A (en) |
| CN (1) | CN101069152A (en) |
| WO (1) | WO2006059267A2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8316071B2 (en) | 2009-05-27 | 2012-11-20 | Advanced Micro Devices, Inc. | Arithmetic processing unit that performs multiply and multiply-add operations with saturation and method therefor |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1031073B1 (en) * | 1997-10-23 | 2003-09-24 | Advanced Micro Devices, Inc. | A method and apparatus for multi-function arithmetic |
| GB2367659A (en) * | 2000-10-04 | 2002-04-10 | Advanced Risc Mach Ltd | SIMD saturation instruction with variable bit length |
| FR2835938A1 (en) * | 2002-02-08 | 2003-08-15 | St Microelectronics Sa | HIGH-EFFICIENCY SATURANT OPERATOR |
-
2005
- 2005-11-28 JP JP2007543953A patent/JP2008522304A/en active Pending
- 2005-11-28 EP EP05825414A patent/EP1820092A2/en not_active Withdrawn
- 2005-11-28 CN CNA2005800411258A patent/CN101069152A/en active Pending
- 2005-11-28 WO PCT/IB2005/053929 patent/WO2006059267A2/en active Application Filing
Also Published As
| Publication number | Publication date |
|---|---|
| EP1820092A2 (en) | 2007-08-22 |
| WO2006059267A2 (en) | 2006-06-08 |
| JP2008522304A (en) | 2008-06-26 |
| WO2006059267A3 (en) | 2006-09-08 |
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