WO2006054412A1

WO2006054412A1 - Storage device employing electric double layer capacitor

Info

Publication number: WO2006054412A1
Application number: PCT/JP2005/019054
Authority: WO
Inventors: Harumi Takeda; Satoshi Tamazawa
Original assignee: Limited Company Tm; Takeda Technological Research Co., Ltd.
Priority date: 2004-11-18
Filing date: 2005-10-17
Publication date: 2006-05-26
Also published as: TW200627779A; JP2008035573A

Abstract

A storage device capable of supplying a stabilized voltage from a DC-AC converting means to a load even if the output voltage from a storage means is varied because an operation interruption control circuit controls a switch to supply the output voltage from an electric double layer capacitor (EDLC) unit to a DC-DC converter when the output voltage from the EDLC unit deviates from the allowable input voltage range of a DC-AC inverter and supplies DC output voltage from the DC-DC converter to the DC-AC inverter. When the output voltage from the EDLC unit falls within the allowable input voltage range of the DC-AC inverter, the switch is controlled to supply the output voltage from the EDLC unit to the DC-AC inverter and the DC-DC converter is brought into nonoperating state. Consequently, power loss incident to operation of a DC-DC converting means is reduced and power can be supplied efficiently to the load.

Description

Specification

Power storage device using electric double layer capacitor

Technical field

The present invention relates to a power storage device using an electric double layer capacitor.

Background art

[0002] In recent years, electric double layer capacitors have attracted attention as new storage devices that replace secondary batteries because of their long cycle life and wide operating temperature range. Patent Document 1). However, capacitors are generally used in series or series-parallel connection because the output voltage changes in proportion to the amount of stored charge, or because the output voltage of a single capacitor is low.

[0003] In order to supply a stable voltage to a load when capacitors are connected in series or series-parallel, a method of switching a plurality of electric double layer capacitors to a series or parallel connection using a complicated switch is often used. Has been.

Patent Document 1: Japanese Patent Laid-Open No. 07-135025 (Page 4-5, Fig. 4)

Disclosure of the invention

Problems to be solved by the invention

The present invention has been made in view of such circumstances, and an electric double layer capacitor capable of efficiently supplying a stable voltage to a load with a relatively simple configuration. It is a first object to provide the power storage device used. Also provided is a power storage device using an electric double layer capacitor that can reduce wasteful consumption of input energy due to forced discharge by an overcharge prevention means added to the electric double layer capacitor that has reached a predetermined voltage. This is the second purpose.

Means for solving the problem

In order to achieve such an object, the present invention has the following configuration.

That is, a power storage device using the electric double layer capacitor according to the invention of claim 1 includes a power storage means including an electric double layer capacitor, and a DC AC conversion that converts a DC input voltage into an AC output voltage and applies it to a load. And DC input voltage to DC / AC conversion means DC-DC conversion means that converts the output voltage to a DC output voltage within the allowable input voltage range, and the output path so that the output voltage of the storage means is supplied to either the DC / AC conversion means or the DC / DC conversion means! Switching means for switching between, and a control means for detecting the output voltage of the power storage means and controlling the switching means according to the voltage value, the output voltage of the power storage means is outside the allowable input voltage range of the DC-AC conversion means In some cases, the switching means is controlled to supply the output voltage of the power storage means to the DC / DC conversion means, and the DC output voltage of the DC / DC conversion means is supplied to the DC / AC conversion means, while the output voltage of the power storage means is When the input voltage of the DC / AC conversion means is within the allowable range, the switching means is controlled so that the output voltage of the power storage means is directly supplied to the DC / AC conversion means, and the DC / DC conversion means is in a non-operating state. Control means.

[0006] Operations and effects of the power storage device of the present invention are as follows. The control means monitors the output voltage of the power storage means and controls the switching means according to the voltage value as follows. That is, when the output voltage of the power storage means is outside the allowable input voltage range of the DC / AC conversion means, the switching means is controlled so that the output voltage of the power storage means is supplied to the DC / DC conversion means. The DC output voltage of the conversion means is given to the DC / AC conversion means. As a result, even if the output voltage of the storage means fluctuates, a constant DC output voltage is given to the DC / AC conversion means by the DC / DC conversion means, so that a stable voltage is supplied from the DC / AC conversion means to the load. can do.

[0007] On the other hand, when the output voltage of the power storage means is within the allowable input voltage range of the DC / AC conversion means, the control means switches the switching means so as to directly supply the output voltage of the power storage means to the DC / AC conversion means. In addition to controlling, the DC / DC converting means is put into a non-operating state, so that the power loss associated with the operation of the DC / DC converting means is reduced and power can be efficiently supplied to the load.

[0008] Furthermore, the power storage means comprises a plurality of electric double layer capacitor forces, and includes a plurality of overcharge prevention means connected in parallel to each electric double layer capacitor, each overcharge prevention means comprising: When the terminal voltage of the electric double layer capacitor corresponding to each becomes a predetermined voltage, the capacitor is forcibly discharged. In this case, each of the plurality of electric double layer capacitors is monitored by overcharge prevention means. Thus, even if there is a variation in capacitance between capacitors, all the capacitors can be fully charged.

[0009] Further, the power storage means includes a circuit configuration in which a plurality of electric double layer capacitors are connected in series, and each electric double layer capacitor of the power storage means includes a first Z switch that switches between energization and non-energization of the electric double layer capacitor. A short-circuit wire connected in series to each of the switches, connected in parallel to the electric double layer capacitor and the corresponding first switch, and a second switch for switching between energization and non-energization provided in the short-circuit wire. Detecting means for detecting the terminal voltage of each electric double layer capacitor, and the first means of the electric double layer capacitor detected by the detecting means to reach a predetermined voltage lower than the predetermined voltage at the overcharge preventing means. Power supply control means for switching the switch to de-energization and switching the second switch of the short-circuit wiring corresponding to the electric double layer capacitor to energization. It is preferred.

[0010] In this case, the energization control means de-energizes the first switch of the electric double layer capacitor that is detected by the detection means to have reached a predetermined voltage lower than the predetermined voltage of the overcharge prevention means. At the same time, since the second switch of the short-circuit wiring corresponding to the electric double layer capacitor is switched to energization, the electric double layer capacitor having a predetermined voltage can be electrically disconnected, and the electric The forced discharge by the overcharge prevention means added to the multilayer capacitor can be reduced, and the waste of input energy due to the forced discharge by the overcharge prevention means can be reduced. In addition, the charging time of other electric double layer capacitors (other electric double layer capacitors that are not separated) can be shortened.

[0011] Further, the energization control means, based on the terminal voltage detection of each electric double layer capacitor by the detection means, so that the output voltage of the power storage means is not less than the input lower limit voltage of the DC-DC conversion means, It is preferable that the first switch corresponding to the electric double layer capacitor that has reached the predetermined voltage lower than the predetermined voltage in the overcharge preventing means and the second switch of the short-circuit wiring are controlled to be switched.

[0012] In this case, the energization control means prevents the output voltage of the power storage means from being lower than the input lower limit voltage of the DC-DC conversion means based on the terminal voltage detection of each electric double layer capacitor by the detection means. Since the first switch corresponding to the electric double layer capacitor and the second switch of the short-circuit wiring are switched, the output of the power storage means is charged. The electric double layer capacitor that has become a predetermined voltage lower than the predetermined voltage in the overcharge prevention means can be electrically disconnected so that the force voltage does not fall below the input lower limit voltage of the DC-DC conversion means. The forced discharge by the overcharge prevention means added to the electric double layer capacitor that has become a voltage can be reduced, and the waste of input energy due to the forced discharge by the overcharge prevention means can be reduced. This also shortens the charging time of other electric double layer capacitors (other electric double layer capacitors that are not separated). When discharging, when the output voltage of the power storage means approaches the input lower limit voltage of the DC-DC conversion means, the charged and electrically disconnected electric double layer capacitor is connected again, and the power storage means Can increase the output voltage.

The present specification also discloses the following means for solving problems.

Power storage means comprising an electric double layer capacitor;

DC / AC conversion means for converting the DC input voltage into AC output voltage and applying it to the load; DC / DC conversion means for converting the DC input voltage to a DC output voltage within the allowable input voltage range of the DC / AC conversion means;

Control means for detecting the output voltage of the power storage means and controlling the operation of the direct current to direct current conversion means according to the voltage value;

The direct current to direct current conversion means is a boosting chiba type direct current direct current conversion circuit comprising the following components (a) to (d):

(a) an inductance having one end connected to the power storage means side;

(b) a diode having an anode connected to the other end of this inductance and a force sword connected to the DC / AC converter stage side;

(c) a capacitor interposed between the power sword of this diode and the ground line;

(d) a switching transistor interposed between the anode of the diode and the ground line,

When the output voltage of the power storage means is lower than the input voltage allowable range of the DC / AC conversion means, the control means gives a pulse signal of a predetermined frequency to the gate of the switching transistor of the DC / DC conversion means to When the conversion means is activated and the output voltage of the storage means is within the allowable input voltage range of the DC / AC conversion means, the switch Stops the no-less signal applied to the gate of the switching transistor and maintains the switching transistor in the off state.

A power storage device using an electric double layer capacitor.

[0014] According to the above problem solving means, when the output voltage of the power storage means is lower than the allowable input voltage range of the DC / AC conversion means, the control means operates the DC / DC conversion means, The output voltage of the means is boosted and provided to the DC / AC conversion means. As a result, a stable voltage can be supplied to the DC / AC conversion means load. On the other hand, when the output voltage of the storage means is within the allowable input voltage range of the DC / AC conversion means, the control means stops the pulse signal applied to the gate of the switching transistor and maintains the switching transistor in the OFF state. Is output to the DC-AC conversion means as it is through the inductance and the diode. During this time, the loss is essentially only the amount of diode passing, and the efficiency can be increased compared to when the operation stop control is not performed.

The invention's effect

[0015] According to the power storage device of the present invention, when the output voltage of the power storage means is outside the allowable input voltage range of the DC / AC conversion means, the output voltage of the power storage means is changed to DC / AC via the DC / DC conversion means. Since the voltage is applied to the conversion means, a stable voltage can be supplied to the load even if the output voltage of the power storage means varies. On the other hand, when the output voltage of the storage means is within the allowable input voltage range of the DC / AC conversion means, the output voltage of the storage means directly through the DC-DC conversion means is directly applied to the DC / AC conversion means. The power loss associated with the operation of the conversion means is reduced, and power can be efficiently supplied to the load.

Brief Description of Drawings

FIG. 1 is a block diagram showing an embodiment of a power storage device according to the present invention.

FIG. 2 is a circuit diagram of a parallel monitor circuit group.

FIG. 3 is a diagram for explaining the operation of the parallel monitor circuit.

FIG. 4 is a block diagram showing a configuration of an example apparatus.

FIG. 5 is a diagram for explaining operation stop control of a DC-DC converter. [Fig. 6] A diagram showing the difference in efficiency depending on whether or not DC-DC converter operation is stopped.

FIG. 7 is a diagram showing a circuit configuration of an EDLC portion of the EDLC unit of Embodiment 2.

FIG. 8 is a diagram for explaining disconnection of a fully charged electric double layer capacitor (EDLC).

FIG. 9 is a block diagram showing a main configuration of an EDLC unit according to a second embodiment.

FIG. 10 is a diagram illustrating the detection of the voltage between terminals of the EDLC of Example 2.

[11] FIG. 11 is a diagram illustrating the detection of the voltage between terminals of each EDLC in Example 2.

FIG. 12 is a diagram for explaining disconnection of a fully charged electric double layer capacitor (EDLC). Explanation of symbols

10… Power storage device body

10A… livestock

10B '… Power converter

11… DC current source

12… Load

13… EDLC unit

14… Parallel monitor circuit group

14A… Parallel monitor circuit

15… Resistance

16… Field-effect transistor

17… Discharge control circuit

18… DC—AC inverter

19… DC—DC converter

20… off

21… Operation stop control circuit

22… Inductance

23… Diode

24… Capacitor

25… Switching transistors BEST MODE FOR CARRYING OUT THE INVENTION

[0018] In a power storage device using an electric double layer capacitor, the control means detects the output voltage of the power storage means and controls the switching means according to the voltage value, and the output voltage of the power storage means is DC-AC converted. When the input voltage is outside the allowable input voltage range, the switching means is controlled to supply the output voltage of the power storage means to the DC / DC conversion means, and the DC output voltage of the DC / DC conversion means is supplied to the DC / AC conversion means. On the other hand, when the output voltage of the storage means is within the allowable input voltage range of the DC / AC conversion means, the switching means is controlled so that the output voltage of the storage means is directly supplied to the DC / AC conversion means, and the DC / DC conversion is performed. And a control means for bringing the means into a non-operating state by using an electric double layer capacitor capable of efficiently supplying a stable voltage to the load with a relatively simple configuration. Realized the purpose of providing a power storage device.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a power storage device using the electric double layer capacitor according to the present invention.

The power storage device body 10 stores the DC power supplied from the DC current source 11, converts it into AC power, and supplies it to the load 12.

[0021] The DC current source 11 as an external device is composed of, for example, a solar cell, a wind power generator, an engine generator, or the like.

[0022] The power storage device body 10 is broadly provided with a power storage unit 10A and a power conversion unit 10B that converts direct current power stored in the power storage unit 10A into AC power.

First, the power storage unit 10A will be described. The power storage unit 10A includes an EDLC unit 13 composed of an electric double layer capacitor (EDLC) and a parallel monitor circuit group 14 connected thereto.

[0024] The EDLC unit 13 is also configured with a plurality of electric double layer capacitor forces. For example

It consists of 6 series and 2 parallel electric double layer capacitors with a capacitance of 3500F and a withstand voltage of 2.3V. The EDLC unit 13 corresponds to the power storage means in the present invention.

As shown in FIG. 2, the parallel monitor circuit group 14 includes a plurality of parallel monitor circuits 14A, 14B connected in parallel to the electric double layer capacitors CAP1, CAP2,... Constituting the EDLC unit 13, respectively. It is composed of ... Each parallel monitor circuit 14A, 14B is the same Since it is configured, the parallel monitor circuit 14A will be described below as an example.

[0026] The parallel monitor circuit 14A includes a resistor 15 and a field effect transistor (FET) 16 connected in series. The discharge path bypasses both terminals of the capacitor CAP1, and the discharge control circuit 17 controls the opening and closing of the discharge path. It consists of and. The discharge control circuit 17 monitors the terminal voltage of the capacitor CAP1, and when this terminal voltage exceeds the predetermined voltage (withstand voltage of the electric double layer capacitor), a control signal is given to the FET 16 to make it conductive. Capacitor CAP1 is forcibly discharged with the discharge path closed. Each parallel monitor circuit 14A, 14 、, ... prevents the corresponding electric double layer capacitors CAP1, CAP2, ... from falling into overcharge. Each of the parallel monitor circuits 14A, 14B,... Corresponds to the overcharge prevention means in the present invention.

Furthermore, with reference to FIG. 3, the functions of the parallel monitor circuits 14, 14,... During the charging operation will be described. FIG. 3 shows changes in the terminal voltage during the charging operation of the 12 electric double layer capacitors (CAP1 to CAP12) constituting the EDLC unit 13. According to the standard, even if an electric double layer capacitor has the same capacity, the charging time varies depending on the capacitor because the capacity actually varies. Therefore, even if one capacitor is fully charged, the other capacitor may not be fully charged. Therefore, as described above, by providing a parallel monitor circuit for all capacitors, all capacitors that do not end charging all capacitors when one capacitor reaches full charge are fully charged. be able to.

Next, the configuration of the power conversion unit 10B will be described. As shown in FIG. 1, the power converter 10B includes a direct current alternating current (DC—AC) inverter 18, a direct current direct current (DC—DC) converter 19, a switch 20, and an operation stop control circuit 21. . DC—AC inverter 18 converts the DC input voltage to AC output voltage and applies it to load 12. The DC-DC converter 19 converts the DC input voltage into a DC output voltage within the input voltage allowable range (for example, 10 to 15 V) of the DC-AC inverter 18. The switch ^^ 20 switches the output path so that the output voltage of the EDLC unit 13 is supplied to one of the DC—AC inverter 18 and the DC—DC converter 19. The operation stop control circuit 21 detects the output voltage of the EDLC unit 13 and controls switching according to the voltage value. That is, the operation stop control circuit 21 (control means) When the output voltage of the LC unit 13 is outside the allowable input voltage range of the DC—AC inverter 18, the switch 20 is controlled so that the output voltage of the EDLC unit 13 is supplied to the DC-DC converter 19, and the DC — When the DC output voltage of DC converter 19 is applied to DC—AC inverter 18 while the output voltage of EDLC unit 13 is within the allowable input voltage range of DC—AC inverter 18, the output voltage of EDLC unit 13 is set to DC— The switch is controlled so that it is supplied directly to the AC inverter 18 and the DC-DC converter 19 is made non-operating.

[0029] The DC-AC inverter 18 is a DC / AC converter in the present invention, the DC-DC converter 19 is a DC-DC converter in the present invention, and the switch is a switch in the present invention. 21 corresponds to the control means in the present invention.

Next, the operation of the apparatus shown in FIG. 1 (particularly the operation related to power conversion) will be described. The operation stop control circuit 21 monitors the output voltage of the EDLC unit 13, and when the output voltage is lower than the allowable input voltage range of the DC-AC inverter 18 (for example, 10 to 15V), the operation stop control circuit 21 Turn off 20 to supply output voltage to DC-DC converter 19. As a result, the output voltage of the EDLC unit 13 is boosted by the DC-DC converter 19 to a predetermined voltage (for example, 12.5 V) within the allowable input voltage range of the DC-AC inverter 18. The output voltage of the DC—DC converter 19 applied to the DC—AC inverter 18 is converted into an alternating voltage by the DC—AC inverter 18 and supplied to the load 12. Thus, even if the output voltage of the EDLC unit 13 is lower than the input voltage allowable range of the DC-AC inverter 18, it is boosted to a predetermined voltage by the DC-DC converter 19 and applied to the DC-AC inverter 18. Therefore, a stable voltage can be supplied from the DC-AC inverter 18 to the load 12.

On the other hand, when the output voltage of the EDLC unit 13 is within the input voltage allowable range of the DC—AC inverter 18, the operation stop control circuit 21 supplies the output voltage of the EDLC unit 13 to the DC—AC inverter 18. In this way, the switching 20 is controlled, and the DC-DC converter 19 is put into a non-operating state. As a result, the output voltage of the EDLC unit 13 is directly applied to the DC-AC inverter 18 to be converted into an AC voltage and supplied to the load 12. ED like this When the output voltage of the LC unit 13 is within the allowable input voltage range of the DC-AC inverter 18, the DC-DC converter 19 becomes non-operational, so the power loss associated with the operation of the DC-DC converter 19 is reduced. Thus, power can be efficiently supplied to the load.

Example 1

Hereinafter, an embodiment of the present invention will be described with reference to FIG. This embodiment shows a specific example of the DC-DC converter 19 and the switch 20 in the apparatus shown in FIG. The other configuration is the same as that of the apparatus shown in FIG. 1, and a description thereof is omitted here.

[0033] The DC-DC converter 19 of this embodiment is a step-up hopper type DC-DC converter, and also has a function as a cut-off, as will be apparent from the following description.

[0034] Specifically, the DC-DC converter 19 has an inductance 22 connected to the DLC unit 13 side at one end, an anode connected to the other end of the inductance 22, and a power sword connected to the DC-AC inverter 18 side. A diode 23 connected to the capacitor 23, a capacitor 24 interposed between the power sword of the diode 23 and the ground line, and a switching transistor (FET) 25 interposed between the anode of the diode 23 and the ground line. Yes. Then, a control signal is given to the gate of the switching transistor 25 from the operation stop control circuit 21.

Next, the operation of the embodiment apparatus will be described. Similar to the device shown in Fig. 1, the operation stop control circuit 21 monitors the output voltage of the EDLC unit 13, and when the output voltage is lower than the allowable input voltage range of the DC-AC inverter 18, A pulse signal (operation control signal) with a predetermined frequency is applied to the gate of transistor 25. As a result, the DC-DC converter 19 is activated, and the output voltage of the EDLC unit 13 is boosted and applied to the DC-AC inverter 18. As described above, the DC-DC converter 19 is operated by the control signal from the operation stop control circuit 21 to boost the output voltage of the EDLC unit 13 from the operation stop control circuit 21 in the apparatus of FIG. This is equivalent to controlling the switcher 20 by the control signal and supplying the output voltage of the EDLC unit 13 to the DC-DC converter 19.

On the other hand, in the embodiment apparatus of FIG. 4, when the output voltage of the EDLC unit 13 is within the input voltage allowable range of the DC—AC inverter 18, the operation stop control circuit 21 is connected to the gate of the switching transistor 25. Stop the pulse signal applied to the switching transistor 25 Keep it off. Then, the DC-DC converter 19 is stopped, and is supplied to the DC-AC inverter 18 as it is through the output voltage force inductance 22 and the diode 23 of the ED LC unit 13. The loss during this period is substantially only the passage of the diode 23, and the efficiency is increased as compared with the case where the operation stop control is not performed. In this way, the control signal from the operation stop control circuit 21 disables the DC-DC converter 19 and applies the output voltage of the EDLC unit 13 to the DC-AC inverter 18 as it is. In this case, the switch 20 is controlled by the control signal from the operation stop control circuit 21 to supply the output voltage of the EDLC unit 13 to the DC-AC inverter 18 and DC.

— Equivalent to setting the DC converter 19 to the non-operating state.

[0037] In order to confirm the usefulness of the apparatus of the embodiment of FIG. 4, the following measurements were performed. First, the EDLC unit 13 was charged with no load. When all the electric double layer capacitors reached full charge, charging was stopped, and a discharge was started by connecting a 10 W incandescent lamp load. The measurement was completed when the stored voltage fell below the operating voltage range (4V) of the DC-DC converter 19. This experiment was measured with and without the DC-DC converter 19 operation stop control when the output voltage of the EDLC unit 13 entered the DC-AC inverter 18 input voltage range. Went. Measurement results when operation stop control is performed (DC

— Output voltage of DC converter 19) is shown in Fig. 5. When the output voltage of the EDLC unit 13 is lower than the input voltage range of the DC-AC inverter 18, the output voltage of the EDLC unit 13 is boosted by the DC-DC converter 19 to output a substantially constant DC voltage, When the output voltage of the EDLC unit 13 is within the input voltage range of the DC—AC inverter 18, it can be seen that the output voltage force of the EDLC unit 13 is almost output from the DC—DC converter 19 (non-operating state). .

[0038] In the above-described experiment, the efficiency when the operation stop control of the DC-DC converter 19 is performed and when the operation is not performed are measured. The result is shown in Fig. 6. Here, the input voltage and input current of the DC-DC converter 19 and the output voltage and output current were measured, and the efficiency was calculated from the power of the input and output. As can be seen from the results shown in Fig. 6, when the operation stop control functioned most effectively, an efficiency improvement of up to about 5% was obtained.

[0039] Further, the discharge when the operation stop control of the DC-DC converter 19 is performed and when it is not performed. The depth was compared. The depth of discharge indicates how much power stored in the electric double layer capacitor can be used. In this experiment, the output voltage of the EDLC unit 13 is lower than the operating voltage lower limit (4V) of the DC-DC converter 19. It can be obtained by measuring the voltage across the terminals of each electric double layer capacitor when the system stops operating.

The depth of discharge of each electric double layer capacitor is calculated using the following formula:

Depth of discharge (%) = [i-(v ² / V ² )] X 100

1 2

V: DC—below the DC converter 19 operating voltage lower limit (4V), and the equipment stops operating.

1

Terminal voltage of each electric double layer capacitor at the time

V: Electric double layer capacitor withstand voltage (full charge voltage)

2

It can ask for.

[0040] The depth of discharge when the DC-DC converter 19 is stopped is as high as 89%. It was confirmed that the electric power stored in the electric double layer capacitor can be used effectively. This value is high when considering that the discharge depth is about 40% when the output voltage of the EDLC unit 13 is directly applied to the DC-AC inverter 18 with the DC-DC converter 19 used. It is a power to be a value.

Example 2

[0041] In the power storage device of Example 1, the power storage means includes a circuit configuration in which a plurality of electric double layer capacitors are connected in series, and each electric double layer capacitor of the power storage means is energized to the electric double layer capacitor. A first switch that switches energization is connected in series to each other, and the short circuit wiring connected in parallel to the electric double layer capacitor and the corresponding first switch, and the energization Z de-energization provided in the short circuit wiring The second switch to be switched, the detection means for detecting the terminal voltage of each electric double layer capacitor, and the electric double layer detected by the detection means as having reached a predetermined voltage lower than the predetermined voltage at the overcharge prevention means Energization control to switch the first switch of the capacitor to de-energization and to switch the second switch of the short-circuit wiring corresponding to the electric double layer capacitor to energization Using an electric double layer capacitor that can reduce waste of input energy due to forced discharge by means of an overcharge prevention means added to the electric double layer capacitor that has reached a predetermined voltage. The second objective of providing power storage devices was realized. [0042] In Example 1 described above, the effectiveness of the technique of Example 1 was shown. In other words, we showed a method that can supply a stable voltage efficiently to a load with a relatively simple configuration. However, the results of Fig. 3 show that in the charging process of each of the 12 electric double layer capacitors CAP1, CAP2, ..., CAP12, due to variations in the capacitance of these capacitors (capacitors), they are fully charged. The time required to reach the difference is different for each capacitor.

[0043] That is, until the capacitor having a large capacitance reaches full charge, the parallel monitor circuit added to the capacitor having small capacitance that has already reached full charge operates and forced discharge is performed. It can be seen that overcharging is prevented. In other words, during this time, the input energy is wasted due to the resistance.

[0044] Therefore, in order to accumulate input energy more efficiently, an electric double layer capacitor (EDLC) with as little capacitance error as possible should be used. It is not practical to construct a device because it leads to waste of time and cost for measuring capacitance. In particular, it takes a lot of time to accurately measure the capacitance of a large-capacity electric double layer capacitor used when constructing a large-capacity power storage device.

[0045] The second embodiment solves this problem and is configured as follows, for example.

Hereinafter, Embodiment 2 of the present invention will be described with reference to FIGS. FIG. 7 is a diagram illustrating a circuit configuration of the EDLC portion of the EDL C unit according to the second embodiment. Fig. 8 is a diagram illustrating the separation of a fully charged electric double layer capacitor (EDLC). FIG. 9 is a block diagram showing a main configuration of the EDLC unit according to the second embodiment. FIG. 10 is a diagram for explaining the detection of the voltage between the terminals of the EDLC of the second embodiment. FIG. 11 is a diagram for explaining the detection of the voltage between terminals of each EDLC of the second embodiment. Fig. 12 is a diagram illustrating the separation of a fully charged electric double layer capacitor (EDLC).

This Example 2 shows a specific example of the EDLC unit 13 in the apparatus shown in FIG.

. Other configurations are the same as those of the apparatus shown in FIG.

[0048] As shown in FIG. 7, the EDLC unit 13 includes a plurality (n) of electric double layer capacitors CAP. 1, CAP2, ... Includes a circuit configuration in which CAPn is connected in series. Each electric double layer capacitor CAP1, CAP2, ..., CAPn is a switch Sl, S2, ..., Sn for switching between energization Z to non-energization of its own electric double layer capacitor. Yes. That is, switch S1 is connected in series to electric double layer capacitor CAP1, switch S2 is connected in series to electric double layer capacitor CAP2, and so on.

[0049] In addition, electric double layer capacitors CAP1, CAP2, ..., CAPn and corresponding switches Sl, S2, ..., short-circuit wiring for each set of Sn, hl, h2, ..., hn are connected in parallel. That is, the shorting wiring hi is connected in parallel to the set of the electric double layer capacitor CAP1 and the corresponding switch S1, and the shorting wiring h2 is connected to the set of the electric double layer capacitor CAP2 and the corresponding switch S2. Connected in parallel, and so on.

[0050] Each short-circuit wiring hl, h2, ..., hn is energized Z switches for switching between non-energized Sbl, Sb

2, ... Sbn are connected in series. That is, the switch Sb1 is connected in series to the short-circuit wiring hi, the switch Sb2 is connected in series to the short-circuit wiring h2, and so on.

That is, the EDLC unit 13 of the second embodiment includes a first stage block including an electric double layer capacitor CAP1 and a switch S1, a short-circuit wiring hi and a switch Sbl, an electric double layer capacitor CAP 2 and a switch S2. A second-stage block with a short-circuit wiring h2 and a switch Sb2, and an n-th block with an electric double layer capacitor CAPn and a switch Sn, a short-circuit wiring hn and a switch Sbn .

Furthermore, as shown in FIG. 9, the EDLC unit 13 includes a voltage detection circuit 30 for detecting the terminal voltages of the respective electric double layer capacitors CAP1, C ΑΡ2,..., CAPn, and this voltage detection circuit. The electric double layer capacitor CAPi switch that was detected as having reached the predetermined voltage (close to full charge) at 30 at lower than the predetermined voltage (full charge voltage) in the parallel monitor circuit (see Fig. 2) at 30 Si And a switching circuit 32 that switches the switch Sbi of the short-circuit wiring hi corresponding to the electric double layer capacitor CAPi to energization.

Further, as shown in FIG. 9, the switching circuit 32 is based on the detection of the terminal voltage of each electric double layer capacitor CAP1, CAP2,. Switch the switch Si corresponding to the electric double layer capacitor CAPi that has reached a voltage close to full charge and switch Sbi so that the output voltage of 3 does not fall below the input lower limit voltage of the DC-DC converter 19. Control.

Note that the switches Sl, S2,..., Sn are the first switch in the present invention, and the switches Sbl, Sb2,..., Sbn are the second switch in the present invention. Are equivalent to detection means in the present invention, and the switching circuit 32 corresponds to energization control means in the present invention.

[0055] The method of the second embodiment is such that the parallel monitor circuit (see Fig. 2) is not operated as much as possible. In other words, as shown in FIG. 7 (a), the EDLC unit 13 is configured, and the electric double layer capacitor CAPi that is almost fully charged is electrically disconnected from the EDLC unit 13.

That is, charging is started from a state in which all electric double layer capacitors CAP1, CAP2,..., CAPn are connected in series. Then, when charging proceeds, for example, when the voltage of the electric double layer capacitor CAP2 in the second stage block is close to full charge (withstand voltage), switch S2 is turned off and switch Sb2 is turned on as shown in Fig. 7 (b). By doing so, the electric double layer capacitor CAP2 with high inter-terminal voltage is temporarily electrically disconnected from the EDLC unit 13. In this way, the forced discharge by the parallel monitoring circuit added to the electric double layer capacitor CAP2 can cause unnecessary energy consumption and other electric double layer capacitors (other unseparated other capacitors). The charging time of the electric double layer capacitor) can be shortened.

[0057] Although the output voltage Vt of the EDLC unit 13 temporarily decreases by electrically disconnecting the electric double layer capacitor, in this method, the output voltage Vt is generally not supplied directly to the inverter. Actually, there is not much problem because a DC-DC converter with a low input lower limit voltage is used.

[0058] For example, some electric double layer capacitors have a capacitance error of about 20%, and this capacitance error is reflected in the voltage between terminals. Here, consider the worst condition. In other words, if there is a capacity error of ± 20% of the rating, when charged under the same conditions, the electric double layer capacitor whose capacitance is 20% smaller than the rating will reach full charge quickly, and the voltage between terminals will be the withstand voltage. 2 Suppose that it becomes 3 [V]. At that time, the voltage between the terminals of the electric double layer capacitor as rated is 1.91 [V], and the voltage between the terminals of the electric double layer capacitor whose capacitance is 20% larger than the rating is 1.53 [V].

[0059] Therefore, as shown in FIG. 8 (a), in a power storage device in which six electric double layer capacitors are connected in series and the input lower limit voltage of the DC-DC converter 19 is 4.0 [V], As shown in Fig. 8 (b), the three electric double layer capacitors whose capacitance is 20% lower than the rated value are close to full charge (withstand voltage) sooner than other electric double layer capacitors (2.3 [V ), And the output voltage Vt of the EDLC unit 13 is still the same even when the remaining three electric double layer capacitors are 20% larger than the rated value. 4. 59 [V] (1.53 [V] X 3), and the DC-DC converter 19 operates sufficiently.

[0060] If the output voltage Vt of the EDLC unit 13 is likely to be lower than the input lower limit voltage of the DC-DC converter 19, the disconnected electric double layer capacitor may be connected to the EDLC unit 13 again.

[0061] In order to realize the above method, it is necessary to measure the voltage between terminals of each electric double layer capacitor. For this purpose, the voltage between terminals of each electric double layer capacitor may be obtained by using AD conversion, but a transformer may be used as shown in FIG. In FIGS. 9 and 12, the parallel monitor circuit is not shown.

For example, as shown in FIG. 10, when the switch S is turned on and off by the switch control circuit 31,

si

The secondary coil of switch S is connected to the voltage across the terminals of the electric double layer capacitor CAPi.

si

The example voltage is generated.

Therefore, as shown in FIG. 11, by sequentially turning on and off the switches S to S,

sl sn

The voltage detection circuit 30 can measure the voltage between the terminals of the electric double layer capacitors CAPl to CAPn. Furthermore, the switching circuit 32 detects the electric double layer capacitor CAPi that is close to full charge (withstand voltage) based on the measurement value of the voltage detection circuit 30, and switches the switches S and S to switch the target electric circuit. Double layer capacitor CAPi EDLC unit

Electrically disconnected from 13 Note that if there are multiple electric double layer capacitors CAPi that are close to full charge (withstand voltage), the output voltage of the EDLC unit 13 is limited to the input lower limit voltage of the DC-DC converter 19. Electrical from unit 13 Disconnect.

[0064] For example, when the electric double layer capacitor CAP2 of the second stage block approaches full charge (withstand voltage), the connection is made as shown in FIG. 12 (a). Fig. 12 (b) shows the equivalent of Fig. 12 (a) for easier viewing. In other words, unnecessary circuits are deleted in Fig. 12 (b).

[0065] By doing this, input energy is not wasted by forced discharge by the parallel monitor circuit (see Fig. 2) attached to the electric double layer capacitor with small electrostatic capacity that has already reached full charge. In addition, the capacitance of the electric double layer capacitor can be charged, and the charging time can be shortened.

That is, according to the apparatus of the second embodiment, the switching circuit 32 detects that the voltage detection circuit 30 has reached a predetermined voltage lower than the predetermined voltage in the parallel monitor circuit (see FIG. 2). Switch of electric double layer capacitor CAPi is switched to de-energization, and switch Sbi of the short-circuit wiring hi corresponding to the electric double layer capacitor CAPi is switched to energization. The forced discharge by the parallel monitor circuit added to the electric double-layer capacitor CAPi that has reached the specified voltage can be reduced, and the forced discharge by the parallel monitor circuit reduces the wasted input energy. it can. However, the charging time of other electric double layer capacitors (other electric double layer capacitors that are not separated) can be shortened.

[0067] In addition, the switching circuit 32 is configured so that the output voltage of the EDLC unit 13 is input to the DC DC converter 19 based on the terminal voltage detection of each electric double layer capacitor CAP1, CAP2, ..., CAPn by the voltage detection circuit 30. Switch sbi of switch Si corresponding to electric double layer capacitor CAPi that has reached a predetermined voltage close to full charge and switch Sbi so that it does not fall below the lower limit voltage. The output voltage of 13 is lower than the specified voltage (full charge) in the parallel monitor circuit so that it does not fall below the DC DC converter 19 input lower limit voltage. The electric double layer capacitor CAPi can be electrically disconnected, and the forced discharge caused by the parallel monitor circuit added to the electric double layer capacitor CAR at the specified voltage can be reduced. Input energy in the control discharge can be reduced to be wasted. When charging other electric double layer capacitors (other electric double layer capacitors that are not separated) The time can be shortened. When discharging, when the output voltage of the EDLC unit 13 approaches the input lower limit voltage of the DC DC converter 19, the electric double layer capacitor CAPi that has been charged and electrically disconnected is connected again, and the EDLC unit The output voltage of 13 can be increased.

[0068] It should be noted that the energy required for coil switching and circuit switching is much smaller than the energy consumption due to resistance in the parallel monitor circuit.

[0069] The electric double layer capacitors shown in FIGS. 7 to 9 and 12 may be connected in parallel rather than one.

Industrial applicability

[0070] As described above, the present invention can more efficiently use the electric double layer capacitor.

In addition, since the configuration is relatively simple and complicated control is not required, it is advantageous in terms of maintenance and manufacturing costs. Note that the DC-DC converter becomes larger as the scale of power to be handled increases, so the present invention is particularly suitable for handling relatively small power.

Claims

The scope of the claims

[1] Power storage means comprising an electric double layer capacitor;

Switching means for switching the output path so that the output voltage of the storage means is supplied to one of the DC / AC conversion means and the DC / DC conversion means;

A control means for detecting the output voltage of the power storage means and controlling the switching means in accordance with the voltage value. When the output voltage of the power storage means is outside the allowable input voltage range of the DC / AC conversion means, the power storage means The switching means is controlled so that the output voltage is supplied to the DC / DC converter, and the DC output voltage of the DC / DC converter is supplied to the DC / AC converter, while the output voltage of the storage means is converted to DC / AC. When the input voltage is within the allowable voltage range, the switching means is controlled so that the output voltage of the storage means is supplied directly to the DC / AC converter, and the DC / DC converter is deactivated. And a power storage device using an electric double layer capacitor.

[2] In the device according to claim 1, the power storage means includes a plurality of electric double layer capacitor forces, and includes a plurality of overcharge prevention means connected in parallel to each electric double layer capacitor. Each of the overcharge prevention means is a power storage device using an electric double layer capacitor characterized by forcibly discharging the capacitor when the terminal voltage of the corresponding electric double layer capacitor reaches a predetermined voltage.

[3] In the device according to claim 2,

The power storage means includes a circuit configuration in which a plurality of electric double layer capacitors are connected in series, and each electric double layer capacitor of the power storage means has a first switch for switching between energization and non-energization of the electric double layer capacitor in series. Connected,

A short-circuit wiring connected in parallel to the electric double layer capacitor and the corresponding first switch;

A second switch that switches between energization and non-energization provided in the short-circuit wiring, a detection means that detects the terminal voltage of each electric double layer capacitor, and Switch the first switch of the electric double layer capacitor, which is detected by the detection means to have reached a predetermined voltage lower than the predetermined voltage at the overcharge prevention means, to the non-energized state, and connect the short circuit wiring corresponding to the electric double layer capacitor. Energization control means for switching the second switch to energization,

A power storage device using an electric double layer capacitor.

In the apparatus according to claim 3, the energization control means must be such that the output voltage of the power storage means is less than or equal to the input lower limit voltage of the DC-DC conversion means based on the terminal voltage detection of each electric double layer capacitor by the detection means. As described above, the first switch corresponding to the electric double layer capacitor that has reached the predetermined voltage lower than the predetermined voltage in the overcharge prevention means and the second switch of the short-circuit wiring are switched and controlled. A power storage device using an electric double layer capacitor characterized by the following.