WO2006053036A3 - Trous traversants non circulaires pour former des bossages sur des plages de connexion et des structures associees - Google Patents

Trous traversants non circulaires pour former des bossages sur des plages de connexion et des structures associees Download PDF

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Publication number
WO2006053036A3
WO2006053036A3 PCT/US2005/040584 US2005040584W WO2006053036A3 WO 2006053036 A3 WO2006053036 A3 WO 2006053036A3 US 2005040584 W US2005040584 W US 2005040584W WO 2006053036 A3 WO2006053036 A3 WO 2006053036A3
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WO
WIPO (PCT)
Prior art keywords
conductive pad
conductive
substrate
hole
via holes
Prior art date
Application number
PCT/US2005/040584
Other languages
English (en)
Other versions
WO2006053036A2 (fr
Inventor
William E Batchelor
Glenn A Rinne
Original Assignee
Unitive Int Ltd
William E Batchelor
Glenn A Rinne
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Unitive Int Ltd, William E Batchelor, Glenn A Rinne filed Critical Unitive Int Ltd
Publication of WO2006053036A2 publication Critical patent/WO2006053036A2/fr
Publication of WO2006053036A3 publication Critical patent/WO2006053036A3/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
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    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
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    • H01L2924/01023—Vanadium [V]
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    • H01L2924/01028—Nickel [Ni]
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    • H01L2924/01033—Arsenic [As]
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    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
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    • H01L2924/013—Alloys
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

L'invention concerne un dispositif à circuit intégré qui peut comprendre un substrat, une plage conductrice disposée sur une surface du substrat et une ligne conductrice disposée sur la surface du substrat. De plus, la ligne conductrice peut être connectée à la plage conductrice et la ligne conductrice peut être étroite par rapport à la plage conductrice. De plus, une couche isolante peut être appliquée sur le substrat, sur la ligne conductrice et sur des parties périphériques de la plage conductrice. La couche isolante peut être pourvue d'un trou qui laisse à découvert une partie centrale de la plage conductrice et un premier segment d'un périmètre du trou peut être sensiblement définir un arc de cercle autour de la partie centrale de la plage conductrice. Un second segment du périmètre du trou peut dévier sensiblement du cercle entourant la partie centrale de la plage conductrice et le second segment du périmètre du trou peut être adjacent à une connexion entre la ligne conductrice et la plage conductrice.
PCT/US2005/040584 2004-11-10 2005-11-08 Trous traversants non circulaires pour former des bossages sur des plages de connexion et des structures associees WO2006053036A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US62680204P 2004-11-10 2004-11-10
US60/626,802 2004-11-10

Publications (2)

Publication Number Publication Date
WO2006053036A2 WO2006053036A2 (fr) 2006-05-18
WO2006053036A3 true WO2006053036A3 (fr) 2006-07-06

Family

ID=35897955

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/040584 WO2006053036A2 (fr) 2004-11-10 2005-11-08 Trous traversants non circulaires pour former des bossages sur des plages de connexion et des structures associees

Country Status (2)

Country Link
TW (1) TW200629512A (fr)
WO (1) WO2006053036A2 (fr)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7795134B2 (en) 2005-06-28 2010-09-14 Micron Technology, Inc. Conductive interconnect structures and formation methods using supercritical fluids
US7830018B2 (en) 2007-08-31 2010-11-09 Micron Technology, Inc. Partitioned through-layer via and associated systems and methods
US7863187B2 (en) 2005-09-01 2011-01-04 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US7973411B2 (en) 2006-08-28 2011-07-05 Micron Technology, Inc. Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods
US8322031B2 (en) 2004-08-27 2012-12-04 Micron Technology, Inc. Method of manufacturing an interposer
US8536485B2 (en) 2004-05-05 2013-09-17 Micron Technology, Inc. Systems and methods for forming apertures in microfeature workpieces
US9209158B2 (en) 2007-12-28 2015-12-08 Micron Technology, Inc. Pass-through 3D interconnect for microelectronic dies and associated systems and methods
US9214391B2 (en) 2004-12-30 2015-12-15 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
US9343368B2 (en) 2008-05-15 2016-05-17 Micron Technology, Inc. Disabling electrical connections using pass-through 3D interconnects and associated systems and methods

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8084866B2 (en) 2003-12-10 2011-12-27 Micron Technology, Inc. Microelectronic devices and methods for filling vias in microelectronic devices
US7232754B2 (en) 2004-06-29 2007-06-19 Micron Technology, Inc. Microelectronic devices and methods for forming interconnects in microelectronic devices
US7300857B2 (en) 2004-09-02 2007-11-27 Micron Technology, Inc. Through-wafer interconnects for photoimager and memory wafers
US7262134B2 (en) 2005-09-01 2007-08-28 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US7749899B2 (en) 2006-06-01 2010-07-06 Micron Technology, Inc. Microelectronic workpieces and methods and systems for forming interconnects in microelectronic workpieces
US7902643B2 (en) 2006-08-31 2011-03-08 Micron Technology, Inc. Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods
US7884015B2 (en) 2007-12-06 2011-02-08 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0194696A (ja) * 1987-10-06 1989-04-13 Ibiden Co Ltd プリント配線板
US5252781A (en) * 1991-05-31 1993-10-12 International Business Machines Corporation Substrate member having electric lines and apertured insulating film
US6232668B1 (en) * 1999-02-02 2001-05-15 Rohm Co. Ltd. Semiconductor device of chip-on-chip structure and semiconductor chip for use therein
US6617655B1 (en) * 2002-04-05 2003-09-09 Fairchild Semiconductor Corporation MOSFET device with multiple gate contacts offset from gate contact area and over source area
US20030218246A1 (en) * 2002-05-22 2003-11-27 Hirofumi Abe Semiconductor device passing large electric current
US20040023450A1 (en) * 2001-02-08 2004-02-05 Mitsuaki Katagiri Semiconductor integrated circuit device and its manufacturing method
US20040053483A1 (en) * 2002-06-25 2004-03-18 Nair Krishna K. Methods of forming electronic structures including conductive shunt layers and related structures
US20050012222A1 (en) * 2003-07-15 2005-01-20 Min-Lung Huang [chip structure]

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0194696A (ja) * 1987-10-06 1989-04-13 Ibiden Co Ltd プリント配線板
US5252781A (en) * 1991-05-31 1993-10-12 International Business Machines Corporation Substrate member having electric lines and apertured insulating film
US6232668B1 (en) * 1999-02-02 2001-05-15 Rohm Co. Ltd. Semiconductor device of chip-on-chip structure and semiconductor chip for use therein
US20040023450A1 (en) * 2001-02-08 2004-02-05 Mitsuaki Katagiri Semiconductor integrated circuit device and its manufacturing method
US6617655B1 (en) * 2002-04-05 2003-09-09 Fairchild Semiconductor Corporation MOSFET device with multiple gate contacts offset from gate contact area and over source area
US20030218246A1 (en) * 2002-05-22 2003-11-27 Hirofumi Abe Semiconductor device passing large electric current
US20040053483A1 (en) * 2002-06-25 2004-03-18 Nair Krishna K. Methods of forming electronic structures including conductive shunt layers and related structures
US20050012222A1 (en) * 2003-07-15 2005-01-20 Min-Lung Huang [chip structure]

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 013, no. 330 (E - 793) 25 July 1989 (1989-07-25) *

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8536485B2 (en) 2004-05-05 2013-09-17 Micron Technology, Inc. Systems and methods for forming apertures in microfeature workpieces
US8664562B2 (en) 2004-05-05 2014-03-04 Micron Technology, Inc. Systems and methods for forming apertures in microfeature workpieces
US8322031B2 (en) 2004-08-27 2012-12-04 Micron Technology, Inc. Method of manufacturing an interposer
US9214391B2 (en) 2004-12-30 2015-12-15 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
US7795134B2 (en) 2005-06-28 2010-09-14 Micron Technology, Inc. Conductive interconnect structures and formation methods using supercritical fluids
US7863187B2 (en) 2005-09-01 2011-01-04 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US7973411B2 (en) 2006-08-28 2011-07-05 Micron Technology, Inc. Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods
US7830018B2 (en) 2007-08-31 2010-11-09 Micron Technology, Inc. Partitioned through-layer via and associated systems and methods
US9209158B2 (en) 2007-12-28 2015-12-08 Micron Technology, Inc. Pass-through 3D interconnect for microelectronic dies and associated systems and methods
US9343368B2 (en) 2008-05-15 2016-05-17 Micron Technology, Inc. Disabling electrical connections using pass-through 3D interconnects and associated systems and methods

Also Published As

Publication number Publication date
TW200629512A (en) 2006-08-16
WO2006053036A2 (fr) 2006-05-18

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