WO2006036289A1

WO2006036289A1 - Image sensor

Info

Publication number: WO2006036289A1
Application number: PCT/US2005/027140
Authority: WO
Inventors: Mark W. Majette; Jack H. Schmidt
Original assignee: Hewlett-Packard Development Company, L.P.
Priority date: 2004-09-24
Filing date: 2005-07-29
Publication date: 2006-04-06
Also published as: TW200618609A; EP1813093A1

Abstract

An image sensor (104) includes offset dual arrays (202, 204, 206, 208, 210, 212) of photosensor pixels which are narrower along the arrays (202, 204, 206, 208, 210, 212) than across, and circuitry (300) configured for transferring charge from the photosensor pixels depending upon a level of resolution to be provided.

Description

Image Sensor

BACKGROUND

Various scanner mechanisms utilize sensor arrays. The providers of such mechanisms have sought in various ways to provide low cost (e.g., single lamp) scanners that can operate at different resolutions. For example, known charge coupled device (CCD) architectures provide a first set of square pixels and a second set of square pixels of a lower resolution. The second set of square pixels are used to for scanning at a lower resolution than with the first set. This approach, however, increases the area of silicon in the CCD which in turn increases the cost of the device.

Another approach would be to provide one or more arrays of square pixels that are sufficiently small in size to provide the highest scan resolution needed and to use multiple pixels for lower resolution modes of scanner operation. A problem with this approach, however, is that scanning is slower (for the same costs illumination and optics) because of the smaller size of the pixels.

Thus, it would be useful to be able to provide a sensor array that is both affordable and capable of providing multiple levels of resolution. It would also be useful to be able to provide a low cost (e.g., single lamp) scanner that meets the requirements for multiple resolution specifications. BRIEF DESCRIPTION OF THE DRAWINGS

Detailed description of embodiments of the invention will be made with reference to the accompanying drawings: FIG. 1 illustrates an example embodiment of a scanner apparatus;

FIG. 2 illustrates an example embodiment of a multiresolution pixel architecture;

FIG. 3 illustrates an example embodiment of a charge coupled device (CCD) circuit; FIG. 4 illustrates how pixels of offset dual arrays are sampled in an example 2400 dpi mode;

FIG. 5 illustrates a timing example for the 2400 dpi mode of FIG. 4; FIG. 6 illustrates how pixels of offset dual arrays are sampled in an example 1200 dpi mode; FIG. 7 illustrates a timing example for the 1200 dpi mode of FIG. 6;

FIG. 8 illustrates how pixels of offset dual arrays are sampled in an example 600 dpi mode;

FIG. 9 illustrates a timing example for the 600 dpi mode of FIG. 8; FIG. 10 illustrates how pixels of offset dual arrays are sampled in an example 300 dpi mode; and

FIG. 11 illustrates a timing example for the 300 dpi mode of FIG. 10.

DETAILED DESCRIPTION

The following is a detailed description for carrying out embodiments of the invention. This description is not to be taken in a limiting sense, but is made merely for the purpose of illustrating the general principles of the example embodiments of the invention.

The present invention generally involves providing a photosensor architecture that facilitates image sensing at multiple resolutions. In an example embodiment, an image sensor includes offset dual arrays of photosensor pixels which are narrower along the arrays than across and circuitry configured for transferring charge from the photosensor pixels depending upon a level of resolution to be provided.

Such image sensors can serve as components of scanner apparatuses and other systems. Referring to FIG. 1, in an example embodiment, a scanner apparatus 100 includes a scan module 102 which contains scanning components, namely, a scan module printed circuit assembly (PCA) 104, a scanline aperture 106, and a light source 108. The scan module 102 also contains mirrors and a lens (not shown) for folding an optical path and for forming an image of the object (e.g., document being scanned) onto a sensing apparatus on the scan module PCA 104. In this example, the scan module PCA 104 contains a sensing apparatus that includes CCDs (described below in greater detail) as well as associated electronic components for power and control signal transfer to and from the CCDs. The scan module PCA 104 connects to a system PCA 110 via a scan cable 112, e.g., a multi-conductor ribbon cable which carries signals needed for scanner operation.

The scanner apparatus 100 includes a housing 114 which supports the foregoing components as well as a scan area 116, e.g., a piece of glass upon which an object to be scanned is placed. The scan area 116 provides a focal plane (e.g., the top surface of the glass) for the scanner optics. The scanner apparatus 100 includes a motor and pulley assembly 118, a drive belt 120, and a slider rod 122 configured as shown. The motor and pulley assembly 118 is mechanically coupled to the scan module 102 by the drive belt 120. The slider rod 122 supports and guides the scan module 102 enabling the scan module 102 to move in a straight line along a scan axis 124. Under control of the system PCA 110, the motor and pulley assembly 118 repositions the scan module 102 in relation to the scan area 116. As the scan module 102 moves along arrow 126, an object positioned on the scan area 116 is scanned. In one line exposure, the scan module 102 moves a distance equal to the width (along the direction of the arrow 126) of a scan area 128. In this example embodiment, the scanline aperture 106 is an opening in the top of the scan module 102 through which the scanline image passes toward a first mirror of the optical path (not shown). In this example embodiment, the light source 108 (e.g., a cold cathode fluorescent lamp) spans and illuminates the width of the scan area 116. In this example embodiment, the scan module 102 includes an inverter (not shown) for converting a low voltage DC input to a high voltage AC lamp drive.

In this example embodiment, the scanner apparatus 100 includes a panel 130 (or other user input mechanism) for receiving inputs for scan, copy, etc. The scanner apparatus 100 can also include (or be operatively interfaced with) a computer 132 to facilitate receiving user inputs, image viewing, printing, etc. The system PCA 110 contains electronics for interfacing to user inputs from one or both of the panel 130 and the computer 132, controlling the motor and pulley assembly 118, the light source 108, and the scan module PCA 104 and its sensing apparatus, digitizing image data from the CCDs (or other sensing apparatus), and performing image processing for viewing on a monitor and/or printing. The computer 132 is configured for reading, storing and executing instructions from a computer-readable medium 134 (such as a CD-ROM). By way of example, such instructions can be used to control operation of the scan module PCA 104 and/or the system PCA 110. It should be appreciated that the various functionalities described for this example embodiment as being implemented via the scan module PCA 104 and the system PCA 110 can be migrated between the two, or remotely provided, depending upon the particular application. Further by way of example, the CCDs (or other sensing apparatus) can be controlled via a system application specific integrated circuit (ASIC), i.e., an onboard CPU operated by system firmware. In such an example, a sensor signal processor can provide a primary interface between the ASIC and the CCDs. By way of example, the sensor signal processor provides analog signal sampling, analog signal amplification and analog-to-digital (A/D) converter functionalities. Additional signals can be routed directly between the ASIC and the CCDs.

FIG. 2 illustrates an example embodiment of a multiresolution pixel architecture 200 suitable for the sensing apparatus of the scan module PCA 104 (FIG. 1). In this example embodiment, the multiresolution pixel architecture 200 includes three pairs of offset CCD photosensor arrays, filtered (e.g., to provide blue, green and red spectral responses, respectively) for three-color sensing. In this example embodiment, the photodetectors are arranged as shown in six one- dimensional arrays 202, 204, 206, 208, 210 and 212. This geometry has an analog on the object plane, or scan object, scaled up by the optical magnification of the scanner. In this example embodiment, each of the arrays 202, 204, 206, 208, 210 and 212 includes 21360 active pixels (the entire arrays are not shown in FIG. 2), which are 3 μm x 6 μm in size. In this example embodiment, the pixels have a rectangular shape, and the height of the rectangular shape (across the arrays) is approximately twice that of a width of the rectangular shape (along the arrays). It should be appreciated, however, that the principles of the present invention are not limited to rectangular shaped pixels or to pixels with this aspect ratio.

In this example embodiment, the dual arrays 202 and 204 are offset from each other by approximately one-half of a photosensor pixel width along the arrays. Likewise, the dual arrays 206 and 208 are offset from each other by approximately one-half of a photosensor pixel width along the arrays, and the dual arrays 210 and 212 are offset from each other by approximately one-half of a photosensor pixel width along the arrays. In this example embodiment, the distance (denoted "A") between the dual arrays 202 and 204 is approximately 18 μm, the distance (denoted "B") between the arrays 202 and 206 is approximately 72 μm, and the distance (denoted "C") spanning across the arrays 202 and 212 is approximately 168 μm. It should be appreciated, however, that the principles of the present invention are not limited to pairs of arrays that are offset by one-half of a pixel width. Nor are they limited to the distances between the arrays described above.

FIG. 3 illustrates an example embodiment of a charge coupled device (CCD) circuit 300 suitable for the scan module PCA 104 (FIG. 1). In this example embodiment, the CCD circuit 300 includes arrays of photodiodes 302, 304, 306, 308, 310 and 312, shift gates (or transfer gates) 314, 316, 318, 320, 322 and 324, CCD analog shift registers 326, 328, 330, 332, 334 and 336, and output stages 338, 340 and 342, which each include a capacitor and an amplifier, configured as shown. The input and output signals for the CCD circuit 300 are set forth in Table 1 (below).

Table 1. Pin Names

In operation, the photodiodes are allowed to accumulate charge in response to incident light for a time Tg, know as the transfer gate period. The charge is proportional to the amount of light and the Tg period. In this way, the page (or other scanned article) information is converted to electrical signals. The charge is then transferred from the entire array across the transfer gate into the shift registers. The signal which triggers this is the TG or SH signal. The photodiodes are cleared and begin a new charge accumulation cycle as a result of this as well. The shift register serves to store the charge from each photodiode and to transfer these sequentially to the output stage. The phi clocks φ are the signals that cause the charges to move through the shift register. The relationship between clock edges and charge transfer is described below. In FIG. 3, there are multiple phi clocks. These can be abstracted to a single clock signal to simplify the discussion. Thus, for each transition in the clock the charges shift one register towards the output capacitor. As the leading element of charge moves out of the array and into the capacitor, it is converted into a voltage and amplified by the amplifier into the output signal OS. The sensor signal processor samples the output voltage of the amplifier, amplifies it again, and digitizes it.

Between pixels, the capacitor is reset to a zero voltage level by the reset signal. However, the capacitor can be reset for each charge transfer, or only between every 2, 3, 4, or N transfers. When the capacitor is not reset between transfers, the charges from the related pixels are "added" in the capacitor to a voltage proportional to the sum of their charges. This is how "pixel lumping" according to various embodiments occurs. The array switch SW turns off the transfer from either the odd or even arrays to allow values to be shift only out of the other arrays.

Adjacent pixels are averaged in the voltage domain on the CCD itself through the pixel lumping process. At a specific time, the charge of all the sensors is transferred into a shift register, which can be thought of as a linear array of charge "buckets" in which the charge can be shifted from one bucket to the next. At the end of the array, the capacitor converts charge to voltage. In pixel lumping, successive buckets of charge are shifted into the output capacitor between samples, in effect combining the signal of adjacent photosensors.

Dual offset arrays as described herein provide a mechanism for sensing images at different levels of resolution depending upon how the pixels of the arrays are sampled. In various embodiments, the circuitry transfers charge from the photosensor pixels of both of the offset dual arrays in a higher resolution mode and from the photosensor pixels of only one of the offset dual arrays in a lower resolution mode. In various embodiments, the circuitry samples different numbers of successive photosensor pixels depending upon the level of resolution. In various embodiments, the circuitry is configured to sample a sufficient number of successive photosensor pixels to effectively sample a substantially square-shaped area.

With respect to FIGs. 5, 7, 9 and 11 discussed below, example timing (ns) is as follows: t1=1000, t2=50, t3=5000, t4=50, t5=5000, t6=50, t7=50, t8=20, t9=100, t10=20, t11=20, t12=20, t13=20, t14=500, and t15=25.

FIG. 4 illustrates how pixels of offset dual arrays are sampled in an example 2400 dpi mode, and FIG. 5 illustrates a timing example for the 2400 dpi mode. In FIG. 4, a section of lower (odd) and upper (even) arrays is shown. FIG. 5 shows the φ clocks, the reset signal, and the output signal. For each edge transition pair in the clocks there is a transition in the output signal. Here Ni is the voltage corresponding to pixel Ni. The signal is of negative polarity, meaning that the "no signal" level is the higher voltage immediately prior to the OS transition. The "zero" or black state of the output signal is a high voltage. Accumulation of signal causes this voltage level to decrease in proportion to the increasing signal, hence the term "negative polarity". This is inverted in the signal processor such that increasing signal level corresponds to increasing digital output. The signal processor measures the voltage difference across this transition. The reset signal causes the output signal to return to its "zero" value by clearing the output capacitor. The next pair of φ edges shift out pixel Ni+1. Thus, as shown in FIG. 4, the pixels are sequentially scanned in the order of: Ni, Ni+1 , Ni+2, Ni+3, Ni+4, Ni+5. The pixels are later recombined into a single row, e.g., in the system ASIC/CPU.

FIG. 6 illustrates how pixels of offset dual arrays are sampled in an example 1200 dpi mode, and FIG. 7 illustrates a timing example for the 1200 dpi mode. This example is the same as above except that the second RS pulse coincides with the φ clock edges. The charge from pixel Ni+1 is eliminated in the capacitor reset process immediately. In this way subsequent pixels in one array are shifted out. The SW signal to disable an array is unnecessary. Also, which 1200dpi array is used is controlled by the phase relationship of φ and RS. As shown in FIG. 6, in this example, the pixels of only the lower array are sequentially scanned in the order of: Ni, Ni+2, Ni+4.

FIG. 8 illustrates how pixels of offset dual arrays are sampled in an example 600 dpi mode, and FIG. 9 illustrates a timing example for the 600 dpi mode. In this example, the SW signal is used to turn off the even array. This is demonstrated in FIG. 9 by the absence of an OS response to the third pair of φ edges. The RS signal is used only after two shift cycles, resulting in the lumping of the charges from pixels Ni and Ni+2. On the page, this results in a square or substantially square 600dpi pixel. In a sense, this embodiment exploits the recombination of subdivided pixels.

FIG. 10 illustrates how pixels of offset dual arrays are sampled in an example 300 dpi mode, and FIG. 11 illustrates a timing example for the 300 dpi mode. This example is similar to the 600dpi example except that four shift cycles happen between RS's. Again, the sensor signal processor measures the voltage difference between the flat section before the Ni step and after the Ni+6 step, sampling a single voltage lumped from four adjacent pixels, Ni, Ni+2, Ni+4, Ni+6, in the odd array. The result is a pixel that is 1/300 inches wide by 1/600 inches tall on the page.

This pixel geometry provides the advantages of a multiresolution CCD without the expense of additional low resolution arrays. A smaller die area results which potentially lower costs. The additional area of the rectangular pixel, as compared to a square pixel, helps enable a single lamp design versus dual lamps, which also potentially lowers costs.

In an example embodiment, an image sensing method includes providing a resolution mode input, and for a pair of photosensor pixel arrays that are offset from each other in position along the arrays, sampling outputs of the photosensor pixel arrays depending upon the resolution mode input.

In an example embodiment, an image sensor apparatus includes photosensor elements with image sensing areas that are substantially rectangular in shape, and a mechanism for arranging the photosensor elements such that multiple image sensing resolutions can be provided via selective sampling of outputs of the photosensor elements.

In an example embodiment, an image sensor apparatus includes a charge-coupled device (CCD) including arrays of pixels which are arranged such that positions of the pixels of an adjacent pair of the arrays are offset from each other along the arrays, a height of the pixels across the arrays being greater than that of a width of the pixels along the arrays, and circuitry configured for transferring charge from the pixels depending upon a level of resolution to be provided by the image sensor apparatus.

Referring again to FIG. 1, the computer-readable medium 134 can be used to provide instructions for controlling sampling in response to a resolution mode input, e.g., provided by a user of the system via either the panel 130 or the computer 132. In an example embodiment, an image sensing control device includes a computer-readable medium storing instructions for a computer to provide a resolution mode input to circuitry for dual offset photosensor pixel arrays, and control the circuitry to sample outputs of the dual offset photosensor pixel arrays depending upon the resolution mode input. In an example embodiment, the computer-readable medium stores instructions for the computer to control the circuitry to sample outputs of both of the dual offset photosensor pixel arrays in a higher resolution mode. In an example embodiment, the computer-readable medium stores instructions for the computer to control the circuitry to sample outputs of only one of the dual offset photosensor pixel arrays in a lower resolution mode. In an example embodiment, the computer-readable medium stores instructions for the computer to control the circuitry to sample outputs of different numbers of successive photosensor pixels depending upon the resolution mode input. In an example embodiment, the computer-readable medium stores instructions for the computer to control the circuitry to sample outputs of successive photosensor pixels to effectively sample a substantially square-shaped pixel area.

In an example embodiment, a scanning system includes a housing supporting a scan area, arrays of photosensor elements, each of the arrays including image sensing areas that are substantially rectangular in shape and offset in position in relation to the image sensing areas of an adjacent array, a mechanism for repositioning the arrays in relation to the scan area, an optical path between the scan area and the photosensor elements, and a mechanism (e.g., circuitry) for selectively sampling outputs of the photosensor elements depending upon a selected imaging resolution mode. Although embodiments of the present invention have been described in terms of the example embodiments above, numerous modifications and/or additions to the above-described embodiments would be readily apparent to one skilled in the art. It is intended that the scope of the claimed subject matter extends to all such modifications and/or additions.

We claim:

Claims

1. An image sensor (104) comprising: offset dual arrays (202, 204, 206, 208, 210, 212) of photosensor pixels which are narrower along the arrays (202, 204, 206, 208, 210, 212) than across; and circuitry (300) configured for transferring charge from the photosensor pixels depending upon a level of resolution to be provided.

2. The image sensor (104) of claim 1 , wherein the photosensor pixels have a rectangular shape.

3. The image sensor (104) of claim 2, wherein a height of the rectangular shape across the arrays (202, 204, 206, 208, 210, 212) is approximately twice that of a width of the rectangular shape along the arrays (202, 204, 206, 208, 210, 212).

4. The image sensor (104) of claim 1, wherein the offset dual arrays (202, 204, 206, 208, 210, 212) are offset from each other by approximately one- half of a photosensor pixel width along the arrays (202, 204, 206, 208, 210, 212).

5. The image sensor (104) of claim 1, wherein the photosensor pixels are charge-coupled devices (CCD).

6. The image sensor (104) of claim 1 , wherein the circuitry (300) transfers charge from the photosensor pixels of both of the offset dual arrays (202, 204, 206, 208, 210, 212) in a higher resolution mode and from the photosensor pixels of only one of the offset dual arrays (202, 204, 206, 208, 210, 212) in a lower resolution mode.

7. The image sensor (104) of claim 1, wherein the circuitry (300) samples different numbers of successive photosensor pixels depending upon the level of resolution.

8. The image sensor (104) of claim 7, wherein the circuitry (300) samples two successive photosensor pixels.

9. The image sensor (104) of claim 7, wherein the circuitry (300) samples two successive photosensor pixels of only one of the offset dual arrays (202, 204, 206, 208, 210, 212).

10. The image sensor (104) of claim 7, wherein the circuitry (300) samples four successive photosensor pixels.

11. The image sensor (104) of claim 7, wherein the circuitry (300) samples four successive photosensor pixels of only one of the offset dual arrays (202, 204, 206, 208, 210, 212).

12. The image sensor (104) of claim 1, wherein the circuitry (300) is configured to sample a sufficient number of successive photosensor pixels to effectively sample a substantially square-shaped area.

13. The image sensor (104) of claim 1 , wherein the circuitry (300) is configured to combine the charge in a voltage domain.

14. The image sensor (104) of claim 1, wherein the circuitry (300) includes an output capacitor for converting charge to voltage.

15. The image sensor (104) of claim 14, wherein the circuitry (300) is configured to shift the charge into the output capacitor between samples.