WO2006035258A1 - Semiconductor chip assembly including stacked components and method for producing it - Google Patents

Semiconductor chip assembly including stacked components and method for producing it Download PDF

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Publication number
WO2006035258A1
WO2006035258A1 PCT/IB2004/003175 IB2004003175W WO2006035258A1 WO 2006035258 A1 WO2006035258 A1 WO 2006035258A1 IB 2004003175 W IB2004003175 W IB 2004003175W WO 2006035258 A1 WO2006035258 A1 WO 2006035258A1
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WO
WIPO (PCT)
Prior art keywords
tape
semiconductor chip
rewiring
contact areas
chip
Prior art date
Application number
PCT/IB2004/003175
Other languages
French (fr)
Inventor
Lee Hua Seah
Boon Kiat Alex Chew
Original Assignee
Infineon Technologies Ag
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Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Priority to PCT/IB2004/003175 priority Critical patent/WO2006035258A1/en
Publication of WO2006035258A1 publication Critical patent/WO2006035258A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/147—Structural association of two or more printed circuits at least one of the printed circuits being bent or folded, e.g. by using a flexible printed circuit
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L2224/05573—Single external layer
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
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    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
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    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0652—Bump or bump-like direct electrical connections from substrate to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
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    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06579—TAB carriers; beam leads
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/04—Assemblies of printed circuits
    • H05K2201/049—PCB for one component, e.g. for mounting onto mother PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10507—Involving several components
    • H05K2201/10515—Stacked components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/36—Assembling printed circuits with other printed circuits
    • H05K3/361—Assembling flexible printed circuits with other printed circuits
    • H05K3/363—Assembling flexible printed circuits with other printed circuits by soldering

Definitions

  • the invention relates to a semiconductor chip assembly, a stacked electronic component including the assembly and meth ⁇ ods for producing the assembly and electronic component.
  • One method by which the size of a package can be decreased is by mounting the chips on a substrate by a flip chip technique.
  • This technique is advantageous as both the height and lateral space required by a package including the flip chip contacts is less than that required by packages with wire bonds.
  • electrical contacting be ⁇ tween the chip and its substrate occurs in parallel for all the flip contacts rather than serially as for wire bonded chips. This increases manufacturing speeds and, therefore, re ⁇ cutes costs.
  • US 2002-074637 Al discloses an electronic component which in- eludes stacked semiconductor chip electrically connected by flip chip contacts.
  • Each semiconductor chip or die is provided with conductive redistribution traces both its active front and passive rear surfaces.
  • the conductive traces on the two opposing faces of each die are electrically connected by con- ductive tracks disposed on the side of the chip.
  • the manufac ⁇ turing process of such a stacked component is, therefore, com ⁇ plicated and expensive.
  • an object of the invention to provide a semiconductor chip assembly which enables the density of the integrated circuits to be increased within a package of a given size and which can be produced using more cost effective manufacturing methods.
  • a semiconductor chip assembly in- eludes a substrate board.
  • the substrate board typically com ⁇ prises a glass fibre matrix such as FR4 or BT and includes a redistribution structure.
  • the substrate board includes a plurality of first contact areas po ⁇ sitioned on the upper surface towards the lateral centre which are electrically connected by a plurality of first conductor tracks and a plurality of first vias to first outer contact areas positioned on the bottom surface of the substrate board to provide a first redistribution structure.
  • the substrate board further includes a plurality of second contact areas positioned on the upper surface towards the pe- riphery of the substrate board.
  • the second contact areas are electrically connected by second conductor tracks and second vias to second outer contact areas positioned on the bottom surface of the substrate board and provide a second redistri ⁇ bution structure.
  • the semiconductor chip assembly according to the invention also includes at least one semiconductor chip, including a plurality of chip contact areas on its active surface.
  • a first semiconductor chip is mounted in the lateral centre on the up- per surface of the substrate board by electrical connections between the chip contact areas and the first contact areas.
  • the lateral arrangement of the first contact areas on the upper surface of the substrate board corresponds to the lateral arrangement of the chip contact areas on the active surface of the chip.
  • the first semiconductor chip is mounted by a flip chip technique by a microscopic solder ball positioned between each chip contact pad and its corre ⁇ sponding contact area on the substrate board.
  • the first semi- conductor chip is thereby electrically connected to the first redistribution structure.
  • the semiconductor chip assembly according to the invention also includes a pre-formed intermediate rewiring tape.
  • the pre-formed intermediate rewiring tape includes third contact areas, positioned towards the centre of its upper surface, and fourth contact areas, positioned on the bottom surface towards the periphery.
  • the third and fourth contact areas are electri ⁇ cally connected by tape conductor tracks located in the centre of the intermediate rewiring tape and being positioned between and surrounded by between an upper and lower electrically in- sulating film.
  • the electrically insulating film preferably comprises polyimide and the conductor tracks preferably com ⁇ prise copper or a copper alloy.
  • a pre-formed intermediate rewiring structure pro- vides a simple cost effective method to provide a rewiring structure for the upper semiconductor chip in a stacked elec ⁇ tronic component, particularly for a semiconductor chip mounted using a flip chip technique as portions of the rewir ⁇ ing tracks can be positioned under the upper chip.
  • Electrical contacts to the intermediate rewiring structure and therefore the upper chip are advantageously provided in the periphery of the intermediate rewiring tape. This enables an easy reliable contact to the upper chip of the stack to be formed.
  • the pre-formed intermediate rewiring tapes are, preferably, fabricated in the form of a strip including a plurality of in ⁇ termediate rewiring tapes arranged along the length.
  • the in ⁇ termediate rewiring tapes are manufactured cost effectively using simple known techniques.
  • the pre-formed intermediate wiring tape further includes a re ⁇ cess surrounded by peripheral regions which protrude laterally outwards from the recess.
  • the recess is formed with a flat bottom and the laterally protruding regions lie in a plane ap ⁇ proximately parallel to that of the bottom of the recess.
  • the recess is formed over the whole width of the tape so that the laterally protruding regions extend on only two opposing sides of the recess. This has the advantage that the lateral size of the rewiring tape is reduced.
  • the fourth contact areas are therefore located in the protrud ⁇ ing region and the third contact areas in the central region.
  • the recess of the intermediate rewiring tape is mounted to the rear side of the first semiconductor chip, and the fourth con ⁇ tact areas of the intermediate rewiring tape are electrically connected to the second contact areas of the substrate board.
  • the fourth contact areas of the intermediate re ⁇ wiring tape have a lateral arrangement which corresponds to the lateral arrangement of the second contact areas of the substrate board.
  • the fourth and second connect areas are ad ⁇ vantageously electrically connected by a plurality of solder balls.
  • the contact areas on the upper and lower surface of the inter- mediate rewiring tape are provided by metallic contact pads positioned on metallic vias which are positioned through the upper and lower electrically insulating films. This method has the advantage that the lateral size of the vias and contact areas can be independently controlled.
  • the contact areas of the intermediate rewiring tape are provided by providing n appropriate arrangement of apertures in the electrically insulating films which expose the underlying conductor track. This method has the advantage that fewer masking and deposition steps are required.
  • the recess of the intermediate rewiring tape is attached to the rear side of the first semiconductor chip by adhesive.
  • the first semiconductor chip is, therefore, accommo ⁇ dated within the recess and the plane of the laterally out ⁇ wardly protruding regions lie in approximately the same plane as the active surface of the first semiconductor chip.
  • This arrangement of the pre-formed intermediate tape enables the rewiring tape to be attached directly to the rear side of the semiconductor chip without requiring an intermediate elec- trically insulating layer.
  • the production of the semiconductor chip assembly is simplified.
  • the intermediate rewiring tape includes tape con ⁇ ductor tracks on two or more electrically isolated inner lay- ers. This enables a more complex redistribution structure to be provided.
  • the flip chip contacts and the space between the active surface of the chip and the substrate are protected by underfill material. This protects the contact from corrosion due to moisture.
  • the semiconductor chips are also encapsulated by plastic mould material, the contacts between the intermediate rewiring foil and the substrate are encapsu ⁇ lated by plastic mould material.
  • the plastic mould material provides further mechanical protection for the electrical con ⁇ nections and protection from moisture penetration and, there ⁇ fore, corrosion of the contacts.
  • a stacked electronic component including the semiconductor as ⁇ sembly according to the invention further includes a second semiconductor chip mounted on the upper surface of the inter- mediate rewiring tape.
  • the lateral arrangement of the third contact areas on the upper surface of the intermediate rewiring tape corre ⁇ sponds to that of the chip contact areas on second semiconduc- tor chip.
  • the second semiconductor chip is, preferably, elec ⁇ trically connected to the rewiring tape by a flip chip tech ⁇ nique whereby microscopic solder balls are provided between the chip contact areas and third contact areas enabling the electrical connection between the upper semiconductor chip and the intermediate rewiring tape.
  • This enables a stacked electronic component which includes two semiconductor chips are mounted by a flip chip technique on one side of a substrate board. This increases the packing den- sity of the electronic component while not increasing the lat ⁇ eral space required by the component on the external sub ⁇ strate.
  • the invention also provides methods to assemble a semiconduc- tor chip assembly.
  • the method includes the steps of providing a substrate board including a plurality of first contact areas on the upper surface, the first contact areas being located approximately in the lateral centre and electrically connected by first conductor tracks and first vias to first outer con- tact areas positioned on the bottom surface of the substrate board and provides a first redistribution structure.
  • the sub ⁇ strate further includes second contact areas positioned to- wards the periphery of its upper surface which are connected by second conductor tracks and second vias to the outer con ⁇ tact areas positioned on the bottom surface of the substrate board and provides a section of the second redistribution structure.
  • At least one semiconductor chip with chip contact areas on its active surface is provided.
  • a first semiconductor chip is mounted on the substrate board by the chip contact pads and first contact pads of the substrate board.
  • the semiconductor chip is mounted by a flip chip technique by a microscopic solder ball positioned between each chip contact pad and its corresponding first contact pad.
  • a rewiring strip which includes an upper and lower polyimide foil with tape conductor tracks lying in the centre of the rewiring tape and being surrounded by the polyimide foils.
  • the rewiring strip includes a plurality of intermediate rewiring tapes arranged at intervals along the length of the strip, each intermediate rewiring tape having a plurality of third contact areas positioned in the upper surface connected by the tape conductor tracks to fourth contact areas posi ⁇ tioned in the bottom surface.
  • the fourth contact areas are laterally positioned outside of the third contact areas at the periphery of the rewiring tape.
  • the intermediate rewiring tape for the semiconductor chip as ⁇ sembly is formed from the rewiring strip by pressing a section of the rewiring tape strip into a mould of a template holder and applying heat to provide a flat bottomed recess in its central portion.
  • the third contact areas are therefore posi ⁇ tioned in the upper surface of the intermediate rewiring tape in the central regions raised by the recess.
  • the fourth con ⁇ tact areas are positioned in the lower surface of the interme ⁇ diate rewiring tape in the laterally protruding peripheral re ⁇ gions.
  • Adhesive is applied to the upper rear surface of the lower semiconductor chip and the recess of the pre-formed rewiring tape is attached to the rear surface of the semiconductor chip.
  • the third contact areas of the intermediate rewiring substrate face upwards away from the substrate board and the fourth contact areas of the rewiring tape face the substrate.
  • the first semiconductor chip is accommodated within the re ⁇ cess.
  • the fourth contact areas are electrically connected to the second contact pads of the substrate board.
  • the template holder is removed leaving the pre-formed rewiring tape attached to the substrate board and lower semiconductor chip an provide a semiconductor chip assembly according to the invention.
  • the lateral arrangement of the first contact areas on the upper surface of the substrate board corresponds to the lateral arrangement of the chip contact areas of the semicon ⁇ ductor chip which is to be mounted on the substrate board.
  • the semiconductor chip is then mounted to the substrate board by flip chip contacts, i.e. microscopic solder balls, between the chip contact pads and the first contact areas. This reduces the height and lateral dimensions of the semiconductor chip assembly and consequently the electronic component.
  • the fourth contact areas positioned on the lower surface of the rewiring tape are provided with a lateral ar- rangeraent which corresponds to the lateral arrangement of the second contact areas. Solder balls are then attached to the fourth contact areas positioned on the bottom surface of the rewiring tape. This provides a simple reliable electrical con- nection to be provided between the intermediate rewiring tape and the substrate board.
  • the lower semiconductor chip is underfilled and, preferably, also encapsulated by plastic mould material be- fore the intermediate rewiring tape is attached as the chip can be more easily accessed.
  • the contacts between the intermediate rewiring foil and the substrate are encapsulated by plastic mould mate- rial to provide protection from moisture penetration and cor ⁇ rosion.
  • the electrical connection between the first semiconductor chip and the intermediate rewiring tape and the board is performed using single solder reflow process. This has the advantage of reducing the number of manufacturing steps which reduces the manufacturing costs.
  • a method to assemble a stacked electronic component includes the further step of mounting a sec ⁇ ond semiconductor chip on the upper surface of the intermedi ⁇ ate rewiring tape to form a stacked electronic component.
  • the third contact areas positioned on the upper surface of the rewiring tape are provided with an arrangement corresponding to that of the chip contact areas on second semiconductor chip.
  • the second semiconductor chip is, prefera- bly, electrically connected to the rewiring tape using a flip chip technique by microscopic solder balls between the chip contact areas and third contact areas.
  • An electronic component with a high packing density and small footprint is, therefore, provided.
  • the upper and lower semiconductor chips and the intermediate rewiring layer are encapsulated by plastic mould material in one process step after the stack is assembled. This advantageously reduced the number of process steps re ⁇ quired.
  • a semiconductor assembly including stacked flip chips accord ⁇ ing to the invention provides an electronic package in which the density of the integrated circuits within the package is increased.
  • the semiconductor chip assembly enables flip chip bonding can be used.
  • the mechanical and electrical connection between the chip and the substrate is formed underneath the chip, therefore, reducing the lateral size of the package.
  • the stacked electronic component can also be fabricated cost effectively as the bonding is performed in parallel and can be performed in one solder reflow process to electrically connect two or more chips and the intermediate rewiring layers to the substrate board.
  • the further disadvantages of wire bonding such as the inductance of the wires and shorting between the wires are also avoided.
  • the assembly according to the invention is very flexible as either similar flip chips or different flip chips can be mounted to form a stack as the pre-formed intermediate tape is designed to have an appropriate arrangement of contact areas or bump terminals for the upper chip.
  • the contact pad arrange ⁇ ment for the upper chip is, therefore, independent of the ar ⁇ rangement of the contact areas on the substrate board for the lower semiconductor chip.
  • the assembly according to the invention has the added advan ⁇ tage that a single solder reflow process can be used to elec ⁇ trically connect two or more flip chips in the stack. This further simplifies the manufacturing process.
  • the pre-formed intermediate rewiring tape also has the advan ⁇ tage that the intermediate rewiring tape can be accurately mounted onto the rear surface of a lower semiconductor chip without requiring significant pressure to be applied to either the semiconductor chip or the underlying substrate in order to produce reliable mechanical and electrical connections.
  • Figure 1 shows a stacked electronic component according to a first embodiment of the invention
  • Figure 2 illustrates a step in the method to produce a stacked electronic component according to Figure 1.
  • FIG. 1 shows a stacked electronic component 100 according to a first embodiment of the invention.
  • Stacked electronic compo ⁇ nent 100 includes two semiconductor chips 101, 102, one inter- mediate rewiring tape 103 and a substrate board 104.
  • the semi ⁇ conductor chip 102 is mounted on the upper surface of the sub ⁇ strate board 104 by a flip chip technique.
  • the intermediate rewiring tape 103 is positioned on the upper rear surface of the semiconductor chip 102.
  • the upper semiconductor chip 101 is mounted on the upper surface of the intermediate rewiring tape 103, above the lower semiconductor chip 102 to form a stacked electronic component 100.
  • each semiconductor chip 101, 102 of the stacked flip-chip assembly 100 is a BGA pack ⁇ age and has approximately the same size.
  • Each semiconductor chip 101 and 102 includes a plurality of chip contact pads 110 on its upper active surface. Typically the chip contact pads 110 are arranged in a perfectly square grid array towards the periphery of the active surface. In the embodiment of the in ⁇ vention shown in Figure 1, six of the plurality of chip con- tact pads 110 are depicted for each of the semiconductor chips 101 and 102. Microscopic solder balls 111 which comprise the flip chip contacts are positioned on the chip contact pads 110 to provide the electrical connection to the semiconductor chip 101 and 102.
  • the substrate board 104 of the stacked electronic component 100 includes in its central portion a first rewiring structure 125 for the lower semiconductor chip 102 which is mounted di ⁇ rectly on the upper surface of the substrate board 104.
  • the substrate board 104 further includes a second rewiring struc ⁇ ture 126 located in its periphery for the upper semiconductor chip 101 of the assembly 100.
  • the first rewiring structure 125 includes a plurality of first contact areas 105 laterally positioned towards the centre of the upper surface of the substrate board 104.
  • the lateral ar ⁇ rangement of the first contact areas 105 corresponds to the lateral arrangement of the chip contact areas 110 on the lower semiconductor chip 102. Therefore, six of the plurality of first contact areas 105 are depicted in Figure 1.
  • the plurality of first contact areas 105 are electrically con ⁇ nected by conductor tracks 106 and vias 107 to a plurality of first outer contact pads 108 of the stacked electronic compo ⁇ nent 100. This provides the first rewiring structure 125 for the lower semiconductor chip 102.
  • the plurality of first outer contact pads 108 are positioned on the bottom surface of the substrate board 104.
  • a solder ball 109 is positioned on each of the outer contact pads 108 and allow the flip-chip assembly 100 including the two semi- conductor chips 101 and 102 to be mounted on, and electrically connected to, an external substrate such as a printed circuit board which is not shown in the figure for clarity.
  • the semiconductor chip 102 is mounted to the substrate board 104 by the microscopic solder balls 111 which are positioned between the chip contact pads 110 on the active surface of the semiconductor chip 102 and the contact areas 105 of the first rewiring structure 125 of the substrate board 104.
  • the second rewiring structure 126 is positioned at the periph ⁇ ery of the substrate board 104 and includes a plurality of second contact areas 112 which are arranged at the periphery of the upper surface of the substrate board 104.
  • the second plurality of contact areas 112 are electrically connected by second conductor tracks 113 and second vias 114 to a second plurality of outer contact areas 115 positioned on the bottom surface of the substrate board 104.
  • Solder balls 109 are also positioned on the second plurality of the outer contact areas 115.
  • the second contact areas 112, second conductor tracks 113 and second vias 114 provide a part of the second rewiring structure 126 for the upper semiconductor chip 101 of the stacked electronic component 100.
  • the intermediate rewiring tape 103 is positioned on the upper rear surface of the lower semiconductor chip 102.
  • the interme ⁇ diate rewiring tape has a multi-layer structure which, in this embodiment of the invention, includes an upper 116 and lower 117 electrically insulating polyimide film and a plurality of tape conductor tracks 118 of the rewiring structure arranged in the centre of the intermediate rewiring tape 103 between the upper 116 and lower 117 polyimide films.
  • the intermediate rewiring tape 103 further includes a plural ⁇ ity of third contact areas 121 positioned in the upper surface central portion of the intermediate rewiring tape 103 which are connected to the conductor tracks 118.
  • the lateral ar- rangement of the third contact areas 121 corresponds to the lateral arrangement of the chip contact pads 110 of the upper semiconductor chip 101.
  • a fourth plurality of contact pads 122 is arranged on the bot- torn surface at the periphery of the rewiring tape 103.
  • the fourth contact pads 122 are electrically connected by vias 123 to the tape conductor tracks 118 to the plurality of third contact areas 121 of the intermediate rewiring tape 103.
  • the lateral arrangement of the fourth contact pads 122 corre ⁇ sponds to the arrangement of the plurality of second contacts areas 112 positioned at the periphery of the upper surface of the substrate board 104 and provides a part of the rewiring structure of upper semiconductor chip 101.
  • the intermediate rewiring tape 103 is pre-formed to provide a flat bottomed recess 119.
  • the re ⁇ cess 119 is laterally slightly larger than the lower semicon ⁇ ductor chip 102 and has a depth of approximately that of the semiconductor chip 102.
  • the side walls of the recess 119 are approximately perpendicular to the bottom of the recess.
  • the intermediate rewiring tape 103 is pre-formed so that the upper surface of the central portion of the intermediate re ⁇ wiring tape 103 facing away from the recess 119 provides a flat surface.
  • the third plurality of contact pads 121 are po- sitioned in the upper surface of the intermediate rewiring tape in this central flat region.
  • the lower surface of the intermediate rewiring tape 103 out ⁇ side of the recess 119 lies on a plane parallel to that of the bottom of the recess 119 and lies in approximately the same plane as the upper active surface of the lower semicon ⁇ ductor chip 102 when mounted on the rear surface of the semi ⁇ conductor chip 102.
  • the fourth contact pads 122 are positioned in the periphery of the intermediate rewiring tape 103 and lie outside of pre ⁇ formed recess 119 of the intermediate tape 103 and lie in a horizontal plane above the corresponding contact pads 112 of the substrate board 104.
  • the dimensions of the recess are chosen so that the solder balls 124 positioned between the second contact areas 112 and fourth contact areas 122 are approximately the same size as the microscopic solder balls 111 attached to the chip contact areas 110 of the semiconductor chip 102.
  • a solder ball 124 is positioned between the second contact pads 112 of the substrate board 104 and the fourth contact ar ⁇ eas 122 of the intermediate rewiring tape 10.
  • the solder balls 124 electrically connect the second 112 and fourth 122 contact areas and, therefore, the upper semiconductor chip 101 to the substrate board 104 and completes the rewiring structure 126 for the second semiconductor chip 101.
  • the recess 119 in the intermediate rewiring tape 103 extends across the width of the rewiring tape. Therefore, the protrud- ing regions extend only from two opposing sides of the recess 119. This arrangement is not visible in the cross-sectional view of the figures.
  • the intermediate tape 103 is pre-formed by pressing a section of the rewiring tape 103 into a mould while being heated. This is performed in such as way so that the conductor tracks 118 po ⁇ sitioned in the centres of the intermediate rewiring tape 103 are not damaged. This is facilitated by the provision of bend- ing or flexing lines appropriately positioned in the rewiring tape 103.
  • a layer of adhesive 120 is positioned on the upper rear sur ⁇ face of the lower semiconductor chip 102 and attaches the rear surface of the semiconductor chip 102 to the flat bottom of the recess 119.
  • the intermediate rewiring tape 103 is mounted on the semiconductor chip 102 so that the semiconductor chip 102 is accommodated within the recess 119 and the bottom sur ⁇ face of the rewiring tape 103 outside of the recess lies in approximately the same plane as the active surface of the lower semiconductor chip 102.
  • the upper semiconductor chip 101 is also a ball-grid array type package and includes an active surface with integrated circuit devices and chip contact areas 110.
  • the upper semicon ⁇ ductor chip 101 is mounted to intermediate rewiring tape using the flip chip technique.
  • a microscopic solder ball 105 is po ⁇ sitioned between each of the contact areas 110 on the upper surface of the semiconductor 101 and a fourth contact area 121 of the rewiring tape 103.
  • the upper semiconductor chip 101 is electrically connected to the substrate board 104 by the second rewiring structure 126 which includes the tape conductor tracks 118 and tape vias 123 which connect the third 121 and fourth 122 pluralities of con ⁇ tact areas of the intermediate rewiring tape 103 and then by the solder ball 124 to the section of second rewiring struc ⁇ ture provided by the second contact pads 112, second conductor track 113 and second vias 114 to the outer contact area 115 of the substrate board 104.
  • the second rewiring structure 126 which includes the tape conductor tracks 118 and tape vias 123 which connect the third 121 and fourth 122 pluralities of con ⁇ tact areas of the intermediate rewiring tape 103 and then by the solder ball 124 to the section of second rewiring struc ⁇ ture provided by the second contact pads 112, second conductor track 113 and second vias 114 to the outer contact area 115 of the substrate board 104.
  • a stacked electronic component 100 is, therefore, provided by the invention.
  • the embodiment shown in Figure 1 in ⁇ cludes an assembly of two stacked flip chips, the invention can be used to provide a stacked module containing three or more stacked semiconductor chips.
  • Figure 2 shows a step in the method to produce a stacked elec ⁇ tronic component according to the invention.
  • Parts of the em- bodiment which are essentially the same as the embodiment of Figure 1 are designated by the same reference number and are not necessarily described again.
  • a substrate board 104 is provided.
  • the central por ⁇ tion of the substrate board includes a rewiring structure 125 for the lower semiconductor chip 102 which is mounted on its upper surface.
  • the rewiring structure includes a plurality of contact areas 105 on the upper surface whose lateral arrange- ment corresponds to the lateral arrangement of the chip con ⁇ tact areas 110 of the semiconductor chip 102 which is to be mounted on the substrate board 104.
  • the contact areas 105 are connected by conductor tracks 106 and vias 107 to outer con ⁇ nect areas 108 positioned on the bottom surface of the sub- strate board 104.
  • the substrate further includes a second rewiring structure for the upper semiconductor chip 101 of the stack positioned to ⁇ wards its periphery including contact areas 112 on its upper surface which are connected by conductor tracks 113 and vias 113 to the outer contact areas 115 positioned on the bottom surface of the substrate board 104.
  • a semiconductor chip 102 is then mounted by the flip chip technique on the substrate board 104 by microscopic solder balls 111 positioned between the chip contact pads 110 and first contact pads 105 of the substrate board 104.
  • the rewiring tape 103 is provided in the form of a long strip 127 including an upper 116 polyimide film and a lower 117 polyimide film.
  • the rewiring structure for each intermediate rewiring tape 103 including the tape conductor tracks 118 is positioned between the two polyimide films.
  • the rewiring strip 127 includes a plurality of intermediate rewiring structures 103 arranged at intervals along the length of the strip.
  • a pre-formed intermediate rewiring tape 103 includes an upper 116 and lower 117 polyimide foil.
  • a plurality of third contact areas 121 are positioned in the central portion of the upper surface of the intermediate tape 103 and are connected by con ⁇ ductor tracks 118 to fourth contact areas 122 positioned in the bottom surface at the periphery of the rewiring tape 103.
  • the lateral arrangement of the third contact areas corresponds to the lateral arrangement of the semiconductor chip 101 which is to be mounted on the intermediate substrate tape.
  • the lat- eral arrangement of the fourth contact areas corresponds to that of the second contact areas positioned in the periphery of the substrate board 104.
  • the tape conductor tracks 118 lie in the centre of the rewiring tape 103
  • the intermediate rewiring tape 103 for the assembly 100 is formed by pressing a section of the rewiring tape strip 127 into the mould 128 of a template holder 129 in order to form a flat bottomed recess 119 in its central portion.
  • the recess 119 is laterally slightly larger than the lower semiconductor chip 102 and has a depth of approximately that of the semiconductor chip.
  • the recess 119 is formed in the bottom surface of the rewiring tape 103 so that the third con ⁇ tact areas 121 are arranged in the upper surface of the inter- mediate rewiring tape which is raised by the recess 119 and the fourth contact areas 122 lie in the bottom surface of the rewiring tape 103 outside of the recess 119.
  • the portion of the pre-formed intermediate tape 103 including the fourth contact areas protrudes laterally outwards from two opposing sides of the recess 119 and the bottom surface lies in a plane parallel to the flat bottom of the recess 119.
  • the section of the strip is cut to provide the pre-formed interme ⁇ diate tape 103 for the assembly 100.
  • Solder balls 124 are then attached to the fourth contact areas 122 positioned on the bottom surface of the rewiring tape 103.
  • a layer of adhesive is applied the upper rear surface of the lower semiconductor chip 101.
  • the pre-formed rewiring tape 103 is lowered onto the semiconductor chip 101 so that the flat bottom of the recess 119 is attached to the rear surface of the semiconductor chip 101 and the semiconductor chip 101 is accommodated within the recess 119 of the rewiring tape 103.
  • the solder balls 124 attached to the bottom surface of the pe ⁇ ripheral fourth contact areas 122 of the rewiring tape 103 are positioned on the second contact pads 112 at the periphery of the substrate board 104.
  • solder is reflowed to electrically connect the intermedi ⁇ ate rewiring tape 103 to the substrate board 104 and the tem- plate holder 129 removed leaving the pre-formed rewiring tape 103 attached to the substrate board 104 and lower semiconduc ⁇ tor chip 102.
  • a second semiconductor chip 101 is then mounted on the upper • surface of the intermediate rewiring tape 103 using the flip- chip technique by microscopic solder balls positioned between the chip contact pads 110 and plurality of third contact pads of the intermediate rewiring tape 103.
  • the upper semiconductor chip 101 is, therefore electrically connected to the substrate board 104 by the second rewiring structure provided by in the intermediate rewiring tape 103 and periphery of the substrate board 104.
  • the stacked electronic component 100 is then encapsulated by a plastic mould material which is not shown in the figures for clarity.

Abstract

A stacked electronic component (100) comprises a substrate board (104) and a first semiconductor chip (101) mounted by a flip chip technique to the substrate board (104). An intermediate rewiring tape (103) having a recess (119), is mounted to the rear side of the first semiconductor chip (102), the recess (119) of the intermediate rewiring tape accommodate the first semiconductor chip. A second semiconductor chip (101) is mounted to the intermediate rewiring layer by a flip chip technique.

Description

Description
SEMICONDUCTOR CHIP ASSEMBLY INCLUDING STACKED COMPONENTS AND METHOD FOR PRODUCING IT
The invention relates to a semiconductor chip assembly, a stacked electronic component including the assembly and meth¬ ods for producing the assembly and electronic component.
Increased miniaturisation and cost reduction are among some of the development aims currently addresses in semiconductor technology. It is desired that both the outer size of semicon¬ ductor packages is reduced and that the number of integrated circuits within a package of a given size, the so-called pack- ing density, is increased.
One method by which the size of a package can be decreased is by mounting the chips on a substrate by a flip chip technique. This technique is advantageous as both the height and lateral space required by a package including the flip chip contacts is less than that required by packages with wire bonds. Addi¬ tionally, in flip chip technology electrical contacting be¬ tween the chip and its substrate occurs in parallel for all the flip contacts rather than serially as for wire bonded chips. This increases manufacturing speeds and, therefore, re¬ duces costs.
Further increases in the packing density of electronic pack¬ ages are achieved by providing multi-chip modules in which two or more chips are stacked on top of one another. However, a stacked multi-chip module is difficult to achieve for two or more chips mounted using a flip-chip technique due to the cen¬ tral arrangement of the flip chip contacts.
US 2002-074637 Al discloses an electronic component which in- eludes stacked semiconductor chip electrically connected by flip chip contacts. Each semiconductor chip or die is provided with conductive redistribution traces both its active front and passive rear surfaces. The conductive traces on the two opposing faces of each die are electrically connected by con- ductive tracks disposed on the side of the chip. The manufac¬ turing process of such a stacked component is, therefore, com¬ plicated and expensive.
It is, therefore, an object of the invention to provide a semiconductor chip assembly which enables the density of the integrated circuits to be increased within a package of a given size and which can be produced using more cost effective manufacturing methods.
It is a further object of the invention to provide an elec¬ tronic component including the semiconductor chip assembly which includes at least two stacked semiconductor chips and a method for its production.
This is achieved by the subject matter of the independent claims. Further improvements are provided by the subject mat¬ ter of the dependent claims.
A semiconductor chip assembly, according to the invention, in- eludes a substrate board. The substrate board typically com¬ prises a glass fibre matrix such as FR4 or BT and includes a redistribution structure. The substrate board, according to the invention, includes a plurality of first contact areas po¬ sitioned on the upper surface towards the lateral centre which are electrically connected by a plurality of first conductor tracks and a plurality of first vias to first outer contact areas positioned on the bottom surface of the substrate board to provide a first redistribution structure.
The substrate board further includes a plurality of second contact areas positioned on the upper surface towards the pe- riphery of the substrate board. The second contact areas are electrically connected by second conductor tracks and second vias to second outer contact areas positioned on the bottom surface of the substrate board and provide a second redistri¬ bution structure.
The semiconductor chip assembly according to the invention also includes at least one semiconductor chip, including a plurality of chip contact areas on its active surface. A first semiconductor chip is mounted in the lateral centre on the up- per surface of the substrate board by electrical connections between the chip contact areas and the first contact areas.
Preferably, the lateral arrangement of the first contact areas on the upper surface of the substrate board corresponds to the lateral arrangement of the chip contact areas on the active surface of the chip. Preferably, the first semiconductor chip is mounted by a flip chip technique by a microscopic solder ball positioned between each chip contact pad and its corre¬ sponding contact area on the substrate board. The first semi- conductor chip is thereby electrically connected to the first redistribution structure. The semiconductor chip assembly according to the invention also includes a pre-formed intermediate rewiring tape. The pre-formed intermediate rewiring tape includes third contact areas, positioned towards the centre of its upper surface, and fourth contact areas, positioned on the bottom surface towards the periphery. The third and fourth contact areas are electri¬ cally connected by tape conductor tracks located in the centre of the intermediate rewiring tape and being positioned between and surrounded by between an upper and lower electrically in- sulating film. The electrically insulating film preferably comprises polyimide and the conductor tracks preferably com¬ prise copper or a copper alloy.
The use of a pre-formed intermediate rewiring structure pro- vides a simple cost effective method to provide a rewiring structure for the upper semiconductor chip in a stacked elec¬ tronic component, particularly for a semiconductor chip mounted using a flip chip technique as portions of the rewir¬ ing tracks can be positioned under the upper chip. Electrical contacts to the intermediate rewiring structure and therefore the upper chip are advantageously provided in the periphery of the intermediate rewiring tape. This enables an easy reliable contact to the upper chip of the stack to be formed.
The pre-formed intermediate rewiring tapes are, preferably, fabricated in the form of a strip including a plurality of in¬ termediate rewiring tapes arranged along the length. The in¬ termediate rewiring tapes are manufactured cost effectively using simple known techniques.
The pre-formed intermediate wiring tape further includes a re¬ cess surrounded by peripheral regions which protrude laterally outwards from the recess. The recess is formed with a flat bottom and the laterally protruding regions lie in a plane ap¬ proximately parallel to that of the bottom of the recess.
Preferably, the recess is formed over the whole width of the tape so that the laterally protruding regions extend on only two opposing sides of the recess. This has the advantage that the lateral size of the rewiring tape is reduced.
The fourth contact areas are therefore located in the protrud¬ ing region and the third contact areas in the central region. The recess of the intermediate rewiring tape is mounted to the rear side of the first semiconductor chip, and the fourth con¬ tact areas of the intermediate rewiring tape are electrically connected to the second contact areas of the substrate board.
Preferably, the fourth contact areas of the intermediate re¬ wiring tape have a lateral arrangement which corresponds to the lateral arrangement of the second contact areas of the substrate board. The fourth and second connect areas are ad¬ vantageously electrically connected by a plurality of solder balls.
The contact areas on the upper and lower surface of the inter- mediate rewiring tape are provided by metallic contact pads positioned on metallic vias which are positioned through the upper and lower electrically insulating films. This method has the advantage that the lateral size of the vias and contact areas can be independently controlled.
Alternatively, the contact areas of the intermediate rewiring tape are provided by providing n appropriate arrangement of apertures in the electrically insulating films which expose the underlying conductor track. This method has the advantage that fewer masking and deposition steps are required.
Preferably, the recess of the intermediate rewiring tape is attached to the rear side of the first semiconductor chip by adhesive. The first semiconductor chip is, therefore, accommo¬ dated within the recess and the plane of the laterally out¬ wardly protruding regions lie in approximately the same plane as the active surface of the first semiconductor chip.
This arrangement of the pre-formed intermediate tape enables the rewiring tape to be attached directly to the rear side of the semiconductor chip without requiring an intermediate elec- trically insulating layer. The production of the semiconductor chip assembly is simplified.
Preferably, the intermediate rewiring tape includes tape con¬ ductor tracks on two or more electrically isolated inner lay- ers. This enables a more complex redistribution structure to be provided.
Preferably, the flip chip contacts and the space between the active surface of the chip and the substrate are protected by underfill material. This protects the contact from corrosion due to moisture. Preferably the semiconductor chips are also encapsulated by plastic mould material, the contacts between the intermediate rewiring foil and the substrate are encapsu¬ lated by plastic mould material. The plastic mould material provides further mechanical protection for the electrical con¬ nections and protection from moisture penetration and, there¬ fore, corrosion of the contacts. A stacked electronic component including the semiconductor as¬ sembly according to the invention further includes a second semiconductor chip mounted on the upper surface of the inter- mediate rewiring tape.
Preferably, the lateral arrangement of the third contact areas on the upper surface of the intermediate rewiring tape corre¬ sponds to that of the chip contact areas on second semiconduc- tor chip. The second semiconductor chip is, preferably, elec¬ trically connected to the rewiring tape by a flip chip tech¬ nique whereby microscopic solder balls are provided between the chip contact areas and third contact areas enabling the electrical connection between the upper semiconductor chip and the intermediate rewiring tape.
This enables a stacked electronic component which includes two semiconductor chips are mounted by a flip chip technique on one side of a substrate board. This increases the packing den- sity of the electronic component while not increasing the lat¬ eral space required by the component on the external sub¬ strate.
The invention also provides methods to assemble a semiconduc- tor chip assembly. The method includes the steps of providing a substrate board including a plurality of first contact areas on the upper surface, the first contact areas being located approximately in the lateral centre and electrically connected by first conductor tracks and first vias to first outer con- tact areas positioned on the bottom surface of the substrate board and provides a first redistribution structure. The sub¬ strate further includes second contact areas positioned to- wards the periphery of its upper surface which are connected by second conductor tracks and second vias to the outer con¬ tact areas positioned on the bottom surface of the substrate board and provides a section of the second redistribution structure.
At least one semiconductor chip with chip contact areas on its active surface is provided. A first semiconductor chip is mounted on the substrate board by the chip contact pads and first contact pads of the substrate board. Preferably, the semiconductor chip is mounted by a flip chip technique by a microscopic solder ball positioned between each chip contact pad and its corresponding first contact pad.
A rewiring strip is provided which includes an upper and lower polyimide foil with tape conductor tracks lying in the centre of the rewiring tape and being surrounded by the polyimide foils. The rewiring strip includes a plurality of intermediate rewiring tapes arranged at intervals along the length of the strip, each intermediate rewiring tape having a plurality of third contact areas positioned in the upper surface connected by the tape conductor tracks to fourth contact areas posi¬ tioned in the bottom surface. The fourth contact areas are laterally positioned outside of the third contact areas at the periphery of the rewiring tape.
The intermediate rewiring tape for the semiconductor chip as¬ sembly is formed from the rewiring strip by pressing a section of the rewiring tape strip into a mould of a template holder and applying heat to provide a flat bottomed recess in its central portion. The third contact areas are therefore posi¬ tioned in the upper surface of the intermediate rewiring tape in the central regions raised by the recess. The fourth con¬ tact areas are positioned in the lower surface of the interme¬ diate rewiring tape in the laterally protruding peripheral re¬ gions.
Adhesive is applied to the upper rear surface of the lower semiconductor chip and the recess of the pre-formed rewiring tape is attached to the rear surface of the semiconductor chip. The third contact areas of the intermediate rewiring substrate face upwards away from the substrate board and the fourth contact areas of the rewiring tape face the substrate. The first semiconductor chip is accommodated within the re¬ cess. The fourth contact areas are electrically connected to the second contact pads of the substrate board.
The template holder is removed leaving the pre-formed rewiring tape attached to the substrate board and lower semiconductor chip an provide a semiconductor chip assembly according to the invention.
Preferably, the lateral arrangement of the first contact areas on the upper surface of the substrate board corresponds to the lateral arrangement of the chip contact areas of the semicon¬ ductor chip which is to be mounted on the substrate board. The semiconductor chip is then mounted to the substrate board by flip chip contacts, i.e. microscopic solder balls, between the chip contact pads and the first contact areas. This reduces the height and lateral dimensions of the semiconductor chip assembly and consequently the electronic component.
Preferably, the fourth contact areas positioned on the lower surface of the rewiring tape are provided with a lateral ar- rangeraent which corresponds to the lateral arrangement of the second contact areas. Solder balls are then attached to the fourth contact areas positioned on the bottom surface of the rewiring tape. This provides a simple reliable electrical con- nection to be provided between the intermediate rewiring tape and the substrate board.
Preferably, the lower semiconductor chip is underfilled and, preferably, also encapsulated by plastic mould material be- fore the intermediate rewiring tape is attached as the chip can be more easily accessed.
Preferably, the contacts between the intermediate rewiring foil and the substrate are encapsulated by plastic mould mate- rial to provide protection from moisture penetration and cor¬ rosion.
The electrical connection between the first semiconductor chip and the intermediate rewiring tape and the board is performed using single solder reflow process. This has the advantage of reducing the number of manufacturing steps which reduces the manufacturing costs.
A method to assemble a stacked electronic component, according to the invention, includes the further step of mounting a sec¬ ond semiconductor chip on the upper surface of the intermedi¬ ate rewiring tape to form a stacked electronic component.
Preferably, the third contact areas positioned on the upper surface of the rewiring tape are provided with an arrangement corresponding to that of the chip contact areas on second semiconductor chip. The second semiconductor chip is, prefera- bly, electrically connected to the rewiring tape using a flip chip technique by microscopic solder balls between the chip contact areas and third contact areas. An electronic component with a high packing density and small footprint is, therefore, provided.
Alternatively, the upper and lower semiconductor chips and the intermediate rewiring layer are encapsulated by plastic mould material in one process step after the stack is assembled. This advantageously reduced the number of process steps re¬ quired.
A semiconductor assembly including stacked flip chips accord¬ ing to the invention provides an electronic package in which the density of the integrated circuits within the package is increased. The semiconductor chip assembly enables flip chip bonding can be used. The mechanical and electrical connection between the chip and the substrate is formed underneath the chip, therefore, reducing the lateral size of the package.
The stacked electronic component can also be fabricated cost effectively as the bonding is performed in parallel and can be performed in one solder reflow process to electrically connect two or more chips and the intermediate rewiring layers to the substrate board. The further disadvantages of wire bonding such as the inductance of the wires and shorting between the wires are also avoided.
The assembly according to the invention is very flexible as either similar flip chips or different flip chips can be mounted to form a stack as the pre-formed intermediate tape is designed to have an appropriate arrangement of contact areas or bump terminals for the upper chip. The contact pad arrange¬ ment for the upper chip is, therefore, independent of the ar¬ rangement of the contact areas on the substrate board for the lower semiconductor chip.
The assembly according to the invention has the added advan¬ tage that a single solder reflow process can be used to elec¬ trically connect two or more flip chips in the stack. This further simplifies the manufacturing process.
The pre-formed intermediate rewiring tape also has the advan¬ tage that the intermediate rewiring tape can be accurately mounted onto the rear surface of a lower semiconductor chip without requiring significant pressure to be applied to either the semiconductor chip or the underlying substrate in order to produce reliable mechanical and electrical connections.
An embodiment of the invention will now be described by refer¬ ence to the figures.
Figure 1 shows a stacked electronic component according to a first embodiment of the invention, and
Figure 2 illustrates a step in the method to produce a stacked electronic component according to Figure 1.
Figure 1 shows a stacked electronic component 100 according to a first embodiment of the invention. Stacked electronic compo¬ nent 100 includes two semiconductor chips 101, 102, one inter- mediate rewiring tape 103 and a substrate board 104. The semi¬ conductor chip 102 is mounted on the upper surface of the sub¬ strate board 104 by a flip chip technique. The intermediate rewiring tape 103 is positioned on the upper rear surface of the semiconductor chip 102. The upper semiconductor chip 101 is mounted on the upper surface of the intermediate rewiring tape 103, above the lower semiconductor chip 102 to form a stacked electronic component 100.
In this embodiment of the invention, each semiconductor chip 101, 102 of the stacked flip-chip assembly 100 is a BGA pack¬ age and has approximately the same size. Each semiconductor chip 101 and 102 includes a plurality of chip contact pads 110 on its upper active surface. Typically the chip contact pads 110 are arranged in a perfectly square grid array towards the periphery of the active surface. In the embodiment of the in¬ vention shown in Figure 1, six of the plurality of chip con- tact pads 110 are depicted for each of the semiconductor chips 101 and 102. Microscopic solder balls 111 which comprise the flip chip contacts are positioned on the chip contact pads 110 to provide the electrical connection to the semiconductor chip 101 and 102.
The substrate board 104 of the stacked electronic component 100 includes in its central portion a first rewiring structure 125 for the lower semiconductor chip 102 which is mounted di¬ rectly on the upper surface of the substrate board 104. The substrate board 104 further includes a second rewiring struc¬ ture 126 located in its periphery for the upper semiconductor chip 101 of the assembly 100.
The first rewiring structure 125 includes a plurality of first contact areas 105 laterally positioned towards the centre of the upper surface of the substrate board 104. The lateral ar¬ rangement of the first contact areas 105 corresponds to the lateral arrangement of the chip contact areas 110 on the lower semiconductor chip 102. Therefore, six of the plurality of first contact areas 105 are depicted in Figure 1.
The plurality of first contact areas 105 are electrically con¬ nected by conductor tracks 106 and vias 107 to a plurality of first outer contact pads 108 of the stacked electronic compo¬ nent 100. This provides the first rewiring structure 125 for the lower semiconductor chip 102.
The plurality of first outer contact pads 108 are positioned on the bottom surface of the substrate board 104. A solder ball 109 is positioned on each of the outer contact pads 108 and allow the flip-chip assembly 100 including the two semi- conductor chips 101 and 102 to be mounted on, and electrically connected to, an external substrate such as a printed circuit board which is not shown in the figure for clarity.
The semiconductor chip 102 is mounted to the substrate board 104 by the microscopic solder balls 111 which are positioned between the chip contact pads 110 on the active surface of the semiconductor chip 102 and the contact areas 105 of the first rewiring structure 125 of the substrate board 104.
The second rewiring structure 126 is positioned at the periph¬ ery of the substrate board 104 and includes a plurality of second contact areas 112 which are arranged at the periphery of the upper surface of the substrate board 104. The second plurality of contact areas 112 are electrically connected by second conductor tracks 113 and second vias 114 to a second plurality of outer contact areas 115 positioned on the bottom surface of the substrate board 104. Solder balls 109 are also positioned on the second plurality of the outer contact areas 115. The second contact areas 112, second conductor tracks 113 and second vias 114 provide a part of the second rewiring structure 126 for the upper semiconductor chip 101 of the stacked electronic component 100.
The intermediate rewiring tape 103 is positioned on the upper rear surface of the lower semiconductor chip 102. The interme¬ diate rewiring tape has a multi-layer structure which, in this embodiment of the invention, includes an upper 116 and lower 117 electrically insulating polyimide film and a plurality of tape conductor tracks 118 of the rewiring structure arranged in the centre of the intermediate rewiring tape 103 between the upper 116 and lower 117 polyimide films.
The intermediate rewiring tape 103 further includes a plural¬ ity of third contact areas 121 positioned in the upper surface central portion of the intermediate rewiring tape 103 which are connected to the conductor tracks 118. The lateral ar- rangement of the third contact areas 121 corresponds to the lateral arrangement of the chip contact pads 110 of the upper semiconductor chip 101.
A fourth plurality of contact pads 122 is arranged on the bot- torn surface at the periphery of the rewiring tape 103. The fourth contact pads 122 are electrically connected by vias 123 to the tape conductor tracks 118 to the plurality of third contact areas 121 of the intermediate rewiring tape 103.
The lateral arrangement of the fourth contact pads 122 corre¬ sponds to the arrangement of the plurality of second contacts areas 112 positioned at the periphery of the upper surface of the substrate board 104 and provides a part of the rewiring structure of upper semiconductor chip 101.
According to the invention, the intermediate rewiring tape 103 is pre-formed to provide a flat bottomed recess 119. The re¬ cess 119 is laterally slightly larger than the lower semicon¬ ductor chip 102 and has a depth of approximately that of the semiconductor chip 102. The side walls of the recess 119 are approximately perpendicular to the bottom of the recess.
The intermediate rewiring tape 103 is pre-formed so that the upper surface of the central portion of the intermediate re¬ wiring tape 103 facing away from the recess 119 provides a flat surface. The third plurality of contact pads 121 are po- sitioned in the upper surface of the intermediate rewiring tape in this central flat region.
The lower surface of the intermediate rewiring tape 103 out¬ side of the recess 119, lies on a plane parallel to that of the bottom of the recess 119 and lies in approximately the same plane as the upper active surface of the lower semicon¬ ductor chip 102 when mounted on the rear surface of the semi¬ conductor chip 102.
The fourth contact pads 122 are positioned in the periphery of the intermediate rewiring tape 103 and lie outside of pre¬ formed recess 119 of the intermediate tape 103 and lie in a horizontal plane above the corresponding contact pads 112 of the substrate board 104.
The dimensions of the recess are chosen so that the solder balls 124 positioned between the second contact areas 112 and fourth contact areas 122 are approximately the same size as the microscopic solder balls 111 attached to the chip contact areas 110 of the semiconductor chip 102.
A solder ball 124 is positioned between the second contact pads 112 of the substrate board 104 and the fourth contact ar¬ eas 122 of the intermediate rewiring tape 10. The solder balls 124 electrically connect the second 112 and fourth 122 contact areas and, therefore, the upper semiconductor chip 101 to the substrate board 104 and completes the rewiring structure 126 for the second semiconductor chip 101.
The recess 119 in the intermediate rewiring tape 103 extends across the width of the rewiring tape. Therefore, the protrud- ing regions extend only from two opposing sides of the recess 119. This arrangement is not visible in the cross-sectional view of the figures.
As is explained in more detail with reference to Figure 2, the intermediate tape 103 is pre-formed by pressing a section of the rewiring tape 103 into a mould while being heated. This is performed in such as way so that the conductor tracks 118 po¬ sitioned in the centres of the intermediate rewiring tape 103 are not damaged. This is facilitated by the provision of bend- ing or flexing lines appropriately positioned in the rewiring tape 103.
A layer of adhesive 120 is positioned on the upper rear sur¬ face of the lower semiconductor chip 102 and attaches the rear surface of the semiconductor chip 102 to the flat bottom of the recess 119. The intermediate rewiring tape 103 is mounted on the semiconductor chip 102 so that the semiconductor chip 102 is accommodated within the recess 119 and the bottom sur¬ face of the rewiring tape 103 outside of the recess lies in approximately the same plane as the active surface of the lower semiconductor chip 102.
The upper semiconductor chip 101 is also a ball-grid array type package and includes an active surface with integrated circuit devices and chip contact areas 110. The upper semicon¬ ductor chip 101 is mounted to intermediate rewiring tape using the flip chip technique. A microscopic solder ball 105 is po¬ sitioned between each of the contact areas 110 on the upper surface of the semiconductor 101 and a fourth contact area 121 of the rewiring tape 103.
The upper semiconductor chip 101 is electrically connected to the substrate board 104 by the second rewiring structure 126 which includes the tape conductor tracks 118 and tape vias 123 which connect the third 121 and fourth 122 pluralities of con¬ tact areas of the intermediate rewiring tape 103 and then by the solder ball 124 to the section of second rewiring struc¬ ture provided by the second contact pads 112, second conductor track 113 and second vias 114 to the outer contact area 115 of the substrate board 104.
A stacked electronic component 100 is, therefore, provided by the invention. Although the embodiment shown in Figure 1 in¬ cludes an assembly of two stacked flip chips, the invention can be used to provide a stacked module containing three or more stacked semiconductor chips.
Figure 2 shows a step in the method to produce a stacked elec¬ tronic component according to the invention. Parts of the em- bodiment which are essentially the same as the embodiment of Figure 1 are designated by the same reference number and are not necessarily described again.
Firstly, a substrate board 104 is provided. The central por¬ tion of the substrate board includes a rewiring structure 125 for the lower semiconductor chip 102 which is mounted on its upper surface. The rewiring structure includes a plurality of contact areas 105 on the upper surface whose lateral arrange- ment corresponds to the lateral arrangement of the chip con¬ tact areas 110 of the semiconductor chip 102 which is to be mounted on the substrate board 104. The contact areas 105 are connected by conductor tracks 106 and vias 107 to outer con¬ nect areas 108 positioned on the bottom surface of the sub- strate board 104.
The substrate further includes a second rewiring structure for the upper semiconductor chip 101 of the stack positioned to¬ wards its periphery including contact areas 112 on its upper surface which are connected by conductor tracks 113 and vias 113 to the outer contact areas 115 positioned on the bottom surface of the substrate board 104.
A semiconductor chip 102 is then mounted by the flip chip technique on the substrate board 104 by microscopic solder balls 111 positioned between the chip contact pads 110 and first contact pads 105 of the substrate board 104.
The rewiring tape 103 is provided in the form of a long strip 127 including an upper 116 polyimide film and a lower 117 polyimide film. The rewiring structure for each intermediate rewiring tape 103 including the tape conductor tracks 118 is positioned between the two polyimide films. The rewiring strip 127 includes a plurality of intermediate rewiring structures 103 arranged at intervals along the length of the strip.
A pre-formed intermediate rewiring tape 103 includes an upper 116 and lower 117 polyimide foil. A plurality of third contact areas 121 are positioned in the central portion of the upper surface of the intermediate tape 103 and are connected by con¬ ductor tracks 118 to fourth contact areas 122 positioned in the bottom surface at the periphery of the rewiring tape 103.
The lateral arrangement of the third contact areas corresponds to the lateral arrangement of the semiconductor chip 101 which is to be mounted on the intermediate substrate tape. The lat- eral arrangement of the fourth contact areas corresponds to that of the second contact areas positioned in the periphery of the substrate board 104. The tape conductor tracks 118 lie in the centre of the rewiring tape 103
The intermediate rewiring tape 103 for the assembly 100 is formed by pressing a section of the rewiring tape strip 127 into the mould 128 of a template holder 129 in order to form a flat bottomed recess 119 in its central portion.
The recess 119 is laterally slightly larger than the lower semiconductor chip 102 and has a depth of approximately that of the semiconductor chip. The recess 119 is formed in the bottom surface of the rewiring tape 103 so that the third con¬ tact areas 121 are arranged in the upper surface of the inter- mediate rewiring tape which is raised by the recess 119 and the fourth contact areas 122 lie in the bottom surface of the rewiring tape 103 outside of the recess 119. The portion of the pre-formed intermediate tape 103 including the fourth contact areas protrudes laterally outwards from two opposing sides of the recess 119 and the bottom surface lies in a plane parallel to the flat bottom of the recess 119. The section of the strip is cut to provide the pre-formed interme¬ diate tape 103 for the assembly 100.
Solder balls 124 are then attached to the fourth contact areas 122 positioned on the bottom surface of the rewiring tape 103.
A layer of adhesive is applied the upper rear surface of the lower semiconductor chip 101. The pre-formed rewiring tape 103 is lowered onto the semiconductor chip 101 so that the flat bottom of the recess 119 is attached to the rear surface of the semiconductor chip 101 and the semiconductor chip 101 is accommodated within the recess 119 of the rewiring tape 103. The solder balls 124 attached to the bottom surface of the pe¬ ripheral fourth contact areas 122 of the rewiring tape 103 are positioned on the second contact pads 112 at the periphery of the substrate board 104.
The solder is reflowed to electrically connect the intermedi¬ ate rewiring tape 103 to the substrate board 104 and the tem- plate holder 129 removed leaving the pre-formed rewiring tape 103 attached to the substrate board 104 and lower semiconduc¬ tor chip 102.
A second semiconductor chip 101 is then mounted on the upper • surface of the intermediate rewiring tape 103 using the flip- chip technique by microscopic solder balls positioned between the chip contact pads 110 and plurality of third contact pads of the intermediate rewiring tape 103. The upper semiconductor chip 101 is, therefore electrically connected to the substrate board 104 by the second rewiring structure provided by in the intermediate rewiring tape 103 and periphery of the substrate board 104.
The stacked electronic component 100 is then encapsulated by a plastic mould material which is not shown in the figures for clarity.
Reference numbers
100 stacked electronic component
101 upper semiconductor chip 102 lower semiconductor chip
103 intermediate rewiring tape
104 substrate board
105 first contact area
106 first conductor track 107 first via
108 outer contact area
109 solder ball
110 chip contact pad
111 microscopic solder ball 112 second contact area
113 second conductor track
114 second via
115 second outer contact are
116 first polyimide foil 117 second polyimide foil
118 tape contactor track
119 recess
120 adhesive
121 third contact area 122 fourth contact area
123 tape via
124 solder ball
125 first rewiring structure
126 second rewiring structure 127 rewiring tape strip
128 mould
129 template holder

Claims

Claims
1. Semiconductor chip assembly comprising the following fea¬ tures: - a substrate board (104) including a plurality of first contact areas (105) and a plurality of second contact areas (112) on its upper surface, at least one semiconductor chip (101) including a plu¬ rality of chip contact areas (110) on its active sur- face, a first semiconductor chip (102) being mounted on the substrate board (104) by the chip contact areas (110) and the first contact areas (105), an intermediate rewiring tape (103) including tape con¬ ductor tracks (118) located between an upper (116) and lower (117) electrically insulating film, and electri¬ cally connecting third contact areas (121) and fourth contact areas (112), wherein the intermediate wiring tape (103) has a recess (119), the recess (119) of the intermediate rewiring tape being mounted to the rear side of the first semiconductor chip (102), and the fourth contact areas (122) of the in¬ termediate rewiring tape being electrically connected to the second contact areas (112) of the substrate board (104) .
2. Semiconductor chip assembly according to claim 1 characterised in that the fourth contact areas (122) of the intermediate rewir¬ ing tape (103) have a lateral arrangement which corre- sponds to the lateral arrangement of the second contact areas (112) of the substrate board (104) and are electri- cally connected to the second contact areas (112) by sol¬ der ball connections (124) .
3. A semiconductor chip assembly according to claim 1 or claim 2 characterised in that the recess (119) of the intermediate rewiring tape (103) is attached to the rear side of the first semiconductor chip (101) by adhesive (120) .
4. A semiconductor chip assembly according to one of the pre¬ vious claims characterised in that the intermediate rewiring tape (103) includes tape conduc- tor tracks (118) lying on two or more electrically iso¬ lated inner layers.
5. A semiconductor chip assembly according to one of the pre¬ vious claims characterised in that the first semiconductor chip (101) is encapsulated by plastic mould material.
6. A semiconductor chip assembly according to one of the pre- vious claims characterised in that the contacts (124) between the intermediate rewiring tape (103) and the substrate (104) are encapsulated by plastic mould material.
7. Stacked electronic component (100) comprising: the semiconductor assembly of one of claims 1 to 6, and a second semiconductor chip (101) mounted on the upper surface of the intermediate rewiring tape (103) .
8. A stacked electronic component (100) according to claim 7 characterised in that the lateral arrangement of the third contact areas (121) corresponds to that of the chip contact areas (110) on the second semiconductor chip (101) and the second semiconduc¬ tor chip (101) is electrically connected to the rewiring tape (103) by microscopic solder balls (111) between the chip contact areas (110) and third contact areas (121) .
9. A stacked electronic component (100) according to claim 7 or claim 8 characterised in that the semiconductor chips (101, 102) are encapsulated by plastic mould material.
10. Method to assemble a semiconductor chip assembly including the steps of: providing a substrate board (104) including a plurality of first contact areas (105) and second contact areas (112) positioned on its upper surface, providing at least one semiconductor chip (102) with chip contact areas (110) on its active surface; mounting a first semiconductor chip (102) on the sub¬ strate board (104) with the chip contact pads (110) and first contact pads (105) of the substrate board (104), providing a rewiring strip (127) which includes tape conductor tracks (118) lying between an upper (116) and lower (117) polyimide foil tape, the rewiring strip (127) including a plurality of intermediate rewiring tapes (103) arranged at intervals along the length of the strip (127), each intermediate rewiring tape 103 having a plurality of third contact areas (121) and fourth contact areas (122) connected by tape conductor tracks (118), forming the intermediate rewiring tape (103) for the assembly (100) from the rewiring strip (127) by press¬ ing a section of the rewiring strip (127) into a mould (128) of a template holder (129) to provide a flat bot- tomed recess (119) in its central portion, and separat¬ ing the intermediate rewiring tape (103) from the re¬ wiring strip (127), applying adhesive (120) to the upper rear surface of the first semiconductor chip (102), - attaching the pre-formed intermediate rewiring tape (103) to the rear surface of the first semiconductor chip (102), electrically connecting the fourth contact areas (122) of the intermediate rewiring tape (103) to the second contact pads (112) of the substrate board (104), and removing the template holder (129) leaving the pre¬ formed intermediate rewiring tape (103) attached to the substrate board (104) and lower semiconductor chip (102) .
11. Method to assemble a semiconductor chip assembly according to claim 10 characterised in that the fourth contact areas (122) of the intermediate rewir- ing tape (103) are provided with a lateral arrangement which corresponds to the lateral arrangement of the second contact areas (112) of the substrate board (104) and sol- der balls (124) are attached to the fourth contact areas (122) positioned on the bottom surface of the intermediate rewiring tape (103) .
12. Method to assemble a semiconductor chip assembly according to claim 10 or claim 11 characterised in that the first semiconductor chip (102) is encapsulated by plastic mould material before the intermediate rewiring tape (103) is attached.
13.Method to assemble a semiconductor chip assembly according to one of claims 10 to 12 characterised in that characterised in that the contacts (124) between the in¬ termediate rewiring foil (103) and the substrate (104) are encapsulated by plastic mould material.
14. Method to assemble a stacked electronic component (100) comprising the steps of: providing a semiconductor chip assembly of one of claims
10 to 13, mounting a second semiconductor chip (101) on the upper surface of the intermediate rewiring tape (103) .
15. Method to assemble a stacked electronic component (100) according to claim 14 characterised in that the third contact areas (121) are provided with an ar- rangement corresponding to that of the chip contact areas
(110) on second semiconductor chip (101) and the second semiconductor chip (101) is electrically connected to the rewiring tape (103) by microscopic solder balls (111) be¬ tween the chip contact areas (110) and third contact areas (121) .
16. Method to assemble a stacked electronic component (100) according to claim 14 or claim 15 characterised in that the electrical connection between the semiconductor chips
(102) and the substrate board (104), the second semicon- ductor chip (101) and the intermediate rewiring substrate
(103) and the intermediate rewiring substrate (103) and the substrate board (104) is performed in one process step.
17. Method to assemble a stacked electronic component (100) according to one of claims 14 to 16, characterised in that the semiconductor chips (101, 102) are encapsulated by plastic mould material in one process step.
PCT/IB2004/003175 2004-09-30 2004-09-30 Semiconductor chip assembly including stacked components and method for producing it WO2006035258A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/IB2004/003175 WO2006035258A1 (en) 2004-09-30 2004-09-30 Semiconductor chip assembly including stacked components and method for producing it

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WO2006035258A1 true WO2006035258A1 (en) 2006-04-06

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EP0730394A1 (en) * 1995-03-03 1996-09-04 International Business Machines Corporation Thermoformed three dimensional wiring module
US6521483B1 (en) * 1999-07-22 2003-02-18 Seiko Epson Corporation Semiconductor device, method of manufacture thereof, circuit board, and electronic device
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