WO2006030513A1

WO2006030513A1 - Unbalance-balance converter

Info

Publication number: WO2006030513A1
Application number: PCT/JP2004/013560
Authority: WO
Inventors: Masayoshi Suzuki
Original assignee: Fujitsu Limited
Priority date: 2004-09-16
Filing date: 2004-09-16
Publication date: 2006-03-23

Abstract

An unbalance-balance converter connected with a pair of loads and providing them with a balance signal in which distortion of the balance signal due to mismatch in the impedance of the loads is lessened. The unbalance-balance converter receives an unbalance signal and outputs a balance signal from first and second output terminals. The unbalance-balance converter has a transistor for providing first and second nodes with a signal varying in accordance with the unbalance signal. A collector ground transistor is provided between the first node and the first output terminal being connected with a first load, and between the second node and the second output terminal being connected with a second load.

Description

Specification

Unbalanced to balanced converter

Technical field

[0001] The present invention relates to an unbalance-balance transformer.

Background art

In wireless communication, a frequency mixer or mixer as shown in FIG. 1 is often used when converting the frequency of a signal. This type of mixer receives a signal S to be frequency converted and a signal L having a predetermined frequency, and outputs a signal S ′ having a frequency converted therefrom. The signal L + with a predetermined frequency is a complementary signal having an equal amplitude and a reverse phase, and may be called a complementary signal, a differential signal, or a balanced signal because of its nature!

FIG. 2 shows a circuit example for realizing the mixer as shown in FIG. This circuit is also called a Gillbert circuit. The differential amplifiers 22, 24 are alternately activated by the signal S and the reference voltage Vref. The differential amplifiers 22 and 24 operate in response to the differential signal L, respectively. As a result, a signal S ′ that changes depending on both the frequency of the signal S itself and the frequency of the differential signal L is output.

[0004] Such a differential signal L can be created using, for example, a balun circuit or a transformer. However, when such individual elements are used, there is a problem that the circuit scale becomes large. For this reason, it is conceivable to generate the differential signal L in a semiconductor integrated circuit.

FIG. 3 shows a conventional unbalanced-balanced converter. In general, unbalanced to balanced converters are

It consists of transistor TR101 connected between two reference potentials (V, GND). G cc

The base of the transistor TR101 is connected to the input terminal T101 via the DC blocking capacitor C101, and is also connected to the high potential source V via the noise resistor R101. Tiger cc

The collector of the transistor TR101 is connected to the high potential source VCC through the amplitude adjusting resistor R102, and is also connected to the output terminal T102 through the DC blocking capacitor C102. The emitter of transistor TR101 is connected to the low potential source GND via the amplitude adjustment resistor R103, and also connected to the output terminal T103 via the DC blocking capacitor C103. Is done. A bypass capacitor C104 is also connected between the reference potential sources. The resistance values of the amplitude adjusting resistors R102 and R103 are set equal.

FIG. 4 shows a timing diagram of voltage signals at the input terminal T101 and the output terminals T102 and T103 in order of the upward force. One non-complementary signal that is not complementary is input to the input terminal T101. For example, a signal (local oscillation frequency) equal to the carrier frequency is input. This signal is input to the base of the transistor TR101, and a current flows between the collector and the emitter accordingly. As the base current increases, the collector current also increases and the voltage drop across resistor R102 increases. Accordingly, the potential at the output terminal T102 decreases. On the other hand, when the base current increases, the emitter current also increases, and the voltage drop due to resistor R103 increases. Therefore, the potential at the output terminal T103 increases. Conversely, when the base current decreases, the collector current also decreases and the voltage drop due to resistor R102 decreases. Therefore, the potential at the output terminal T102 increases. On the other hand, when the base current decreases, the emitter current also decreases, and the voltage drop due to resistor R103 decreases. Therefore, the potential at the output terminal T103 decreases. By the operation as described above, an equiamplitude and reverse phase balanced signal such as the differential signal L is output from the output terminals T102 and T103 according to the change of the signal input to the input terminal T101. Such an unbalance-balance converter is described in, for example, Japanese Patent Application Laid-Open No. 10-163810 (Patent Document 1) and Japanese Patent Application Laid-Open No. 11 298295 (Patent Document 2).

Disclosure of the invention

Problems to be solved by the invention

[0007] Under the condition that the impedances of the loads connected to the output terminals T102, T103 having the same resistance value of the amplitude adjusting resistors R102, R103 are equal, the same amplitude as shown in the middle and lower stages of FIG. A negative phase balanced signal is supplied to the load. Since a circuit for processing a differential signal as shown in FIG. 2 is connected to the output terminals T102 and T103, such a condition is generally satisfied. However, the impedances may not be exactly equal due to variations in the pair of loads connected to the output terminals T102 and T103. For example, if there is a mismatch in the resistance component of the load impedance, the amplitude of the differential signal is mainly disturbed, and the amplitude is not equal. Mismatch in reactance component of load impedance If this is the case, the phase of the differential signal is mainly disturbed and the phases are not opposite to each other. The signal at output terminal T102 changes depending on the impedance of the load connected to it and the combined impedance of amplitude adjustment resistor R102, and the signal at output terminal T103 is also the impedance of the load connected to it. This is because it changes depending on the combined impedance with the amplitude adjusting resistor R103. If the relationship between the amplitude and phase of the differential signal is disturbed, the contents of signal processing performed based on the differential signal are adversely affected, and the signal quality is degraded. In general, since the impedance of the element varies depending on the operating frequency (ω), the problem regarding the mismatch of the impedance of the load becomes more serious as the signal frequency becomes higher.

[0008] The inventions described in the above-mentioned Patent Documents 1 and 2 are designed to address the mismatch in impedance of the load connected to the output terminal that is trying to improve the non-uniformity of the amplitude adjustment resistor connected to the transistor. Not what you want.

[0009] The present invention addresses at least one of the above-mentioned problems, and the problem is that an unbalance-balance change in which a pair of loads are connected and a balanced signal is given to them is used. It is to provide an unbalanced balanced converter that reduces the distortion of the balanced signal caused by the mismatch.

Means for solving the problem

[0010] In one aspect of the present invention, an unbalanced balanced variable that receives an unbalanced signal and outputs a balanced signal from the first and second output terminals is used. This unbalance-balance change has a transistor for supplying a signal that changes in accordance with the unbalance signal to the first and second nodes. A collector is provided between the first node and the first output terminal connected to the first load, and between the second node and the second output terminal connected to the second load. A ground transistor is provided.

The invention's effect

[0011] According to the present invention, a pair of loads are connected, and an unbalanced and unbalanced balance that gives a balanced signal to them is reduced, thereby reducing the distortion of the balanced signal due to the mismatch of the impedances of the load. be able to.

Brief Description of Drawings FIG. 1 is a diagram showing a mixer.

FIG. 2 is a diagram showing a circuit example for realizing a mixer.

FIG. 3 is a diagram showing a conventional unbalanced-equilibrium transformation.

FIG. 4 is a timing diagram of signals in the unbalance-balance converter.

FIG. 5 is a diagram showing unbalance-equilibrium transformation according to an embodiment of the present invention.

FIG. 6 is an explanatory diagram for explaining impedance matching.

FIG. 7 is a diagram showing unbalance-equilibrium transformation according to an embodiment of the present invention.

FIG. 8 is a diagram showing unbalance-equilibrium transformation according to one embodiment of the present invention.

FIG. 9 is a diagram showing a differential input type analog-digital converter.

Explanation of symbols

[0013] 22, 24 differential circuit;

T101 input terminal; T102, T103 output terminal; TR101 transistor; R101 bias resistor; R102, R103 amplitude adjustment resistor; C101, 102, 103 DC blocking capacitor; C104 nopass capacitor;

T1, input terminals; T2, T3 output terminals; TR1, TR11, TR21 transistors; R1, Rl l, R21, R12, R22 bias resistors; R2, R3 amplitude adjustment resistors; CI, C2, C3, C12, C22 DC blocking Capacitors; C4, Cl l, C21 nopass capacitors;

R13, R23 Impedance matching element

BEST MODE FOR CARRYING OUT THE INVENTION

[0014] An unbalanced-balanced converter according to an aspect of the present invention receives an unbalanced signal at an input terminal and outputs a balanced signal from the first and second output terminals. One transistor constituting the unbalanced-balanced converter supplies a signal that changes in accordance with the unbalanced signal to the first and second nodes. A grounded collector transistor is provided between the first node and the first output terminal connected to the first load. A grounded collector transistor is also provided between the second node and the second output terminal connected to the second load.

In the common collector transistor, the input / output signals have the same amplitude and the same phase, and the input impedance is extremely large. Therefore, equal amplitude and in-phase signals are generated at the first and second nodes and the first and second output terminals regardless of the connected load. For this reason, it is connected to the first and second output terminals. Even if there is a difference in the impedance of the load, the balanced signal from which the first and second output terminal forces are output is properly maintained at the same amplitude and in reverse phase.

In one aspect of the present invention, the first and second nodes are connected to a collector and an emitter of the transistor. As a result, an unbalanced-balanced converter with excellent high-frequency characteristics can be constructed.

In one aspect of the present invention, the first and second output terminals are connected to a frequency mixer. In one aspect of the present invention, the first and second output terminals are connected to an analog-digital converter.

In one aspect of the present invention, an impedance matching element is provided between the grounded collector transistor and the first output terminal, and between Z or the grounded collector transistor and the second output terminal. As a result, it is possible to output a good balanced signal while ensuring impedance matching at the output terminal of the unbalanced-balanced variable.

In one aspect of the present invention, two or more collector-grounded transistors connected in series are provided between the first node and the first output terminal or between the second node and the second output terminal. . This improves the ability to prevent reverse transmission of current from the output terminal side to the signal source side.

[0020] In one embodiment of the present invention, since the unbalance-balance change is constituted by a semiconductor integrated circuit, the circuit scale can be reduced as compared with the case where it is constituted by individual elements.

Example 1

[0021] FIG. 5 illustrates an unbalance-equilibrium change according to one embodiment of the present invention. In general, the unbalanced and balanced transformation 500 includes a conversion unit 501, a first output unit 510, and a second output unit 520. The conversion unit 501 includes a transistor TR1 connected between two high and low reference potentials (V, GND).

CC

Composed. The base of the transistor TR1 is connected to the input terminal T1 through the DC blocking capacitor C1, and is also connected to the high potential source V through the bias resistor R1. Dora

CC

The collector of transistor TR1 is connected to high potential source V via amplitude adjustment resistor R2

CC

On the other hand, it is also connected to the first node A via the DC blocking capacitor C2. The emitter of the transistor TR1 is connected to the low potential source GND through the amplitude adjusting resistor R3, and is also connected to the second node B through the DC blocking capacitor C3. Between the reference potential sources, A pass capacitor C4 is also connected.

[0022] The first output unit 510 is a transistor connected between two reference potentials (V, GND).

cc

Consists of TR11. The transistor TR11 is provided so as to function as a common collector transistor (or an emitter-hollow type transistor). The base of the transistor TR11 is connected to the first node A, while the high potential source V is connected via the bias resistor R11.

CC

Also connected to. The collector of the transistor TR11 is connected to the high potential source V. Trang

CC

The emitter of the register TRl 1 is connected to the low potential source GND through the bias resistor R12, and is also connected to the first output terminal T2 through the DC blocking capacitor C12. A bypass capacitor C11 is also connected between the reference potential sources.

The second output unit 520 is provided to have the same configuration as the first output unit 510. The second output section 520 is also connected to the transistor TR21 connected between the high and low reference potentials (V, GND).

cc

Composed. This transistor TR21 is also provided to function as a common collector transistor. The base of the transistor TR21 is connected to the second node B, and is also connected to the high potential source Vcc via the noise resistor R21. The collector of transistor TR21 is connected to the high potential source Vcc. The emitter of the transistor TR21 is connected to the low potential source GND via the noise resistor R22, and is also connected to the second output terminal T2 via the DC blocking capacitor C22. A bypass capacitor C21 is also connected between the reference potential sources.

[0024] The noise resistors Rl, Rll, R21 have a relatively large resistance value, for example, several thousand ohms. The amplitude adjusting resistors R2, R3 have a relatively small resistance value, for example several hundred ohms. The resistance values of the noise resistors R2 and R3 are set equal. Also, the resistance values of the amplitude adjusting resistors R12 and R22 are set equal. The DC blocking capacitor and the bypass capacitor have capacitance values such as tens to thousands of picofarads. These numerical values are merely examples, and various resistance values and capacitance values can be selected depending on the application.

[0025] The operation will now be described. A single unbalanced signal such as a local oscillation frequency is input to the input terminal T1. This signal is input to the base of the transistor TR1, and a current flows between the collector and the emitter accordingly. As the base current increases, the collector The current also increases and the voltage drop due to resistor R2 increases. Therefore, the potential at the first node A drops. On the other hand, when the base current increases, the emitter current also increases and the voltage drop due to resistor R3 also increases. Therefore, the potential at the second node B increases. Conversely, when the base current decreases, the collector current also decreases and the voltage drop due to resistor R2 decreases. Therefore, the potential at the first node A increases. On the other hand, when the base current decreases, the emitter current also decreases, and the voltage drop due to resistor R3 decreases. Therefore, the potential at the second node B decreases. As a result of the above operation, when a signal as shown in the upper part of FIG. 4 is input to the input terminal T1, the first and second nodes A and B are shown in the middle and lower parts of FIG. A balanced signal is output. Up to this point, the operation of the circuit described in Figure 3 is almost the same.

In the present embodiment, a first output unit 510 is provided between the first node A and the first output terminal T2. A second output unit 520 is provided between the second node B and the second output terminal T3. The first output unit 510 includes a grounded collector transistor TR11. In the common collector transistor, the signal flowing through the base and the signal flowing through the emitter are of equal amplitude and in phase. Therefore, signals having the same amplitude and the same phase are generated at the first node A and the first output terminal T2. In addition, the grounded collector transistor has a very large input impedance to the base. Therefore, the impedance when the first node A force is viewed on the load side is constant regardless of the load connected to the first output terminal T2. For this reason, the signal generated at the first node A (and the first output terminal T2) does not depend on the combined impedance of the load and is determined by the amplitude adjustment resistor R2. In addition, the grounded collector transistor has a high degree of isolation (isolation) between the emitter and the emitter due to very little reverse transmission of current to the base. However, the output impedance of the common collector transistor is very small. Therefore, when generating a signal at the first output terminal T2, there is very little power loss due to leakage current and output impedance.

Similarly, the second output unit 520 is also composed of a common collector transistor TR21. Therefore, signals having the same amplitude and the same phase are generated at the second node B and the second output terminal T3. Furthermore, the impedance when the load side is viewed from the second node B is constant regardless of the load connected to the second output terminal T3. Therefore, the signal generated at the second node B (and the second output terminal T3) The signal does not depend on the combined impedance of the load and is determined by the amplitude adjustment resistor R3. In addition, due to the nature of the grounded-collector transistor TR21, when generating a signal at the second output terminal T3, power loss due to leakage current and output impedance is extremely small.

[0028] Therefore, if the balance of the amplitude adjusting resistors R2 and R3 is accurately maintained, a good balance of equal amplitude and reverse phase can be obtained regardless of the load connected to the first and second output terminals T2 and T3. Signals are generated at the first and second nodes A and B, and are output as they are from the first and second output terminals T2 and T3.

[0029] Circuits such as the first and second output units 510 and 520 can be easily integrated together with a circuit such as the conversion unit 501, so it is necessary to consider a significant increase in circuit scale. do not do. Example 2

FIG. 6 is an explanatory diagram that simplifies the unbalance-equilibrium change as shown in FIG. In the figure, the left side of the first and second output terminals T2 and T3 shows the unbalance-balance converter side, and the right side shows the connected loads Z and Z. The source that generates the balanced signal is S

1 and 2

, S. Elements drawn between the first node A and the first output terminal T2

1 2

Z represents the impedance when the signal source side is viewed from the first output terminal T2. Similarly,

1S

The element Z drawn between the second node B and the second output terminal T3 is connected to the second output terminal T3.

2S

It represents the impedance when looking at the signal source side. Where z, Z, Z, Z

Note that 1L 2L IS 2S is a reference symbol and also represents impedance.

[0031] In order to efficiently transmit a high-frequency signal to the load side without loss, it is necessary to match impedances at the first and second output terminals T2 and T3. Z = Z and Z

IS 1L 2

It is necessary to set = Z. In the example of Figure 5, Z is the nature of a common collector transistor.

S 2L IS, 2S

Due to the very small Z 0. Therefore, z ≠ z and z ≠ z

IS, 2S IS 1L 2S 2L For this reason, when the unbalanced signal is a high-frequency signal, a slight reflected wave or standing wave is generated in the circuit of FIG. 5, and the transmission efficiency may be reduced.

In this embodiment, in order to suppress such deterioration of transmission efficiency, Z = Z and Z

IS 1L 2S

= Z satisfies the elements between the first node A and the first output terminal T2 and the second node B.

2

And the second output terminal T3. Even with such an element, in Example 1, The described behavior is not harmed. This is because the input impedance when the load side is viewed from the first and second nodes A and B is high impedance, and the element impedance Z,

1S

Z does not depend on the isolation of the elements Z and Z (first and second outputs)

2S IS 2S

This is because the degree of suppression of leakage current from terminals Τ2 and T3 to the first and second nodes A and B does not worsen.

[0033] FIG. 7 illustrates an unbalance-equilibrium change according to one embodiment of the present invention. In general, this circuit is similar to that shown in FIG. 5, but impedance matching elements Z and Z are provided at the output ends of the first and second output sections 510 and 520, respectively, in accordance with the above consideration. . Impi

IS 2S

A dance matching element generally has a resistance component and a reactance component. However, lines, elements or circuits with a characteristic impedance of, for example, 50 ohms are often connected to this type of circuit where high frequency differential signals are transmitted. For this reason, even when impedance matching is performed at the output terminals T2 and T3, the impedance matching elements are represented as resistors R13 and R23 in the illustrated example in which the resistance values are mainly matched. The impedance (resistance value in the example shown) of the impedance matching element is determined depending on the load value. If the impedance of the pair of loads connected to the first and second output terminals T2 and T3 is equal to each other, the impedance of the impedance matching element is also set equal.

[0034] According to the present embodiment, a pair of elements having substantially the same impedance are inserted between the pair of output terminals of the unbalanced-balanced variable ^^ and the load, respectively. A good balanced signal can be output while ensuring consistency. It should be noted that such an advantage cannot be obtained from a conventional circuit as shown in FIG. The reason is as follows. First, it is assumed that a pair of loads having the same impedance are connected to the output terminals T102 and T103 of the circuit shown in FIG. 3 so that a good balanced signal is output. In this circuit, the impedance when the signal source side is viewed from the output terminals T102 and T103 is different. Therefore, in order to ensure impedance matching at the output terminals T102 and T103, it is necessary to insert elements having different impedances between the output terminals T102 and T103 and the load, respectively. In this way, the signal transmission efficiency at the two output terminals cannot be improved. However, the two output terminals have different impedances. Therefore, the balanced signal of the two output terminal forces will be greatly distorted. In the example shown in Fig. 5, the impedance when the signal source side is viewed from the first and second output terminals T2 and T3 is equal to each other due to the nature of the collector grounded transistor. Therefore, the above inconvenience does not occur.

Example 3

In the first and second embodiments, the transistors used are NPN bipolar transistors, but all or part of them may be PNP transistors. Figure 8 shows an unbalance-equilibrium transformation constructed using PNP transistors. In this case, it is necessary to change the relative magnitude of the two reference potentials, and the positive reference potential (+ V) is negative.

CC

Changed to quasi-potential (-V). In addition, the field effect achieved only by bipolar transistors.

CC

It is also possible to construct a circuit using a fruit transistor (FET) or other transistor. However, it is preferable to use bipolar transistors with good high frequency characteristics for the transistors of the first and second output sections. The high-frequency characteristics are, for example, that the input and output signals are in-phase and of equal amplitude with respect to radio frequency signals, have high input impedance and low output impedance, and have sufficient isolation from output side to input side. To be secured.

Industrial applicability

[0036] The present invention can be used for any unbalanced-balanced variable that generates equal amplitude and antiphase differential signals, complementary signals, or balanced signals based on the unbalanced signals. Such an unbalanced-balanced converter may be used in a mixer, a quadrature modulator, or the like for performing frequency conversion between low frequency, intermediate frequency, and z or high frequency signals. Also unbalanced

—Balanced converters may be used to create input signals for differential input analog-to-digital converters, as shown in Figure 9. Analog digital changes ^^ to which a balanced signal is input, unlike those to which an unbalanced signal is input, cancel out common-mode noise components in the input signal and suppress noise from being mixed into the output signal. Can do.

Claims

The scope of the claims

[1] An unbalance-equilibrium converter that receives an unbalanced signal and outputs a balanced signal from the first and second output terminals. The unbalanced signal changes in response to the unbalanced signal. It has a transistor that feeds two nodes,

Collector ground between the first node and the first output terminal connected to the first load and between the second node and the second output terminal connected to the second load A transistor is provided

An unbalance-equilibrium change that is characterized by ^^.

[2] The unbalance-balance change according to claim 1, wherein the first and second nodes are connected to a collector and an emitter of the transistor.

[3] The unbalanced signal is a radio frequency signal

The unbalance-equilibrium change according to claim 1, characterized in that:

[4] The first and second output terminals are connected to a frequency mixer

The unbalance-equilibrium change according to claim 3, characterized by the above.

[5] The first and second output terminals are connected to an analog-digital converter

The unbalance-equilibrium change according to claim 1, characterized in that:

[6] Impedance matching elements are provided between the grounded collector transistor and the first output terminal, and between Z or the grounded collector transistor and the second output terminal.

The unbalance-equilibrium change according to claim 1, characterized in that:

[7] The impedance matching element includes a resistor.

The unbalance-equilibrium change according to claim 1, characterized in that:

[8] Grounded transistor power consisting of NPN transistor

The unbalance-equilibrium change according to claim 1, characterized in that: