WO2006028577A2 - Using different gate dielectrics with nmos and pmos transistors of a complementary metal oxide semiconductor integrated circuit - Google Patents

Using different gate dielectrics with nmos and pmos transistors of a complementary metal oxide semiconductor integrated circuit Download PDF

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Publication number
WO2006028577A2
WO2006028577A2 PCT/US2005/025337 US2005025337W WO2006028577A2 WO 2006028577 A2 WO2006028577 A2 WO 2006028577A2 US 2005025337 W US2005025337 W US 2005025337W WO 2006028577 A2 WO2006028577 A2 WO 2006028577A2
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Prior art keywords
nmos
dielectric
gate dielectric
forming
gate
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Ceased
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PCT/US2005/025337
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French (fr)
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WO2006028577A3 (en
Inventor
Matthew Metz
Suman Datta
Jack Kavalieros
Mark Doczy
Justin Brask
Robert Chau
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Intel Corp
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Intel Corp
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Priority to DE112005001787T priority Critical patent/DE112005001787T5/en
Priority to GB0700529A priority patent/GB2431289B/en
Priority to JP2007521707A priority patent/JP2008507141A/en
Publication of WO2006028577A2 publication Critical patent/WO2006028577A2/en
Publication of WO2006028577A3 publication Critical patent/WO2006028577A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0144—Manufacturing their gate insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0181—Manufacturing their gate insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Definitions

  • CMOS integrated circuits include NMOS transistors and PMOS transistors. Generally, these transistors may be made by forming a gate dielectric and then forming NMOS and PMOS gate structures on top of that dielectric.
  • the gate electrode structures may be made of polysilicon, suicide, or metal.
  • MOS field-effect transistors with very thin gate dielectrics made from silicon dioxide may experience unacceptable gate leakage currents. Forming the gate dielectric from certain high-k dielectric materials, instead of silicon dioxide, can reduce gate leakage. Because, however, such a dielectric may not be compatible with polysilicon, it may be desirable to use metal gate electrodes in devices that include high-k gate dielectrics.
  • a replacement gate process may be used to form gate electrodes from different metals.
  • a first polysilicon layer bracketed by a pair of spacers, is removed to create a trench between the spacers.
  • the trench is filled with a first metal.
  • a second polysilicon layer is then removed, and replaced with a second metal that differs from the first metal. Because this process requires multiple etch, deposition, and polish steps, high volume manufacturers of semiconductor devices may be reluctant to use it.
  • a subtractive approach may be used.
  • a metal gate electrode is formed on a high-k gate dielectric layer by depositing a metal layer on the dielectric layer, masking the metal layer, and then removing the uncovered part of the metal layer and the underlying portion of the dielectric layer.
  • the exposed sidewalls of the resulting high-k gate dielectric layer render that layer susceptible to lateral oxidation, which may adversely affect its physical and electrical properties.
  • complementary metal oxide semiconductor fabrication techniques there is a need for complementary metal oxide semiconductor fabrication techniques.
  • Figure 1 is a partial, enlarged, cross-sectional view of another embodiment of the present invention at an early stage of manufacture in accordance with one embodiment of the present invention
  • Figure 2 is a partial, enlarged, cross-sectional view of the embodiment shown in Figure 1 at a subsequent stage of manufacture in accordance with one embodiment of the present invention
  • Figure 3 is a partial, enlarged, cross-sectional view of the embodiment shown in Figure 2 at a subsequent stage of manufacture in accordance with one embodiment of the present invention
  • Figure 4 is a partial, enlarged, cross-sectional view of the embodiment shown in Figure 3 at a subsequent stage of manufacture in accordance with one embodiment of the present invention
  • Figure 5 is a partial, enlarged, cross-sectional view of the embodiment shown in Figure 4 at a subsequent stage of manufacture in accordance with one embodiment of the present invention
  • Figure 6 is a partial, enlarged, cross-sectional view of the embodiment shown in Figure 5 at a subsequent stage of manufacture in accordance with one embodiment of the present invention
  • Figure 7 is a partial, enlarged, cross-sectional view of the embodiment shown in Figure 6 at a subsequent stage of manufacture in accordance with one embodiment of the present invention
  • Figure 8 is a partial, enlarged, cross-sectional view of the embodiment shown in Figure 7 at a subsequent stage of manufacture in accordance with one embodiment of the present invention
  • Figure 9 is a partial, enlarged, cross-sectional view of the embodiment shown in Figure 8 at a subsequent stage of manufacture in accordance with one embodiment of the present invention after subsequent processing
  • Figure 10 is a partial, enlarged, cross-sectional view of the embodiment shown in Figure 9 at a subsequent stage of manufacture in accordance with one embodiment of the present invention.
  • CMOS Complementary metal oxide semiconductor
  • the dielectrics may be different in terms of the materials used, their thicknesses, or the techniques used to form the gate dielectrics, to mention a few examples.
  • the gate dielectric can be tailored to the particular type of transistor, be it an NMOS or PMOS transistor, as the case may be.
  • a substrate 32 may be covered by a masking material 34 such as resist. Then, as shown in Figure 2, the masking material 34 may be exposed to create an exposed region 34a on the right and an unexposed region 34 on the left. In many cases, the regions 34 and 34a may be widely spaced over the semiconductor structure 32 and may correspond to active areas where NMOS versus PMOS transistors will ultimately be formed.
  • a masking material 34 such as resist.
  • the masking material 34 may be exposed to create an exposed region 34a on the right and an unexposed region 34 on the left.
  • the regions 34 and 34a may be widely spaced over the semiconductor structure 32 and may correspond to active areas where NMOS versus PMOS transistors will ultimately be formed.
  • the exposed wafer shown in Figure 2 may then be patterned to remove the exposed material 34a. Alternatively, unexposed material may be selectively removed. Then, as shown in Figure 3, an opening 36 may be created.
  • a gate dielectric 38 may then be deposited or grown over the resulting structure.
  • the gate dielectric 38 is formed on top of the substrate 32 and also on top of the masking layer 34.
  • the overlying portion of the gate dielectric 38 is also lifted off.
  • the gate dielectric 38 is left only where it is directly deposited on the substrate 32 in one embodiment of the present invention.
  • the wafer may be covered with another masking layer 40 which, again, may be resist in one embodiment of the present invention.
  • the masking layer 40 may be differentially exposed.
  • the layer 40a has been modified by exposure so that, as shown in Figure 8 on the left, it may be selectively removed to create a gap 42.
  • a gate dielectric 44 may be deposited or grown over the substrate 32. The layer 44 accumulates on the substrate 32 on the left and over the masking layer 40 on the right.
  • the dielectric 44 over the masking layer 40 may be lifted off, leaving the dielectric layer 44 only over the substrate 32.
  • different dielectric materials 44 and 38 are formed in different regions to act as the gate dielectrics for NMOS versus PMOS transistors or for transistors of the same type used for different applications.
  • the PMOS and NMOS transistors may be built up using an appropriate fabrication technology.
  • gate electrodes may be formed of polysilicon, suicide, metal, or any other appropriate material.
  • the dielectric 38 can be selected to have characteristics to optimize the performance of either an NMOS or PMOS transistor to be formed in the region 36.
  • the gate dielectric 38 material, thickness or formation technique may be tailored for its particular application.
  • the NMOS transistor may use a larger conduction band offset material, such as silicon dioxide
  • the PMOS transistor may use a material with a higher dielectric constant, such as hafnium dioxide, which also happens to have good band offset for holes.
  • Higher dielectric constants may be greater than ten in one embodiment.
  • a thicker material may be utilized for the NMOS than the PMOS transistors in some cases.
  • hafnium dioxide leaks electrons more than holes, so a thicker hafnium dioxide layer may be utilized on the NMOS transistors and a thinner hafnium dioxide layer may be utilized on the PMOS transistors.
  • the hafnium dioxide gate dielectric may be 30 Angstroms for the NMOS transistors and 15 Angstroms for the gate dielectric for PMOS transistors.
  • the deposition techniques may be different for the two gate dielectrics.
  • materials for the NMOS transistor such as silicon dioxide, may be deposited using diffusion techniques, while atomic layer deposition, sputtering, or metal organic chemical vapor deposition (MOCVD) may be utilized to deposit high dielectric constant materials such as hafnium dioxide.
  • MOCVD metal organic chemical vapor deposition
  • a single gate dielectric material may not provide the highest performance for both NMOS and PMOS structures. This may be due, for example, to poor band offset with conduction or valence bonds, incompatibility to the gate electrode material, incompatibility with gate electrode processing or thickness requirements.
  • By selecting the better candidate dielectric film for each structure, and depositing the best film with the optimal thickness higher 5 performance complementary metal oxide semiconductor devices may be created in some embodiments.
  • By using better gate dielectric material of optimal thickness for each electrode stack, higher performance structures may be created that may exhibit higher mobility, higher saturation current, or better threshold voltage in some embodiments.

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

Complementary metal oxide semiconductor integrated circuits may be formed with NMOS and PMOS transistors having different gate dielectrics. The different gate dielectrics may be formed, for example, by a subtractive process. The gate dielectrics may differ in material, thickness, or formation techniques, as a few examples.

Description

USING DIFFERENT GATE DIELECTRICS WITH NMOS
AND PMOS TRANSISTORS OF A COMPLEMENTARY
METAL OXIDE SEMICONDUCTOR INTEGRATED CIRCUIT
Background
This invention relates generally to semiconductor technology, semiconductor processing, and the formation of complementary metal oxide semiconductor integrated circuits. Complementary metal oxide semiconductor (CMOS) integrated circuits include NMOS transistors and PMOS transistors. Generally, these transistors may be made by forming a gate dielectric and then forming NMOS and PMOS gate structures on top of that dielectric. The gate electrode structures may be made of polysilicon, suicide, or metal. MOS field-effect transistors with very thin gate dielectrics made from silicon dioxide may experience unacceptable gate leakage currents. Forming the gate dielectric from certain high-k dielectric materials, instead of silicon dioxide, can reduce gate leakage. Because, however, such a dielectric may not be compatible with polysilicon, it may be desirable to use metal gate electrodes in devices that include high-k gate dielectrics.
When making a CMOS device that includes metal gate electrodes, a replacement gate process may be used to form gate electrodes from different metals. In that process, a first polysilicon layer, bracketed by a pair of spacers, is removed to create a trench between the spacers. The trench is filled with a first metal. A second polysilicon layer is then removed, and replaced with a second metal that differs from the first metal. Because this process requires multiple etch, deposition, and polish steps, high volume manufacturers of semiconductor devices may be reluctant to use it.
Rather that apply a replacement gate process to form a metal gate electrode on a high-k gate dielectric layer, a subtractive approach may be used. In such a process, a metal gate electrode is formed on a high-k gate dielectric layer by depositing a metal layer on the dielectric layer, masking the metal layer, and then removing the uncovered part of the metal layer and the underlying portion of the dielectric layer. Unfortunately, the exposed sidewalls of the resulting high-k gate dielectric layer render that layer susceptible to lateral oxidation, which may adversely affect its physical and electrical properties. Thus, there is a need for complementary metal oxide semiconductor fabrication techniques.
Brief Description of the Drawings
Figure 1 is a partial, enlarged, cross-sectional view of another embodiment of the present invention at an early stage of manufacture in accordance with one embodiment of the present invention;
Figure 2 is a partial, enlarged, cross-sectional view of the embodiment shown in Figure 1 at a subsequent stage of manufacture in accordance with one embodiment of the present invention;
Figure 3 is a partial, enlarged, cross-sectional view of the embodiment shown in Figure 2 at a subsequent stage of manufacture in accordance with one embodiment of the present invention; Figure 4 is a partial, enlarged, cross-sectional view of the embodiment shown in Figure 3 at a subsequent stage of manufacture in accordance with one embodiment of the present invention;
Figure 5 is a partial, enlarged, cross-sectional view of the embodiment shown in Figure 4 at a subsequent stage of manufacture in accordance with one embodiment of the present invention;
Figure 6 is a partial, enlarged, cross-sectional view of the embodiment shown in Figure 5 at a subsequent stage of manufacture in accordance with one embodiment of the present invention;
Figure 7 is a partial, enlarged, cross-sectional view of the embodiment shown in Figure 6 at a subsequent stage of manufacture in accordance with one embodiment of the present invention;
Figure 8 is a partial, enlarged, cross-sectional view of the embodiment shown in Figure 7 at a subsequent stage of manufacture in accordance with one embodiment of the present invention; Figure 9 is a partial, enlarged, cross-sectional view of the embodiment shown in Figure 8 at a subsequent stage of manufacture in accordance with one embodiment of the present invention after subsequent processing; and Figure 10 is a partial, enlarged, cross-sectional view of the embodiment shown in Figure 9 at a subsequent stage of manufacture in accordance with one embodiment of the present invention.
Detailed Description Complementary metal oxide semiconductor (CMOS) integrated circuits may be fabricated with NMOS and PMOS transistors having different gate dielectrics. The dielectrics may be different in terms of the materials used, their thicknesses, or the techniques used to form the gate dielectrics, to mention a few examples. As a result, the gate dielectric can be tailored to the particular type of transistor, be it an NMOS or PMOS transistor, as the case may be.
Referring to Figure 1 , initially, a substrate 32 may be covered by a masking material 34 such as resist. Then, as shown in Figure 2, the masking material 34 may be exposed to create an exposed region 34a on the right and an unexposed region 34 on the left. In many cases, the regions 34 and 34a may be widely spaced over the semiconductor structure 32 and may correspond to active areas where NMOS versus PMOS transistors will ultimately be formed.
Referring to Figure 3, the exposed wafer, shown in Figure 2, may then be patterned to remove the exposed material 34a. Alternatively, unexposed material may be selectively removed. Then, as shown in Figure 3, an opening 36 may be created.
In Figure 4, a gate dielectric 38 may then be deposited or grown over the resulting structure. The gate dielectric 38 is formed on top of the substrate 32 and also on top of the masking layer 34.
When the masking layer 34 is removed, as indicated in Figure 5, the overlying portion of the gate dielectric 38 is also lifted off. Thus, the gate dielectric 38 is left only where it is directly deposited on the substrate 32 in one embodiment of the present invention.
Referring to Figure 6, the wafer may be covered with another masking layer 40 which, again, may be resist in one embodiment of the present invention. Then, as shown in Figure 7, the masking layer 40 may be differentially exposed. In the embodiment illustrated, the layer 40a has been modified by exposure so that, as shown in Figure 8 on the left, it may be selectively removed to create a gap 42. Then, as shown in Figure 9, a gate dielectric 44 may be deposited or grown over the substrate 32. The layer 44 accumulates on the substrate 32 on the left and over the masking layer 40 on the right.
Finally, in Figure 10, the dielectric 44 over the masking layer 40 may be lifted off, leaving the dielectric layer 44 only over the substrate 32. As a result, different dielectric materials 44 and 38 are formed in different regions to act as the gate dielectrics for NMOS versus PMOS transistors or for transistors of the same type used for different applications. Thereafter, the PMOS and NMOS transistors may be built up using an appropriate fabrication technology. For example, gate electrodes may be formed of polysilicon, suicide, metal, or any other appropriate material.
In one embodiment, the dielectric 38 can be selected to have characteristics to optimize the performance of either an NMOS or PMOS transistor to be formed in the region 36. For example, the gate dielectric 38 material, thickness or formation technique may be tailored for its particular application.
For example, the NMOS transistor may use a larger conduction band offset material, such as silicon dioxide, and the PMOS transistor may use a material with a higher dielectric constant, such as hafnium dioxide, which also happens to have good band offset for holes. Higher dielectric constants may be greater than ten in one embodiment. As another example, a thicker material may be utilized for the NMOS than the PMOS transistors in some cases. For example, hafnium dioxide leaks electrons more than holes, so a thicker hafnium dioxide layer may be utilized on the NMOS transistors and a thinner hafnium dioxide layer may be utilized on the PMOS transistors. For example, in one embodiment, the hafnium dioxide gate dielectric may be 30 Angstroms for the NMOS transistors and 15 Angstroms for the gate dielectric for PMOS transistors.
As still another example, the deposition techniques may be different for the two gate dielectrics. For example, materials for the NMOS transistor, such as silicon dioxide, may be deposited using diffusion techniques, while atomic layer deposition, sputtering, or metal organic chemical vapor deposition (MOCVD) may be utilized to deposit high dielectric constant materials such as hafnium dioxide.
In some embodiments, a single gate dielectric material may not provide the highest performance for both NMOS and PMOS structures. This may be due, for example, to poor band offset with conduction or valence bonds, incompatibility to the gate electrode material, incompatibility with gate electrode processing or thickness requirements. By selecting the better candidate dielectric film for each structure, and depositing the best film with the optimal thickness, higher 5 performance complementary metal oxide semiconductor devices may be created in some embodiments. By using better gate dielectric material of optimal thickness for each electrode stack, higher performance structures may be created that may exhibit higher mobility, higher saturation current, or better threshold voltage in some embodiments. l o While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.

Claims

What is Claimed:
1. A method comprising: defining NMOS and PMOS transistor areas on a substrate forming a mask over one of the NMOS or PMOS areas; forming a first gate dielectric on the substrate and over the mask to form a transistor of a first conductivity type; masking said first gate dielectric; and forming a second gate dielectric to form a transistor of a second conductivity type.
2. The method of claim 1 including forming said first and second gate dielectrics of different thicknesses.
3. The method of claim 1 including forming said first and second gate dielectrics of different materials.
4. The method of claim 1 including forming first and second gate dielectrics deposited by different techniques.
5. The method of claim 1 including lifting off the dielectric formed over the mask.
6. The method of claim 1 including forming NMOS and PMOS transistors with metal gates.
7. The method of claim 1 including using material with a larger conduction band offset for an NMOS gate dielectric.
8. The method of claim 1 including using a material with a higher dielectric constant as the gate dielectric for a PMOS transistor.
9. The method of claim 1 including using a thicker dielectric for said NMOS transistor than for said PMOS transistor.
10. The method of claim 9 including using first and second dielectrics having dielectric constants greater than 10.
11. A semiconductor structure comprising: a substrate; NMOS and PMOS transistor areas on said substrate; a mask over only one of said areas; and a gate dielectric over both of said areas.
12. The structure of claim 11 wherein said gate dielectric has a dielectric constant greater than 10.
13. The structure of claim 11 wherein said mask is resist.
14. The structure of claim 11 wherein said dielectric is a metal oxide.
15. A method comprising: forming an NMOS transistor of a complementary metal oxide semiconductor integrated circuit in an NMOS region and a PMOS transistor in a PMOS region by masking a PMOS region and forming a first gate dielectric on both PMOS and NMOS regions; and forming a PMOS transistor of said complementary metal oxide semiconductor integrated circuit with a second gate dielectric different than said first gate dielectric.
16. The method of claim 15 including forming said dielectrics having different dielectric thicknesses.
17. The method of claim 15 including forming said dielectrics of different materials.
18. The method of claim 15 including depositing said dielectrics using different deposition techniques.
19. The method of claim 15 including using material with a larger conduction band offset for the first gate dielectric.
20. The method of claim 15 including using a material with a higher dielectric constant as said second gate dielectric.
PCT/US2005/025337 2004-07-28 2005-07-15 Using different gate dielectrics with nmos and pmos transistors of a complementary metal oxide semiconductor integrated circuit Ceased WO2006028577A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
DE112005001787T DE112005001787T5 (en) 2004-07-28 2005-07-15 Use of different gate dielectrics in NMOS and PMOS transistors of an integrated metal oxide semiconductor integrated circuit
GB0700529A GB2431289B (en) 2004-07-28 2005-07-15 Using different gate dielectrics with nmos and pmos transistors of a complementary metal oxide semiconductor integrated circuit
JP2007521707A JP2008507141A (en) 2004-07-28 2005-07-15 Use of different gate dielectrics using NMOS and PMOS transistors in complementary metal oxide semiconductor integrated circuits

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US10/900,585 US7087476B2 (en) 2004-07-28 2004-07-28 Using different gate dielectrics with NMOS and PMOS transistors of a complementary metal oxide semiconductor integrated circuit

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DE112005001787T5 (en) 2007-05-10
TW200618256A (en) 2006-06-01
GB2431289A (en) 2007-04-18
US20060022271A1 (en) 2006-02-02
GB0700529D0 (en) 2007-02-21
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