WO2006016883A1 - Scribed interleaf separator wafer packaging - Google Patents

Scribed interleaf separator wafer packaging Download PDF

Info

Publication number
WO2006016883A1
WO2006016883A1 PCT/US2004/026697 US2004026697W WO2006016883A1 WO 2006016883 A1 WO2006016883 A1 WO 2006016883A1 US 2004026697 W US2004026697 W US 2004026697W WO 2006016883 A1 WO2006016883 A1 WO 2006016883A1
Authority
WO
WIPO (PCT)
Prior art keywords
separator
cut lines
lines
cut
scribed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2004/026697
Other languages
French (fr)
Inventor
Valoris L. Forsyth
Sandrine Charrier
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Illinois Tool Works Inc
Original Assignee
Illinois Tool Works Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Illinois Tool Works Inc filed Critical Illinois Tool Works Inc
Publication of WO2006016883A1 publication Critical patent/WO2006016883A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/10—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof using carriers specially adapted therefor, e.g. front opening unified pods [FOUP]
    • H10P72/19—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof using carriers specially adapted therefor, e.g. front opening unified pods [FOUP] closed carriers
    • H10P72/1924—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof using carriers specially adapted therefor, e.g. front opening unified pods [FOUP] closed carriers characterised by atmosphere control
    • H10P72/1926—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof using carriers specially adapted therefor, e.g. front opening unified pods [FOUP] closed carriers characterised by atmosphere control characterised by the presence of atmosphere modifying elements inside or attached to the closed carrier
    • H10P72/1928—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof using carriers specially adapted therefor, e.g. front opening unified pods [FOUP] closed carriers characterised by atmosphere control characterised by the presence of atmosphere modifying elements inside or attached to the closed carrier characterised by the presence of antistatic elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/10—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof using carriers specially adapted therefor, e.g. front opening unified pods [FOUP]
    • H10P72/19—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof using carriers specially adapted therefor, e.g. front opening unified pods [FOUP] closed carriers
    • H10P72/1911—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof using carriers specially adapted therefor, e.g. front opening unified pods [FOUP] closed carriers characterised by materials, roughness, coatings or the like
    • H10P72/1912—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof using carriers specially adapted therefor, e.g. front opening unified pods [FOUP] closed carriers characterised by materials, roughness, coatings or the like characterised by shock absorbing elements, e.g. retainers or cushions

Definitions

  • This invention pertains to separators used for the packaging and transport of semiconductor wafers.
  • separators In order to maintain electrostatic and mechanical stability during shipping and transport of semiconductor wafers, it is common to use separators between adjacent wafers.
  • One prior art wafer separator uses an embossed grid pattern. While this has been satisfactory in many respects, there have been occurrences of semiconductor wafers and separators within a multi- box canister wherein the wafers and separators have been found stuck together. This produces a "wafer cake" configuration wherein one stack of wafers and separators is difficult to break down. This can cause breakage of the wafers when trying to separate them from the separators. This is typically done manually without the use of automated unpacking equipment. This problem may be caused by the grid pattern embossed on the separators.
  • a separator is provided with a pattern of lines, typically two sets of lines orthogonal to each other. This allows air to flow and circulate.
  • the separators are typically polyethylene, impregnated with a dissipative material, and provided in a circular shape, with many different diameters available.
  • Figure 1 is a plan view of the wafer separator of the present invention.
  • Figure 2 is a detailed view of a portion of Figure 1.
  • FIG. 1 is a plan view of a circular wafer separator 10 of the present invention.
  • Wafer separator 10 may be provided in virtually any shape and size, but circular wafer separators 10 with a 4, 5, 6, 8 or 12 inch diameter are particularly envisioned.
  • Wafer separator 10 is typically made from a polyethylene material, such as Richmond/Valeron®, such as 1207 LLDPE Lamination Grade Film (86-R0438) which is sold by assignee Illinois Tool Works Inc., using the specification number 86-R0438 which details the formulation and property requirements for this antistatic film.
  • Wafer separator 10 is typically 0.006 inches thick, impregnated with a dissipative material which is typically processed to insure that the dissipative material is a part of the material structure while keeping the organic and inorganic contaminate levels below 50 ppm, which is ideal for semiconductor applications.
  • Circular wafer separator 10 is embossed with a first and second set of cut parallel lines, the first set of cut parallel lines typically being perpendicular to the second set of cut parallel lines. Both ends of each line terminate on the periphery of circular wafer separator 10. Moreover, as best shown in Figure 2, the cut parallel lines are typically paired so that the lines within a pair are typically 0.036 inches apart and the pairs are 0.208 inches from adjacent pairs and are cut to a sufficient depth to enable air flow and circulation, providing vacuum release.

Landscapes

  • Packaging Frangible Articles (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Packages (AREA)

Abstract

A separator of semiconductor wafers (10) is made from polyethylene with a dissipative material and includes a first and second set of embossed cut parallel lines. The first set is typically parallel to the second set; and each set includes pairs of cut lines which are spaced from adjacent pairs. The depth of grid lines cut into the material allows air flow, circulation and vacuum release.

Description

SCRIBED INTERLEAF SEPARATOR WAFER PACKAGING This application claims priority from provisional application serial number 60/587,884 filed on July 13, 2004.
BACKGROUND OF INVENTION Field of Invention
This invention pertains to separators used for the packaging and transport of semiconductor wafers.
Description of the Prior Art
In order to maintain electrostatic and mechanical stability during shipping and transport of semiconductor wafers, it is common to use separators between adjacent wafers. One prior art wafer separator uses an embossed grid pattern. While this has been satisfactory in many respects, there have been occurrences of semiconductor wafers and separators within a multi- box canister wherein the wafers and separators have been found stuck together. This produces a "wafer cake" configuration wherein one stack of wafers and separators is difficult to break down. This can cause breakage of the wafers when trying to separate them from the separators. This is typically done manually without the use of automated unpacking equipment. This problem may be caused by the grid pattern embossed on the separators. Each individual square of the grid may behave like a small sucker pad when the wafers are vacuum packed. OBJECTS AND SUMMARY OF THE INVENTION In order to overcome the above deficiencies, a separator is provided with a pattern of lines, typically two sets of lines orthogonal to each other. This allows air to flow and circulate.
This further provides for vacuum release.
The separators are typically polyethylene, impregnated with a dissipative material, and provided in a circular shape, with many different diameters available.
DESCRIPTION OF THE DRAWINGS
Further objects and advantages of the invention will become apparent from the following description and claims, and from the accompanying drawings, wherein:
Figure 1 is a plan view of the wafer separator of the present invention. Figure 2 is a detailed view of a portion of Figure 1.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Figure 1 is a plan view of a circular wafer separator 10 of the present invention. Wafer separator 10 may be provided in virtually any shape and size, but circular wafer separators 10 with a 4, 5, 6, 8 or 12 inch diameter are particularly envisioned.
Wafer separator 10 is typically made from a polyethylene material, such as Richmond/Valeron®, such as 1207 LLDPE Lamination Grade Film (86-R0438) which is sold by assignee Illinois Tool Works Inc., using the specification number 86-R0438 which details the formulation and property requirements for this antistatic film. Wafer separator 10 is typically 0.006 inches thick, impregnated with a dissipative material which is typically processed to insure that the dissipative material is a part of the material structure while keeping the organic and inorganic contaminate levels below 50 ppm, which is ideal for semiconductor applications.
Circular wafer separator 10 is embossed with a first and second set of cut parallel lines, the first set of cut parallel lines typically being perpendicular to the second set of cut parallel lines. Both ends of each line terminate on the periphery of circular wafer separator 10. Moreover, as best shown in Figure 2, the cut parallel lines are typically paired so that the lines within a pair are typically 0.036 inches apart and the pairs are 0.208 inches from adjacent pairs and are cut to a sufficient depth to enable air flow and circulation, providing vacuum release.
Thus the several aforementioned objects and advantages are most effectively attained. Although a single preferred embodiment of the invention has been disclosed and described in detail herein, it should be understood that this invention is in no sense limited thereby and should be determined by the appended claims.

Claims

CLAIMSWhat is Claimed is:
1. A separator for separating semiconductor wafers, the separator being comprised of electrostatic dissipative material and including cut lines wherein both ends of the cut lines terminate on the periphery of said separator.
2. The separator of Claim 1 wherein said cut lines are configured as a first set of cut lines and a second set of cut lines.
3. The separator of Claim 2 wherein said first set of cut lines is perpendicular to said second set of cut lines.
4. The separator of Claim 3 wherein said first and second sets of cut lines are configured in pairs of cut lines, wherein the lines within a given pair are spaced a first distance apart and adjacent pairs of lines are spaced a second distance apart, wherein said first distance is different from said second distance.
5. The separator of Claim 1 wherein said cut lines are cut to a sufficient depth to provide air flow, circulation and vacuum release.
6. The separator of Claim 1 wherein said separator is circular.
7. The separator of Claim 1 wherein said separator is comprised of a polyethylene material.
PCT/US2004/026697 2004-07-13 2004-08-17 Scribed interleaf separator wafer packaging Ceased WO2006016883A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US58788404P 2004-07-13 2004-07-13
US60/587,884 2004-07-13

Publications (1)

Publication Number Publication Date
WO2006016883A1 true WO2006016883A1 (en) 2006-02-16

Family

ID=35839547

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/026697 Ceased WO2006016883A1 (en) 2004-07-13 2004-08-17 Scribed interleaf separator wafer packaging

Country Status (3)

Country Link
CN (1) CN100477099C (en)
MY (1) MY139640A (en)
WO (1) WO2006016883A1 (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5091229A (en) * 1989-10-13 1992-02-25 E. I. Du Pont De Nemours And Company Electronics protective packaging film
US5183699A (en) * 1989-08-01 1993-02-02 Mitsui Toatsu Chemicals, Inc. Wafer processing films
US20020014435A1 (en) * 2000-05-09 2002-02-07 Bores Gregory W. Shock resistant variable load tolerant wafer shipper
US20030005647A1 (en) * 1998-06-11 2003-01-09 Daniel Towery Reactive aqueous metal oxide sols as polishingslurries for low dielectric constant materials
US20040048028A1 (en) * 2002-09-06 2004-03-11 Thomas James R. Plastic packaging cushion
US20040146690A1 (en) * 1997-12-08 2004-07-29 Vermillion Robert J. Packaging material for electrostatic sensitive devices

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09201765A (en) * 1996-01-25 1997-08-05 Shin Etsu Handotai Co Ltd Backing pad and method for polishing semiconductor wafer

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5183699A (en) * 1989-08-01 1993-02-02 Mitsui Toatsu Chemicals, Inc. Wafer processing films
US5091229A (en) * 1989-10-13 1992-02-25 E. I. Du Pont De Nemours And Company Electronics protective packaging film
US20040146690A1 (en) * 1997-12-08 2004-07-29 Vermillion Robert J. Packaging material for electrostatic sensitive devices
US20030005647A1 (en) * 1998-06-11 2003-01-09 Daniel Towery Reactive aqueous metal oxide sols as polishingslurries for low dielectric constant materials
US20020014435A1 (en) * 2000-05-09 2002-02-07 Bores Gregory W. Shock resistant variable load tolerant wafer shipper
US20040048028A1 (en) * 2002-09-06 2004-03-11 Thomas James R. Plastic packaging cushion

Also Published As

Publication number Publication date
CN100477099C (en) 2009-04-08
CN1989599A (en) 2007-06-27
MY139640A (en) 2009-10-30

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