WO2006013973A1

WO2006013973A1 - Switching means driving circuit, switching means driving method, power supply device and switching circuit

Info

Publication number: WO2006013973A1
Application number: PCT/JP2005/014431
Authority: WO
Inventors: Masaji Haneda; Hidehiro Takakusa; Minoru Okada; Haruki Wada
Original assignee: Ntt Data Ex Techno Corporation
Priority date: 2004-08-06
Filing date: 2005-08-05
Publication date: 2006-02-09
Also published as: JP4253318B2; JP2006074991A

Abstract

[PROBLEMS] To provide a switching means driving circuit which does not require an external power supply and to surely on/off drive a switching means at a high speed without requiring the external power supply. [MEANS FOR SOLVING PROBLEMS] A gate driving circuit (1) is provided for inputting a control signal to a gate of an FET (1) to be driven, based on a control pulse (10) inputted from outside of the circuit. In the gate driving circuit, a capacitor (C11) is charged by the control pulse (10), and by the energy charged in the capacitor (C11), the control pulse (10) is amplified in a transistor (TR11) to be inputted to the gate of the FET (1).

Description

Specification

Switching means driving circuit, switching means driving method, power supply device, and switching circuit

Technical field

TECHNICAL FIELD [0001] The present invention relates to a switching means driving circuit for driving switching means such as a transistor, a switching means driving method, a power supply device including the switching means driving circuit, and a switching circuit.

Background art

[0002] It is well known to use various switching means for controlling or switching the conduction Z cutoff state of current paths included in various circuits. Conventionally, for example, a transistor such as a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor) is used as a switching means, and the transistor is turned on and off to drive the transistor. A gate drive circuit that inputs a control signal to the gate was used.

By the way, in transistors such as MOSFET and IGBT, a capacitance component called a gate input capacitance is generated between the gate and the drain and between the gate and the source. For this reason, when a control signal is input to the transistor gate, the signal current of the control signal is consumed to charge the capacitance component, and the transistor may not be driven reliably. There is also a harmful effect called the feedback effect (or mirror effect) between the drain and the gate. Therefore, it is necessary to input a sufficient signal current to the transistor gate. Therefore, in a conventional gate drive circuit, a control signal for controlling on / off of the transistor is amplified using an external power source supplied from an external circuit and then input to the gate of the transistor (for example, (See Patent Document 1.) o

[0004] Patent Document 1: Japanese Patent Application Laid-Open No. 2003-229749

[0005] The gate drive circuit described in Patent Document 1 amplifies the control signal using an external power source Vcc different from the control signal and inputs it to the gate of the MOSFET in order to turn on and off the MOSFET according to the control signal. To do. Disclosure of the invention

Problems to be solved by the invention

[0006] Thus, in the conventional switching means driving circuit, an external power supply is indispensable. Therefore, an object of the present invention is to provide a switching means driving circuit that does not require an external power supply. Another object of the present invention is to provide a driving method of the switching means that does not require an external power supply and that reliably and at high speed drives the switching means.

Means for solving the problem

[0007] To achieve the above object, a switching means driving circuit of the present invention comprises a switching means driving section for driving the switching means on and off, and a power supply section for driving the switching means driving section. The power supply unit includes a charging unit that charges an input signal inputted to the switching unit driving unit to drive the switching unit on and off, and the charging unit drives the switching unit driving unit. It is characterized by supplying power.

[0008] Further, in the switching means driving circuit of the present invention, the switching means is a first element having a first current path and a first control terminal for on-Z-off controlling the first current path. It may be configured.

[0009] In addition, the switching means driving circuit of the present invention amplifies the input signal of the switching means driving section, and applies a mark to the first control end of the switching means to turn on the switching means. First driving means for driving the switching means, and when the polarity of the input signal is inverted, the polarity-inverted input signal is amplified and applied to the first control terminal to drive the switching means off. It is good also as a structure which has 2 drive means

In addition, the switching means driving circuit of the present invention amplifies the input signal of the switching means driving section and applies the input signal to the first control end of the switching means. ON has first driving means for driving ON, and third driving means for driving OFF the switching means when the input signal is not applied It is good also as a structure.

Furthermore, in the switching means driving circuit of the present invention, when the first driving means drives the switching means on, the first control end and the first current path end of the switching means And when the second driving means drives the switching means off, the switching means is provided between the first control end and the first current path end. A configuration may be adopted in which a charge charged in an existing input capacitor is discharged and charged in a polarity opposite to the polarity of the charged charge.

[0012] Further, in the switching means driving circuit of the present invention, when the first driving means drives the switching means on, a first control end and a first current path end of the switching means When the third drive means turns off the switching means, the input capacity existing between the first control terminal and the first current path end of the switching means is present. A configuration may be adopted in which the charge charged in the input capacitor is discharged.

[0013] Further, in the switching means driving circuit of the present invention, the first driving means is a second element having a second current path and a second control terminal for controlling the second current path. The second driving unit or the third driving unit may be a third element having a third current path and a third control end for controlling the third current path.

[0014] A switching circuit of the present invention includes a switching means, a switching means driving section that drives at least the switching means on and off, and a power supply section that supplies electric power for driving the switching means driving section. A switching means drive circuit including a power supply section having a connection end for connecting a charging section for charging an input signal input to the switching means drive section for driving the switching means on and off. The switching means driving circuit is connected to a first control terminal of the switching means, and the switching means driving circuit and the switching means are formed on a single chip.

[0015] Further, in the switching circuit of the present invention, the switching means includes a first element having a first current path and a first control terminal for on-Z-off controlling the first current path. May be. [0016] Further, in the switching circuit of the present invention, the switching means driving section amplifies the input signal and applies the amplified signal to a first control terminal of the switching means to drive the switching means on. And a second drive for amplifying the polarity-inverted input signal and applying it to the first control terminal to drive the switching means off when the polarity of the input signal is inverted It is good also as a structure which has a means.

[0017] Further, in the switching circuit of the present invention, the switching means driving section amplifies the input signal and applies the amplified signal to the first control terminal of the switching means to drive the switching means on. It may be configured to include first driving means and third driving means for driving the switching means off when the input signal is not applied.

[0018] Further, in the switching circuit of the present invention, when the first driving unit drives the switching unit on, the switching unit includes a first control end and a first current path end. And the second driving means exists between the first control end and the first current path end of the switching means when the second driving means drives the switching means off. A configuration may be adopted in which the charge charged in the input capacitor is discharged and charged in the opposite polarity to the polarity of the charged charge.

[0019] Further, in the switching circuit of the present invention, when the first driving unit drives the switching unit on, the switching unit includes a first control end and a first current flow path end. When the third driving means turns off the switching means, the input capacity existing between them is charged, and between the first control end and the first current flow path end of the switching means. A configuration may be adopted in which the electric charge charged in the existing input capacitance is discharged.

[0020] Further, in the switching circuit of the present invention, the first driving means is a second element having a second current path and a second control terminal for controlling the second current path, The second driving means or the third driving means may be a third element having a third current path and a third control terminal for controlling the third current path.

[0021] The power supply device of the present invention is connected to the switching means driving circuit of the present invention described above, the switching means having a first control terminal connected to the switching means driving circuit, and the switching means. Energy depending on the switching operation of the switching means And a transformer or an inductor for transmitting, storing, or discharging.

[0022] The switching means driving method of the present invention includes a switching means having a first control terminal, a switching means driving section for driving the switching means on and off, and a power supply section for driving the switching means driving section. In the switching circuit driving method, the switching means driving method comprises: inputting an input signal to the switching means driving section; charging the input signal input to the switching means driving section to the power supply section; and Power is supplied to drive the switching means driving section, the input signal is amplified by the switching means driving section, and the amplified input signal is applied to the first control terminal of the switching means. and the switching means is driven to be turned on.

[0023] Further, the switching means driving method of the present invention includes a switching means having a first control end, a switching means driving section for driving the switching means on and off, and driving the switching means driving section. In the switching circuit provided with the power supply unit for switching, the input signal whose polarity is alternately inverted is input to the switching unit driving unit, and the input signal input to the switching unit driving unit, according to the switching unit driving method. The power supply unit is charged, power is supplied from the power supply unit, and the first drive unit and the second drive unit included in the switching unit drive unit are driven. The input signal of one polarity is amplified and applied to the first control terminal of the switching means to apply the switch signal to the switch. The switching means is driven on, the second driving means amplifies the input signal of the other polarity, and the amplified input signal of the other polarity is applied to the first control terminal of the switching means. The switching means is driven off.

The invention's effect

[0024] According to the switching means driving circuit of the present invention, the power supply section that drives the switching means driving section charges the input signal input to the switching means driving section in order to drive the switching means on and off. The charging unit supplies power for driving the switching means driving unit. Therefore, use a power supply outside the circuit. A low-cost drive circuit can be easily realized by a simple circuit configuration.

The power supply unit preferably includes a capacitor that is charged by the voltage of the input signal as the charging unit.

[0025] Here, the switching means includes, for example, a transistor (first element) such as FET, IGBT, etc., and includes one current path (first current path) through which the current between the drain and source of the transistor flows, And a gate (first control end) for on-off control of the road. There is an input capacitance between the gate (first control end) of the transistor and the source or drain (first current path end), and the follow-up performance of the transistor on / off operation with respect to the input signal due to the influence of the input capacitance. There is a problem of being better.

[0026] According to the switching means driving circuit of the present invention, when the switching means driving section includes the first driving means and the second driving means, the first driving means amplifies the input signal, The switching means is driven on by applying a force to the first control end of the switching means !, and the second drive means amplifies the input signal with the polarity inverted when the polarity of the input signal is inverted. Then, a printing force tl is applied to the first control end to drive the switching means off. Here, the input signal may be a deviation of an input signal whose polarity is alternately inverted, or an input signal having substantially only one polarity.

When an input signal having substantially only one polarity is input, the first driving means included in the switching means driving unit amplifies the input signal and applies a printing force to the first control terminal of the switching means. The third driving means provided in the switching means driving section drives the switching means off when no input signal is applied.

In a preferred embodiment, the first driving means includes, for example, an NPN bipolar transistor (second element), and a current path (second current path) through which the collector-emitter current of the NPN bipolar transistor flows. And a base (second control end) for controlling the current path. The second driving means includes, for example, a PNP-type bipolar transistor (third element), a current path (third current path) through which the emitter-collector current flows, and a base (first current path) for controlling the current path. 3 control ends). Therefore, the first driving means and the second driving means amplify the input signal. The third driving means includes, for example, a PNP-type bipolar transistor (third element), and a current path (third current path) through which the emitter-collector current flows, and a base for controlling the current path (third A third control end).

[0027] When input signals for on-drive and off-drive amplified by the switching means drive unit force are respectively input to the first control end of the switching means, the first drive means has the switching means. Charging the input capacitance existing between the first control end and the first current path end, and when the second drive means drives off the switching means, the first means of the switching means The charge charged in the input capacitor existing between the control end and the first current path end is discharged, and charged in the opposite polarity to the polarity of the charged charge. Therefore, the effect of the input capacitance of the switching means is not compensated and minimized, the first control terminal voltage of the switching means rises and falls sharply, and the switching means reliably follows the input signal at high speed. Can be operated.

[0028] When an on-drive input signal amplified by the switching means drive unit force is input to the first control end of the switching means, the first drive means is connected to the first control end of the switching means. Charge the input capacitance that exists between the end of the first current path. When the switching means driving unit force input signal is not applied to the first control end of the switching means, the third control means has the first control end of the switching means when the switching means is driven off. And the charge charged in the input capacitor existing between the first current path end is discharged. Therefore, the effect of the input capacitance of the switching means is compensated or minimized, and the rising and falling edges of the first control terminal voltage of the switching means are made steep so that the switching means reliably follows the input signal at high speed. It can be operated.

[0029] Further, since the switching means driving unit amplifies and outputs the input signal, the input signal input to the switching means driving circuit may be of normal strength before being input to the switching means driving circuit. It is also unnecessary to amplify the input signal in advance. Therefore, it is possible to reduce the cost including the peripheral circuit.

[0030] Further, since the first drive end of the switching means is driven strongly by the switching means drive section, the switching means drive circuit may be of high impedance. The margin of circuit layout design is also great.

[0031] The switching means driving circuit of the present invention includes at least a switching means driving section that drives the switching means on and off, and a power supply section that supplies electric power for driving the switching means driving section. When the switching means includes a power supply unit having a connection end for connecting a charging unit for charging an input signal input to the switching unit driving unit for on-Z off driving, the switching unit has the switching unit driving circuit. By connecting to the first control end, the switching means driving circuit and the switching means can be formed on a single chip. Therefore, for example, a switching circuit with a control terminal that has been made into a monolithic IC can be easily realized, and there is an advantage that a small and high-performance switching circuit can be manufactured at low cost. In addition, the user can incorporate and use the switching circuit of the present invention in a device such as a power supply device with the same feeling as when handling a transistor element such as a conventional FET or IGBT.

[0032] According to the power supply device of the present invention, since it is not necessary to use an external power supply for driving the switching means drive circuit, a low-cost power supply device as a whole can be easily realized with a simple circuit configuration.

Conventional power supply devices that use transistors such as FETs as switching means are often switched at a frequency of about 100 to 200 KHz. According to the power supply apparatus of the present invention, by incorporating the switching means driving circuit of the present invention, the influence of the input capacitance of the switching means is not compensated and minimized, and the rise of the first control terminal voltage of the switching means is achieved. Since the falling edge is steep and the switching means can operate reliably and at high speed following the input signal, it is also possible to perform switching operation at a frequency about 10 times that of the conventional system, that is, about 1 MHz. is there. Therefore, a highly efficient power supply apparatus with extremely small switching loss can be easily realized at low cost.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. Each of the following embodiments is an example in which a gate drive circuit is configured by using an FET having a gate as a drive end as a switching means, but these are merely examples, and the present invention is not limited to these. It is not limited to the embodiment of the present invention.

[0034] [First embodiment]

FIG. 1 is a circuit diagram showing a schematic configuration of a gate drive circuit 1 in a first embodiment to which the present invention is applied.

The gate drive circuit 1 shown in FIG. 1 includes NPN transistor TR11, PNP transistor TR 12, diodes Dl l, D12, D13, and a capacitor C11, and inputs a control signal to the gate of FET1. . The drain of FET1 is connected to the coil L11 on the primary side of the transformer T1, the source is grounded, and the operation is switched on and off according to the control signal input by the gate drive circuit 1.

FET 1 has a predetermined gate input capacitance between the gate source and between the gate and drain. The sum of the gate input capacitance between the gate and source and between the gate and drain is called the capacitance C below.

In the gate drive circuit 1, the control pulse 10 is input to the input terminal 11. As shown in the figure, this control pulse 10 is substantially a positive voltage only. A node N12 is arranged on the line connected to the input terminal 11, and the anode side terminal of the diode Dl1 is connected via the node N12. One end of a capacitor C11 is connected to the power sword side terminal of the diode Dl1 via a node Nil, and the other end of the capacitor C11 is grounded. Further, the collector of the transistor TR11 is connected to the node Nil. The diode D11 and the capacitor CI1 constitute a power supply unit that drives the transistor TR11.

[0036] The anode side terminal of the diode D12 is connected to the node N12, and the base of the transistor TR11 is connected to the force sword side terminal of the diode D12 via the node N13.

The emitter of transistor TR11 is connected to the gate of FET1 via node N15, and is further connected to the emitter of transistor TR12 via node N15.

The base of the transistor TR12 is connected to the input terminal 11 via the node N12, and the collector is grounded via the node N16.

[0037] Further, the power sword side terminal of the diode D13 is connected to the line connecting the base of the transistor TR12 and the input terminal 11 via the node N14. Anode of diode D 13 The side terminal is connected to node N13.

The operation of the gate drive circuit 1 configured as described above will be described.

When control pulse 10 is input to input terminal 11, when control pulse 10 is High, a forward voltage is applied to diode D12, and current flows from input terminal 11 to the base of transistor TR11 via diode D12. Flows. On the other hand, the forward voltage is also applied to the diode D11 by the control noise 10 input to the input terminal 11, and the control pulse 10 is input to the collector of the transistor TR11.

Thereby, in the transistor TR11, when the control pulse 10 is High, the base current and the collector current flow, and the transistor TR11 is turned on. In addition, since the base potential of the transistor TR12 is higher than that of the emitter, no current flows and the transistor TR12 is turned off. As a result, the potential of the emitter of transistor TR12 rises, so that a control signal based on control pulse 10 is input to the gate of FET1. Therefore, in FET1, the capacitor C is charged by the control signal input to the gate, and FET1 is turned on.

[0039] When the control pulse 10 is input to the input terminal 11 and the control pulse 10 is in the high state, a forward voltage is applied to the diode D11, whereby a current flows from the diode D11 to the capacitor C11, and the capacitor C11 Is charged. The charging voltage Veil of capacitor C11 is Vcll = Vpp-Vdllf, where Vpp is the voltage of positive control pulse 10 and Vdllf is the forward voltage drop of diode D11.

[0040] Note that when the control noise 10 is input to the input terminal 11, it is considered that the collector potential of the transistor TR11 is lower than the base potential due to the voltage drop (Vdllf) of the diode D11. It is conceivable that a current flows through the base force collector of transistor TR11. However, by inserting the diode D12 between the node N12 and the base of the transistor TR11 and dropping the voltage of the base of the transistor TR11 by the forward voltage of the diode 12, the current flows from the base of the transistor TR11 to the collector of the transistor TR11. Suppresses current.

[0041] On the other hand, when the control pulse 10 is input to the input terminal 11 and the control pulse 10 is in the high state, the transistor TR12 is in the off state because no current flows because the base potential is higher than the emitter. . [0042] Subsequently, when the control pulse 10 input to the input terminal 11 is switched from High to Low (0 volt), no current flows from the diode D12 to the base of the transistor TR11, and the transistor TR11 is switched off. As a result, no voltage is applied to the gate of FET1 in the emitter of transistor TR11.

On the other hand, in the transistor TR12, since the base potential is lower than the emitter, a current flows between the emitter base and the emitter collector, and the transistor TR12 is turned on. Here, since the collector of the transistor TR12 is grounded, the potential of the gate of the FET1 is lowered and the gate driving circuit 1 is turned off. Also, the charge stored in the capacitor C of FET1 is quickly discharged from the gate of FET1 via transistor TR12 and node N16. Since the base of the transistor TR12 is connected to the input terminal 11, the capacitor C whose potential is sufficiently low is surely discharged.

[0044] In the gate drive circuit 1, when the control pulse 10 is High, the base of the transistor TR11 is used as a current path for eliminating minority carriers accumulated between the base emitter and the base collector of the transistor TR11. Node N13, diode D13, node N14, and input terminal 11. In this path, when control pulse 10 is high, diode D13 is biased in the reverse direction, so control pulse 10 is not transmitted to the base of transistor TR11.

[0045] When the control pulse 10 is input to the input terminal 11 and goes from low to high, as described above, a forward voltage is applied to the diode D12, and the input terminal 11 passes through the diode D12 to the base of the transistor TR11. Control pulse 10 is input.

Here, since the transistor TR11 is turned on when the previous control pulse 10 is High, the charge charged in the capacitor C11 can be discharged. Due to the discharge of the capacitor C11, the collector current due to the discharge of the capacitor CI1 flows to the transistor TR11. Therefore, in the transistor TR11, the control pulse 10 input to the base is greatly amplified and input to the gate of FET1.

As a result, the amplified control pulse 10 for FET1 is input as a control signal, so that sufficient current is input to charge the capacitance C of FET1 at high speed, and the rise of the gate 1 applied voltage of FET1 is steep. To. As a result, FET1 turns on quickly. In other words, the rise of the drain current of FET1 becomes steep.

[0046] As described above, in the gate drive circuit 1, the capacitor C11 is charged by the control pulse 10, and the control pulse 10 input thereafter is amplified by the energy charged in the capacitor C11, and the FET1 Therefore, a control signal that can quickly charge the capacitor C, which is the gate input capacitor, is input to the gate of FET1. Also, the capacitor C is discharged quickly with the control pulse 10 turned off.

This compensates for or minimizes the effect of the gate input capacitance on FET1, and allows FET1 to be turned on and off at high speed. In particular, FET1 can be turned on according to the inherent turn-on time characteristics of FET1.

FIG. 2 is a waveform showing the operation of the conventional gate drive circuit, FIG. 3 is a waveform showing the operation of the gate drive circuit 1, and FIG. 4 is a case where an external power supply is applied to the gate drive circuit 1. It is a waveform showing the operation of. Each waveform in Figures 2 to 4 shows the FET gate voltage waveform.

[0048] For example, in the case of a power MOSFET, the specific capacity of the gate input capacity (capacitance C) is about several thousand picofarads. Therefore, when a control signal is input to the gate of the FET, it takes a considerable amount of time to charge the gate input capacitance of the FET, so the on-Zoff operation of the FET does not follow the control signal well.

For example, in the waveform shown in FIG. 2, the rise of the voltage is gradual, and so-called “rounding” occurs. This indicates that the control signal current has been consumed to charge the gate input capacitance of the FET.

On the other hand, when the gate drive circuit 1 (FIG. 1) in the first embodiment is applied, as shown in FIG. 3, the waveform of the voltage output from the FET 1 rises very well, and the FET 1 is good. Shows that it works. This is because the control pulse 10 was amplified by the discharge of the capacitor C11 and input to the gate of FET1. In other words, because sufficient current is input to the gate of FET1, even if part of the control signal is consumed to charge the capacitor C, FET1 is successfully turned on quickly.

Conventionally, in order to prevent the occurrence of “margin” as shown in FIG. 2, a control signal is amplified using an external power source and input to the gate of the FET. Therefore, in the gate drive circuit 1 Figure 4 shows an example where an external power supply Vcc is applied instead of the capacitor CI1. In the example in Fig. 4, the waveform rises very sharply because the control signal is sufficiently amplified by the external power supply. The waveform shown in FIG. 4 shows a sharper rise than the waveform shown in FIG. 3, but in practice, the effect of making a large difference is the same as shown in FIG.

As shown in FIGS. 2 to 4, the gate drive circuit 1 according to the first embodiment has the same effect as the gate drive circuit using the external power supply by the configuration without the external power supply. Very useful in terms.

FIGS. 5 to 7 show waveforms of the gate voltage of the FET in the switching power supply when the above gate drive circuit is mounted on the switching power supply, and FIG. 5 shows a conventional gate drive circuit. FIG. 6 shows an example using the gate drive circuit 1, and FIG. 7 shows an example using the gate drive circuit 1 with an external power supply added.

In the example shown in FIG. 5, the rising power S of the control signal input to the FET is lost as shown in FIG. 2, so that the switching power supply device is configured using a conventional gate drive circuit. Even if it is made, the switching power supply device in which the rise of the gate voltage of the FET is dull cannot obtain high frequency characteristics and is inferior in usefulness.

On the other hand, in the example shown in FIG. 6, the waveform of the gate voltage of FET1 rises satisfactorily by configuring the switching power supply device using the gate drive circuit 1 in the first embodiment. This indicates that FET1 is operating promptly according to the control signal. This switching power supply device has good high-frequency characteristics and is highly useful, such as being able to reduce the size of the transformer T1. Further, as will be described later with reference to FIG. 8, since the output is increased, it has superior usability.

In the example shown in FIG. 7, as described with reference to FIG. 4, the external power supply Vcc is used instead of the capacitor C11 of the gate drive circuit 1, and the control signal input to the FET 1 is sufficiently amplified. Yes. As a result, the gate voltage waveform of FET1 rises very sharply. Practically, the effect of making a large difference is the same as shown in Fig. 8 described later.

[0056] FIG. 8 is a chart showing the results of measuring the output of each switching power supply whose waveforms of the FET gate voltages are shown in FIGS. In FIG. 8, the conventional gate drive circuit is shown. The switching power supply using the circuit (Fig. 5) is called power supply A, the switching power supply using the gate drive circuit 1 (Fig. 6) is called power supply B, and the gate drive circuit 1 is supplied with an external power supply. This switching power supply (Fig. 7) is shown as power supply C.

In the results of FIG. 8, it is recognized that the power supply B has a significantly higher output than the power supply A. The output of power supply B is almost the same as that of power supply C.

That is, when the switching power supply device is configured using the gate drive circuit 1, a remarkable output improvement can be achieved without using an external power supply as in the case where the control signal to the FET is amplified using an external power supply.

[0058] As described above, according to the gate drive circuit 1 in the first embodiment, the control noise 10 which is not supplied with power from the circuit external force is sufficiently amplified and input to the gate of the FET1. Therefore, the influence of the gate input capacitance of FET1 can be compensated or minimized, and FET1 can be operated reliably. Thus, for example, when a switching power supply device is configured using the gate drive circuit 1, a power supply device that is highly useful can be provided.

It should be noted that the configuration and connection state of each circuit element in the first embodiment are merely examples, and can be appropriately changed without departing from the spirit of the present invention. For example, the connection state of the diode D13 is changed. It is also possible to change. Hereinafter, an example is shown as a second embodiment.

[0060] [Second Embodiment]

FIG. 9 is a circuit diagram showing a configuration of the gate drive circuit 2 according to the second embodiment to which the present invention is applied. In the gate drive circuit 2 shown in FIG. 9, the same components as those in the gate drive circuit 1 in the first embodiment are denoted by the same reference numerals and description thereof is omitted.

In the gate drive circuit 2 shown in FIG. 9, the diode D13 of the gate drive circuit 1 (FIG. 1) is omitted, and the node N13 and the node N14 are directly connected. Further, a diode D21 is provided on the line connecting the node N14 and the input terminal 11, and the anode side terminal of the diode D21 is connected to the node N14, and the force sword side terminal is connected to the input terminal 11 via the node N12. . Other configurations are the same as those of the gate drive circuit 1.

[0062] In the gate drive circuit 2, the base of the transistor TR12 is connected via the diode D21. Connected to input terminal 11. For this reason, when the control pulse 10 input to the input terminal 11 is switched from High to Low, the potential of the base of the transistor TR12 is lowered, so that the transistor TR12 is turned on, and the capacitance C of the FET1 is changed to the transistor TR12 and the node TR12. Discharged via the N16.

[0063] In the gate drive circuit 2, minority carriers accumulated between the base emitter and the base collector of the transistor TR1 1 when the control pulse 10 is High disappear when the control pulse 10 changes to Low. As a current path for this, there is a path from the transistor TR11 to the input terminal 11 via the diode D21. Since the diode D21 is reverse-biased when the control pulse 10 is high, the control pulse 10 is not transmitted to the base of the transistor TR11 through this path.

[0064] The operations of the gate drive circuit 2 other than those described above are the same as those of the gate drive circuit 1 in the first embodiment.

Therefore, in the gate drive circuit 2 in the second embodiment, as in the gate drive circuit 1 in the first embodiment, the capacitor C11 is charged by the control pulse 10, and the control input thereafter Pulse 10 is amplified by discharging the charge stored in capacitor C11 and input to FET1, so a control signal that can quickly charge the charge stored in capacitor C, which is the gate input capacitance, to the gate of FET1. Is entered. Capacitor C is quickly discharged when control pulse 10 is low. As a result, if the effect of the gate input capacitance in FET1 is compensated or minimized, and FET1 can be operated at high speed, a special effect can be obtained.

[0065] The configuration and connection state of each circuit element in the first and second embodiments are merely examples, and can be appropriately changed without departing from the spirit of the present invention. It is also possible to adopt a configuration in which the circuit elements are omitted. An example is shown below as the third embodiment.

[0066] [Third embodiment]

FIG. 10 is a circuit diagram showing a configuration of the gate drive circuit 3 in the third embodiment to which the present invention is applied. Note that in the gate drive circuit 3 shown in FIG. 10, each part configured similarly to the gate drive circuit 1 (FIG. 1) in the first embodiment is shown in the figure. The same reference numerals are given and description thereof is omitted.

The gate drive circuit 3 shown in FIG. 10 has a configuration in which the diodes D12 and D13 of the gate drive circuit 1 are omitted. Further, a diode D22 is provided instead of the diode D11 in the gate drive circuit 1. Similarly to the diode D11, the diode D22 has a node side terminal connected to the input terminal 11 via the node N12 and a force sword side terminal connected to the node Nil. The diode D22 has a smaller voltage drop (preferably 0.2 to 0.4 volts) than a general diode, and for example, a Schottky Noria diode is suitable.

Other configurations in the gate driving circuit 3 are the same as those in the gate driving circuit 1.

[0068] In the gate drive circuits 1 and 2 (Fig. 1 and Fig. 9), the control pulse 10 is input to the input terminal 11, and the voltage drop of the diode D11 causes the collector potential of the transistor TR11 to be lower than the base potential. In order to prevent current from flowing from the base to the collector of transistor TR11, a diode D12 was provided.

In the gate drive circuit 3, since the voltage drop of the diode D22 is small, even if the diode D12 is omitted, the above current wraparound can be prevented.

That is, the potential difference between the base and collector of the transistor TR11 is determined by the voltage drop between the base and collector of the transistor TR11 and the voltage drop of the diode D22. In the gate drive circuit 3, since the voltage drop of the diode D22 is small, the potential difference current between the base and collector of the transistor TR11 is suppressed to a level that does not occur. For this reason, omitting the diode D12 (Figs. 1 and 9) does not cause any operational problems.

[0069] Furthermore, in the gate drive circuit 3, by omitting the diode D12, the diode D13 in the gate drive circuit 1 or the diode corresponding to the diode D21 in the gate drive circuit 2 can be omitted. .

In the gate drive circuit 1, by providing the diode D12, the base of the transistor TR11 is connected via the diode D13 as a current path for eliminating minority carriers accumulated between the base emitter and the base collector of the transistor TR11. Connected to input terminal 11. In the gate driving circuit 2, the base of the transistor TR11 is connected to the input terminal 11 through the diode D21, whereby the minority key of the transistor TR11 is connected. A current path for extinguishing the rear was secured. For this reason, the gate drive circuits 1 and 2 require a unidirectional current element such as the diode D13 or the diode D21 so that current does not flow into the base of the transistor TR11 through the above path.

In the gate drive circuit 3, the above path is secured by connecting the base of the transistor TR11 and the base of the transistor TR12 via the node N12 by omitting the diode D12. For this reason, it is not necessary to dispose diodes corresponding to the diodes D13 and D21.

Thus, according to the gate drive circuit 3 in the third embodiment, the same effects as those of the gate drive circuits 1 and 2 in the first and second embodiments can be obtained, and more There is an advantage that it can be realized by a simple circuit configuration.

[0071] In the first to third embodiments, the specific configuration of the gate drive circuits 1, 2, and 3 is not particularly limited. For example, a normal transistor can be used instead of the FET 1, or the IGBT can be used. It is also possible to use a part of or all of the gate drive circuits 1, 2, and 3 with an equivalent circuit, and other details can be changed as appropriate. Of course.

[0072] For example, in the first to third embodiments described above, the transistors TR11 and TR12 have been described as bipolar transistors. The present invention is not limited to this. For example, an FET may be used. Here, the case where the transistors TR11 and TR12 are replaced with FETs in the gate drive circuit 1 described as the first embodiment will be described as a fourth embodiment.

[0073] [Fourth embodiment]

FIG. 11 is a circuit diagram showing a schematic configuration of the gate drive circuit 4 in the fourth embodiment to which the present invention is applied. As shown in FIG. 11, the gate drive circuit 4 is a circuit in which the transistors TR11 and TR12 in the gate drive circuit 1 shown in FIG. 1 are replaced with FETs 11 and 12, respectively.

The FET 11 is an N-channel FET. In the gate drive circuit 4, the drain of the FET 11 is connected to the capacitor CI 1 through the node Nl 1 and connected to the gate of the FET 1 through the source power N15 of the FETl 1. Connected, and the gate of FET11 is connected to the die via node N13. It is connected to the power sword side terminal of Aether Dl 2. The anode side terminal of the diode Dl 2 is connected to the input terminal 11 via the node N 12. The anode side terminal of the diode D11 is connected to the input terminal 11 via the node N12, and the force sword side terminal of the diode D11 is connected to the capacitor CI1 via the node Nl1.

FET 12 is a P-channel FET, and the gate of FET 12 is connected to input terminal 11 via node N 14, the source is connected to the gate of FET 1 via node N 15, and the drain is connected to node N 16. Is grounded. Further, the anode side terminal of the diode D13 is connected to the node N13, and the force sword side terminal is connected to the node N14.

[0074] In the gate drive circuit 4, as in the gate drive circuit 1, the FET 11 is turned on when the control pulse 10 input to the input terminal 11 is High, and the control pulse is based on the current generated by the discharge of the capacitor C11. While 10 is amplified, the gate potential of FET12 increases, so FET12 turns off. As a result, a voltage is applied to the gate of FET1. Also, when the control pulse 10 is low, the FET 11 is turned off and the FET 12 is turned on, and the charge accumulated in the capacitance C of the FET 1 is discharged through the FET 12 and the node N 16. Therefore, according to the gate drive circuit 4 shown in FIG. 11, the same effect as in the first embodiment can be obtained.

[0075] Further, in the second and third embodiments, it is possible to use FETs 11 and 12 instead of the transistors TR11 and TR12. In this case as well, the second and third embodiments can be used. The same effect as that of the embodiment can be obtained.

Note that the transistor driven by the gate drive circuit (FET 1 in FIGS. 1, 9, 10, and 11) is usually a power MOSFET. On the other hand, the FETs 11 and 12 in the gate drive circuit 4 in FIG. 11 do not need to be power MOSFETs, and those having a very small gate input capacity can be used as compared with FET1. For this reason, the influence on the operation of the gate drive circuit 4 by the gate input capacitance of the FETs 11 and 12 is negligible.

[0077] In the first to fourth embodiments described above, the control pulse 10 consisting essentially of a pulse of only the positive voltage is amplified and input to the FET 1 as a control signal, and the capacitance C of the FET 1 is increased at high speed. Input enough current to charge, steep rise of FET1 gate applied voltage. On the other hand, the electric charge charged in the capacitor C of FETl was quickly discharged from the gate of FET1 via transistor TR12 (FET12) and node N16 with a control pulse of 10 power ow. Here, if the charged capacity C of FET1 can be discharged more strongly when the control pulse 10 changes from High to Low, the fall of the FET1 gate applied voltage, in other words, the drain current of FET1 It is possible to make the fall of the steep.

[0078] Therefore, in addition to making the rise of the gate application voltage of FET1 steep, the fall of the gate application voltage of FET1 is made steep and FET1 is turned off at high speed according to the inherent turn-off time characteristics of FET1. For the purpose, examples in which the gate drive circuit is configured will be described as fifth to eighth embodiments.

[0079] [Fifth embodiment]

FIG. 12 is a circuit diagram showing a configuration of the gate drive circuit 5 in the fifth embodiment to which the present invention is applied. In the gate drive circuit 5 shown in FIG. 12, the same components as those in the gate drive circuit 1 in the first embodiment are denoted by the same reference numerals and description thereof is omitted.

The gate drive circuit 5 shown in FIG. 12 is configured by adding a diode D31 and a capacitor C31 to the gate drive circuit 1 (FIG. 1). That is, the node N31 is arranged on the line connecting the node N12 and the node N14, and the power sword side terminal of the diode D31 is connected. The collector of the transistor TR12 connected to the source of the FET1 through the node N16 in the gate drive circuit 1 is connected to the anode side terminal of the diode D31 through the node N32 in the gate drive circuit 5. Further, in the gate drive circuit 5, one end of the capacitor C31 is connected to the anode side terminal of the diode D31 and the collector of the transistor TR12 via the node N32, and the other end of the capacitor C31 is grounded. The diode D31 and the capacitor C31 constitute a power supply unit that drives the transistor TR12.

The diode D31 uses a diode having a smaller voltage drop (preferably 0.2 to 0.4 volt) than a general diode, such as a Schottky barrier diode, and the current between the base and collector of the transistor TR12 does not flow. It is preferable to do so, but it is not always necessary. Other configurations are the same as those of the gate drive circuit 1.

[0081] In the gate drive circuit 5, the force that the control pulse 20 is input to the input terminal 11 is different from the control pulse 10 that is input in the gate drive circuit 1, and the voltage polarity as shown in the figure. Are pulses that are alternately inverted.

[0082] In the gate drive circuit 5 configured as described above, when a control pulse 20 having a positive polarity is input to the input terminal 11, a forward voltage is applied to the diode D12, and the input terminal 11 power diode D12 Current flows to the base of the transistor TR11 via. On the other hand, a forward voltage is applied to the diode Dl 1 by a control pulse 20 having a positive polarity input to the input terminal 11, and the control pulse 20 is input to the collector of the transistor TR11. Thereby, in the transistor TR11, when the positive polarity control pulse 20 is input, the base current and the collector current flow, and the transistor TR11 is turned on.

[0083] On the other hand, when a control pulse 20 having a positive polarity is input to the input terminal 11, a reverse voltage is applied to the diode D31, so that a path from the input terminal 11 to the capacitor via the diode D31 is applied. No current flows. When control pulse 20 having a positive polarity is input to input terminal 11, transistor TR12 has a base potential higher than that of the emitter, similar to the operation when control pulse 10 in gate drive circuit 1 is High. Therefore, no current flows and the device is turned off.

As a result, the potential of the emitter of the transistor TR12 rises, so that a control signal having a positive polarity based on the control pulse 20 is input to the gate of the FET1. For this reason, in FET1, the capacitor C is charged by the positive polarity control signal input to the gate, and FET1 is turned on.

[0084] When a control pulse 20 having a positive polarity is input to the input terminal 11 and a forward voltage is applied to the diode Dl1, a current flows from the diode Dl1 to the capacitor CI1, and the capacitor C11 is charged. Is done. In addition, by inserting a diode D12 between the node N12 and the base of the transistor TR11 and dropping the voltage at the base of the transistor TR11 by the forward voltage of the diode D12, the current flowing from the base of the transistor TR11 to the collector of the transistor TR11 Is suppressed. These operations are the same as those when the control pulse 10 in the gate drive circuit 1 is High. Note that in the gate drive circuit 5 as well, minority carriers accumulated between the base emitter and the base collector of the transistor TR11 when the control pulse 20 having a positive polarity is input to the input terminal 11, As a current path to be extinguished when the polarity of the control pulse 20 turns negative, the base of the transistor TR11, the node N13, the diode D13, the node N14, and the input terminal 11 exist.

[0086] Subsequently, when the polarity of the control pulse 20 input to the input terminal 11 is reversed and the polarity is switched to a negative control pulse, a reverse voltage is applied to the diode D12, and the base of the transistor TR11 is applied from the diode D12. No current flows to transistor TR11, which turns off. As a result, no voltage is applied to the gate of FET1 in the emitter of transistor TR11.

On the other hand, in the transistor TR12, when the control pulse 20 having a negative polarity is input to the input terminal 11, the base potential becomes lower than the emitter, so that the transistor TR12 is turned on, and the emitter of the transistor TR12 is switched from the emitter to the collector. Current flows. Furthermore, the collector potential of transistor TR12 is pulled to a negative polarity due to the negative potential of control pulse 20 and the negative potential on node N32 side of capacitor C31, which will be described later, so the gate potential of FET1 is negative. Reduced to polarity. For this reason, FET1 is turned off sharply. In addition, the negative polarity control pulse 20 input to the input terminal 11 discharges the charge accumulated in the capacitor C of the FET 1 and re-sets the capacitor C to a polarity opposite to the polarity of the accumulated charge. Charge. For this reason, the current between the drain and source of FET1 is immediately cut off. In addition, as the charge stored in the capacitor C of FET1 has sufficient current to flow between the emitter and collector of the transistor TR12 as will be described later, it is ensured from the gate of FET1 via the transistor TR12, node N32, and capacitor C31. And it is discharged at high speed.

[0088] A forward voltage is applied to the diode D31 by the negative polarity control pulse 20 input to the input terminal 11, and a current flows from the capacitor C31 to the path of the diode D31 and the input terminal 11, Capacitor C31 is charged. At this time, the capacitor C31 is charged with a positive charge on the ground side and a negative charge on the node 32 side. The charging voltage Vc31 of capacitor C31 is Vc31 =-(| Vpn | -Vd31f), where Vpn is the voltage of control pulse 20 with negative polarity and V d31f is the forward voltage drop of diode D31. Capacitor C Looking at the potential at node N32 on node 31, the Vpn force is also a negative potential minus Vd31f.

Since the transistor TR12 is turned on when the polarity of the previous control pulse 20 is negative, the charge charged in the capacitor C31 can be discharged. Due to the discharge of the capacitor C31, a current flows between the emitter and the collector due to the discharge of the capacitor C31 through the transistor TR12. Therefore, in the transistor TR12, the control pulse 20 having a negative polarity input to the base is greatly amplified and input to the gate of the FET1.

As a result, a control pulse 20 having a negative polarity amplified with respect to FET1 is input as a control signal, so that a sufficient current flows to discharge the capacitance C of FET1 at high speed, and the gate application voltage of FET1 rises. Make the fall steep. As a result, FET1 turns off quickly. In other words, the fall of the drain current of FET1 becomes steep.

[0090] Further, when the polarity of the control pulse 20 input to the input terminal 11 is reversed and the negative force is positive, as described above, a forward voltage is applied to the diode D12, and the diode D12 is changed from the input terminal 11 to the diode D12. Then, the control pulse 20 having a positive polarity is input to the base of the transistor TR11.

Here, since the transistor TR11 is turned on when the polarity of the previous control pulse 20 is positive, the charge charged in the capacitor C11 can be discharged. Due to the discharge of the capacitor C11, a collector current due to the discharge of the capacitor C11 flows through the transistor TR11. Therefore, in the transistor TR11, the control pulse 20 having a positive polarity inputted to the base is greatly amplified and inputted to the gate of the FET1.

As a result, the control polarity 20 having the positive polarity is input to the FET 1 as a control signal, so that a current sufficient to charge the capacitance C of the FET 1 at high speed is input, and the FET 1 Steep rising of the gate applied voltage. As a result, FET1 turns on quickly. In other words, the rise of the drain current of FET1 becomes steep.

[0091] As described above, in the gate drive circuit 5, the capacitor C11 is charged by the control pulse 20 having the positive polarity, and the control pulse 20 having the positive polarity input thereafter is charged to the capacitor C11. Since it is amplified by energy and input to FET1, a control signal is input to the gate of FET1 that can quickly charge the capacitance C, which is the gate input capacitance. Capacitance C is quickly discharged with the control noise 20 in the negative polarity state. The Further, in the gate drive circuit 5, the capacitor C31 is charged by the control pulse 20 having a negative polarity, and the control pulse 20 having a negative polarity that is input thereafter is amplified by the energy charged in the capacitor C31 to be fed to the FET 1. Therefore, a control signal that can discharge the capacitor C quickly is input to the gate of FET1. Capacitor C is discharged quickly with control pulse 20 in the negative polarity.

Therefore, in the gate drive circuit 5 in the fifth embodiment, the influence of the gate input capacitance in the FET 1 can be compensated or minimized, and the FET 1 can be turned on and off at high speed. In particular, according to the characteristics of both the turn-on time and the turn-off time that FET1 originally has, a special effect that FET1 can be turned on and off is obtained.

The fifth embodiment configured by adding the diode D31 and the capacitor C31 to the gate drive circuit 1 in the first embodiment is also merely an example, and the gist of the present invention is as follows. Changes can be made as appropriate without departing from the scope. For example, an example in which the same change as the change in the fifth embodiment is added to the gate drive circuits 2 and 3 in the second and third embodiments is shown as the sixth and seventh embodiments. .

[0093] [Sixth embodiment]

FIG. 13 is a circuit diagram showing a configuration of the gate drive circuit 6 according to the sixth embodiment to which the present invention is applied. The gate drive circuit 6 shown in FIG. 13 has the same configuration as the gate drive circuit 1 (FIG. 1) in the first embodiment and the gate drive circuit 5 (FIG. 12) in the fifth embodiment. About each part, the same code | symbol is attached | subjected in a figure, and description is abbreviate | omitted.

In the gate drive circuit 6 shown in FIG. 13, the diode D13 of the gate drive circuit 5 (FIG. 12) is omitted, and the node N13 and the node N14 are directly connected. Further, a diode D21 is provided between the node N14 and the node N31, and the anode side terminal of the diode D21 is connected to the node N14, and the force sword side terminal is connected to the input terminal 11 and the power sword of the diode D31 via the node N31. It is connected. Other configurations are the same as those of the gate drive circuit 5.

[0095] In the gate drive circuit 6, the base of the transistor TR12 is connected via the diode D21. Connected to input terminal 11. For this reason, when the polarity of the control pulse 20 input to the input terminal 11 is reversed and the positive power is switched to negative, a forward voltage is applied to the diode D21 to make it conductive, and the potential of the base of the transistor TR12 is also made. When becomes lower than the emitter, transistor TR12 is turned on, and a current flows from the emitter of transistor TR12 to the collector. Furthermore, the collector potential of the transistor TR12 is pulled to a negative polarity due to the negative potential of the control pulse 20 and the negative potential on the node N32 side of the capacitor C31 described above. Be lowered. For this reason, FET1 is sharply turned off. In addition, the negative polarity control pulse 20 input to the input terminal 11 discharges the charge accumulated in the capacitor C of FET1 and recharges the capacitor C to a polarity opposite to the polarity of the accumulated charge. To do. For this reason, the current between the drain and source of FET1 is immediately cut off. Further, as already described in the description of the fifth embodiment, since a sufficient current flows between the emitter and collector of the transistor TR12, the charge accumulated in the capacitor C of the FET1 flows from the gate of the FET1 to the transistor TR12. It is discharged reliably and at high speed via node N32 and capacitor C31.

[0096] When a control pulse 20 having a negative polarity is input to the input terminal 11, the potential of the base of the transistor TR12 may be lower than the potential of the collector due to the voltage drop (Vd31f) of the diode D31. It can be considered that current flows through the base of the collector of transistor TR12. However, in the gate drive circuit 6, the diode D21 is inserted between the node N31 and the base of the transistor TR12, and the voltage at the base of the transistor TR12 is increased by the forward voltage of the diode D21. The current flowing from the collector of the transistor TR12 to the base of the transistor TR12 is suppressed.

In the gate drive circuit 6, the node N13 and the node N14 are directly connected. Therefore, when the polarity of the control pulse 20 is positive, minority carriers accumulated between the base emitter of the transistor TR11 and between the base and collector are eliminated when the polarity of the control pulse 20 turns negative. As a current path, there is a path from the base of the transistor TR11 to the input terminal 11 via the diode D21. This is the same as the gate drive circuit 2 in the second embodiment.

[0098] The operations of the gate drive circuit 6 other than those described above are described in the fifth embodiment. This is the same as the gate drive circuit 5 in FIG.

Therefore, in the gate drive circuit 6 in the sixth embodiment, the capacitor C11 is charged by the control pulse 20 having a positive polarity, and the control pulse 20 having a positive polarity input thereafter is connected to the capacitor CI 1 Because it is amplified by the energy charged to the FET1 and input to the FET1, a control signal that can quickly charge the capacitor C, which is the gate input capacitance, is input to the gate of the FET1. Capacitance C is discharged quickly with control pulse 20 in the negative polarity state. Further, in the gate drive circuit 6, the capacitor C31 is charged by the control pulse 20 having a negative polarity, and the control pulse 20 having a negative polarity inputted thereafter is amplified by the energy charged in the capacitor C31, and the FET1 Therefore, a control signal that can quickly discharge the capacitor C is input to the gate of FET1. In addition, the capacitor C is quickly discharged while the control pulse 20 has a negative polarity, and is charged with a reverse polarity. As a result, the influence of the gate input capacitance in FET1 is not compensated or minimized, and FET1 can be turned on and off at high speed. In particular, if FET1 can be turned on and off according to both the inherent turn-on time and turn-off time characteristics of FET1, a special effect can be obtained.

[0099] [Seventh embodiment]

FIG. 14 is a circuit diagram showing a configuration of the gate drive circuit 7 in the seventh embodiment to which the present invention is applied. Note that the gate drive circuit 7 shown in FIG. 14 is configured similarly to the gate drive circuit 1 (FIG. 1) in the first embodiment and the gate drive circuit 5 (FIG. 12) in the fifth embodiment. About each part, the same code | symbol is attached | subjected in a figure, and description is abbreviate | omitted.

[0100] The gate drive circuit 7 shown in Fig. 14 has a configuration in which the diodes D12 and D13 of the gate drive circuit 5 are omitted. Further, diodes D22 and D42 are provided in place of the diodes D11 and D31 in the gate drive circuit 5. The diodes D22 and D42 are diodes having a smaller voltage drop (preferably 0.2 to 0.4 volts) than a general diode, and for example, a Schottky barrier diode is suitable.

Other configurations in the gate drive circuit 7 are the same as those in the gate drive circuit 5.

[0101] In the gate drive circuit 6 (Fig. 13), the negative polarity control pulse 20 is applied to the input terminal 11. The diode D21 is provided to prevent the current from flowing from the collector of the transistor TR11 to the base due to the voltage drop of the diode D21 being caused to cause the base potential of the transistor TR11 to be lower than the collector potential.

In the gate drive circuit 7, since the voltage drop of the diode D42 is small, even if the diode D21 is omitted, the above current wraparound can be prevented.

That is, the potential difference between the base and collector of the transistor TR12 is determined by the voltage drop between the collector and base of the transistor TR11 and the voltage drop of the diode D42. In the gate drive circuit 7, since the voltage drop of the diode D42 is small, the potential difference current between the collector and base of the transistor TR12 is suppressed to a level that does not occur. Thus, omitting diode D21 (Figure 13) does not cause operational problems.

[0102] In the gate drive circuit 7, by omitting the diode D12, the base of the transistor TR11 and the base of the transistor TR12 are connected via the node N12 and the node N31, so that the base emitter of the transistor TR11 In the meantime, a current path for eliminating minority carriers accumulated between the base and the collector is secured. Therefore, it is not necessary to provide diodes corresponding to the diodes D13 and D21 (FIGS. 12 and 13) as in the gate drive circuit 3 (FIG. 10) in the third embodiment.

As described above, according to the gate drive circuit 7 in the seventh embodiment, the same effects as those of the gate drive circuits 5 and 6 in the fifth and sixth embodiments can be obtained, and more There is an advantage that it can be realized by a simple circuit configuration.

In the fifth to seventh embodiments, the transistors TR11 and TR12 have been described as bipolar transistors. However, the present invention is not limited to this. For example, FETs may be used. Here, the case where the transistors TR11 and TR12 are replaced with FETs in the gate drive circuit 6 (FIG. 13) described as the sixth embodiment will be described as an eighth embodiment.

[Eighth embodiment]

FIG. 15 is a circuit diagram showing a schematic configuration of the gate drive circuit 8 in the eighth embodiment to which the present invention is applied. As shown in FIG. 15, the gate drive circuit 8 replaces the transistors TR11 and TR12 in the gate drive circuit 6 shown in FIG. 13 with FETs 11 and 12, respectively. Circuit.

Note that FET 11 is an N-channel FET, and in the gate drive circuit 8, the drain of FE Tl 1 is connected to the capacitor CI 1 via the node Nl 1, and the source of the FET 11 is connected to the FET 1 via the node N15. It is connected to the gate, and the gate of FET11 is connected to the power sword side terminal of diode D12 via node N13.

In addition, FET12 is a P-channel type FET. The drain of FET12 is connected to capacitor C31 via node N32, the source is connected to the gate of FET1 via node N15, and the gate is connected to node N14. The other configuration of the gate drive circuit 8 connected to the anode side terminal of the diode D21 is the same as that of the gate drive circuit 6.

Note that the FETs 11 and 12 in the gate drive circuit 8 of FIG.

There is no need to be T. The gate input capacity is very small compared to FET1!

[0106] According to the gate drive circuit 8 shown in FIG. 15, the transistors TR11 and TR12 in the date drive circuit 6 (FIG. 13) of the sixth embodiment are replaced with the FETs 11 and 12, respectively. Since it has the same configuration as that of the sixth embodiment, the same effect as that of the sixth embodiment can be obtained. This is because the transistors TR11 and TR12 in the gate drive circuit 1 (FIG. 1) of the first embodiment are replaced with FETs 11 and 12, respectively, and the gate drive circuit 4 ( Since it is obvious in light of the operation description in Fig. 11), detailed description is omitted here.

In the fifth and seventh embodiments, the FETs 11 and 12 can be used instead of the transistors TR11 and TR12. In this case, the fifth and seventh embodiments are also used. It is a matter of course that the same effect as the form of can be obtained.

The configuration of the gate drive circuits 1 to 8 in the first to eighth embodiments can be modified so that the direction of current flow is reversed.

For example, in the gate drive circuits 1, 2, and 3 (FIGS. 1, 9, and 10), the transistor TR11 is described as an NPN bipolar transistor, and the transistor TR12 is described as a PNP bipolar transistor. Reverse the configuration of these transistors to make transistor TR11 A PNP bipolar transistor is used, and transistor TR12 is an NPN bipolar transistor. In addition, FET1 is a P-channel FET, and the drain and source are reversed. In addition, diodes Dll, D12, D13, and D21 are arranged so that the anode side terminal and the force sword side terminal are all reversed.

In the gate drive circuit configured in this way, by inputting a pulse of substantially only a negative voltage to the input terminal 11, FET1 is turned on when the negative pulse is on (Low), and the coil of the transformer T1 is turned on. A current flows through LI 1, and a current in the opposite direction to the gate drive circuits 1, 2, and 3 flows through each part of the circuit. In this case, the same effect as that of the gate drive circuits 1, 2, and 3 can be obtained only by reversing the direction of current flow.

[0110] For example, in the gate drive circuit 4 (Fig. 11), FET11 is an N-channel FET, and FET12 is a P-channel FET. Type FET, and FET12 is N-channel type FET. In addition, FET1 is a P-channel FET and the drain and source are reversed. In addition, the diodes Dll, D12, and D13 are arranged so that the anode side terminal and the force sword side terminal are all reversed.

In the gate drive circuit configured in this way, by inputting a pulse of substantially only a negative voltage to the input terminal 11, FET1 is turned on when the negative pulse is on (Low), and the coil of the transformer T1 is turned on. A current flows through LI 1, and a current in the opposite direction to the gate drive circuit 4 flows through each part of the circuit. In this case, the same effect as that of the gate drive circuit 4 can be obtained only by reversing the direction of current flow.

On the other hand, for example, in the gate drive circuits 5, 6, and 7 (FIGS. 12, 13, and 14), in addition to the change of the gate drive circuits 1, 2, and 3, the diodes D31 and D42 are What is necessary is just to arrange | position so that an anode side terminal and a force sword side terminal may be reversed.

[0112] For example, in the gate drive circuit 8 (Fig. 15), FET11 is an N-channel FET and FET12 is described as a P-channel FET. Type FET, and FET12 is N-channel type FET. In addition, FET1 is a P-channel FET. The diodes Dll, D12, D21, and D31 may be arranged so that the anode side terminal and the force sword side terminal are all reversed. As is clear from the description of the first to eighth embodiments described above, the switching means driving circuit of the present invention includes a diode except for a charging unit (usually a capacitor such as a capacitor) in the power supply unit. (pn junction diodes, Schottky barrier diodes), and transistors (FETs, neuropolar transistors) and other semiconductor elements, so combined with switching means (usually power MOSFETs) driven by a switching stage drive circuit It is also possible to form the switching circuit on a single substrate. That is, a switching means driving circuit having a connection end for connecting a charging section of the power supply section and the switching means are integrated on the same semiconductor substrate to form, for example, a monolithic IC. Then, a capacitor equivalent to the charging part can be externally attached to the monolithic IC switching circuit. This has the advantage that a small, high-performance switching circuit can be manufactured at low cost.

In the above switching circuit, an example in which a charging unit is externally attached to a monolithic IC switching circuit has been described. However, this is merely an example, and the present invention is not limited thereto. Of course, the entire switching means driving circuit including the switching means and the switching means may be integrated on the same semiconductor substrate to constitute the switching circuit.

[0114] As described above, the first to eighth embodiments described above show only examples when the present invention is applied, and various modifications can be made without departing from the spirit of the present invention. Needless to say, the description of the first to eighth embodiments does not limit the scope of the present invention.

Industrial applicability

[0115] The switching means driving circuit of the present invention is applicable to all circuits that operate various switching means such as FETs and devices equipped with such circuits. For example, a power supply circuit (for example, a switching power supply circuit) It can utilize suitably for etc.

Brief Description of Drawings

FIG. 1 is a circuit diagram showing a schematic configuration of a gate drive circuit 1 according to a first embodiment to which the present invention is applied.

FIG. 2 is a waveform showing the operation of a conventional gate drive circuit. 3 is a waveform showing the operation of the gate drive circuit 1 shown in FIG.

4 is a waveform chart showing the operation when an external power supply is applied to the gate drive circuit 1 shown in FIG.

[Fig. 5] This is the waveform of the FET gate voltage in a power supply using a conventional gate drive circuit.

6 is a waveform of the gate voltage of FET1 in the power supply device using the gate drive circuit 1 shown in FIG.

7 is a waveform of the gate voltage of FET1 in a power supply device using a gate drive circuit configured by adding an external power supply to the gate drive circuit 1 shown in FIG.

[Fig. 8] Fig. 5 to Fig. 7 are diagrams comparing the output of each power supply device showing the waveform of the FET gate voltage.

FIG. 9 is a circuit diagram showing a schematic configuration of a gate drive circuit 2 in a second embodiment to which the present invention is applied.

FIG. 10 is a circuit diagram showing a schematic configuration of a gate drive circuit 3 in a third embodiment to which the present invention is applied.

FIG. 11 is a circuit diagram showing a schematic configuration of a gate drive circuit 4 in a fourth embodiment to which the present invention is applied.

FIG. 12 is a circuit diagram showing a schematic configuration of a gate drive circuit 5 in a fifth embodiment to which the present invention is applied.

FIG. 13 is a circuit diagram showing a schematic configuration of a gate drive circuit 6 in a sixth embodiment to which the present invention is applied.

FIG. 14 is a circuit diagram showing a schematic configuration of a gate drive circuit 7 in a seventh embodiment to which the present invention is applied.

FIG. 15 is a circuit diagram showing a schematic configuration of a gate drive circuit 8 in an eighth embodiment to which the present invention is applied.

Explanation of symbols

1, 2, 3, 4, 5, 6, 7, 8 Gate drive circuit

10, 20 Control pulse Input terminal

Claims

The scope of the claims

[1] a switching means driving section for turning on and off the switching means;

A power supply unit for driving the switching means driving unit;

Comprising

The power supply unit includes a charging unit that charges an input signal input to the switching unit driving unit to drive the switching unit on and off, and the charging unit drives the switching unit driving unit. Supplying power,

A switching means driving circuit.

[2] The switching device according to [1], wherein the switching unit is a first element having a first current path and a first control terminal that performs on-Zoff control on the first current path. Switching means drive circuit.

[3] The switching means driving unit comprises:

A first driving means for amplifying the input signal and driving the switching means on by applying a printing force tl to a first control end of the switching means;

A second driving means for amplifying the input signal whose polarity has been reversed when the polarity of the input signal is reversed, and driving the switching means off by applying a printing force tl to the first control terminal; The switching means driving circuit according to claim 1 or 2, wherein:

[4] The switching means driving unit includes:

Third driving means for driving the switching means off when the input signal is not applied;

The switching means driving circuit according to claim 1 or 2, characterized by comprising:

[5] The first driving means, when turning on the switching means, charges the input capacitance existing between the first control end and the first current path end of the switching means, The second driving means, when driving the switching means off, charges stored in the input capacitance existing between the first control end and the first current path end of the switching means. Discharging and charging with a polarity opposite to the polarity of the charged charge The switching means driving circuit according to claim 3.

[6] The first driving means charges the input capacitance existing between the first control end and the first current path end of the switching means when the switching means is turned on. The third drive means, when driving the switching means off, charges stored in the input capacitance existing between the first control end and the first current path end of the switching means. 5. The switching means driving circuit according to claim 4, wherein the switching means driving circuit is discharged.

[7] The first driving means is a second element having a second current path and a second control end for controlling the second current path, and the second driving means or the third driving means. 7. The switching according to claim 3, wherein the driving means is a third element having a third current path and a third control terminal for controlling the third current path. Means driving circuit.

[8] switching means;

A switching means driving section for driving at least the switching means on and off, and a power supply section for supplying electric power for driving the switching means driving section, the switching means for driving on and off the switching means. A switching means driving circuit including a power supply section having a connection end for connecting a charging section for charging an input signal input to the means driving section;

With

The switching means driving circuit is connected to a first control end of the switching means, and the switching means driving circuit and the switching means are formed on a single chip;

A switching circuit characterized by

9. The switching device according to claim 8, wherein the switching means is a first element having a first current path and a first control terminal that performs on-Zoff control of the first current path. Switching circuit.

[10] The switching means driving unit includes:

When the polarity of the input signal is inverted, the input signal with the polarity inverted is amplified, 10. The switching circuit according to claim 8, further comprising: a second driving unit that drives the switching unit off by applying a printing force tl to the first control end.

[11] The switching means driving unit includes:

The switching circuit according to claim 8 or 9, characterized by comprising:

[12] The first driving means charges the input capacitance existing between the first control end and the first current path end of the switching means when the switching means is turned on. The second driving means, when driving the switching means off, charges stored in the input capacitance existing between the first control end and the first current path end of the switching means. 11. The switching circuit according to claim 10, wherein the switching circuit is discharged and charged with a polarity opposite to a polarity of the charged electric charge.

[13] The first driving means charges the input capacitance existing between the first control end and the first current path end of the switching means when the switching means is turned on. The third drive means, when driving the switching means off, charges stored in the input capacitance existing between the first control end and the first current path end of the switching means. 12. The switching circuit according to claim 11, wherein the switching circuit is discharged.

[14] The first driving means is a second element having a second current path and a second control end for controlling the second current path, and the second driving means or the third driving means. The switching means according to any one of claims 10 to 13, wherein the driving means is a third element having a third current path and a third control terminal for controlling the third current path. circuit.

[15] The switching means driving circuit according to any one of claims 1 to 7,

Switching means having a first control end connected to the switching means drive circuit;

A transformer or an inductor connected to the switching means for transmitting, storing or discharging energy according to a switching operation of the switching means; A power supply apparatus comprising:

[16] Driving the switching means in a switching circuit comprising a switching means having a first control end, a switching means driving section for driving the switching means on and off, and a power supply section for driving the switching means driving section. In the method

An input signal is input to the switching means driver,

The power supply unit is charged with the input signal input to the switching unit driving unit, the power source unit supplies power to drive the switching unit driving unit, and the switching unit driving unit amplifies the input signal. Applying the amplified input signal to the first control terminal of the switching means to drive the switching means on;

A driving method of the switching means characterized by the above.

[17] Driving of the switching means in the switching circuit comprising a switching means having a first control end, a switching means driving section for driving the switching means on and off, and a power supply section for driving the switching means driving section In the method

An input signal whose polarity is alternately inverted is input to the switching means driving section, the input signal input to the switching means driving section is charged to the power supply section, and the power supply section power is supplied to the switching means. Driving the first drive means and the second drive means of the drive unit;

The first driving means amplifies the input signal of one polarity, and applies the amplified input signal of one polarity to the first control terminal of the switching means to drive the switching means on. And

The input signal of the other polarity is amplified by the second driving means, and the amplified input signal of the other polarity is applied to the first control terminal of the switching means to drive the switching means off. To do,

A driving method of the switching means characterized by the above.