WO2006008689A1 - Bipolar transistor and method of manufacturing the same - Google Patents
Bipolar transistor and method of manufacturing the same Download PDFInfo
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- WO2006008689A1 WO2006008689A1 PCT/IB2005/052260 IB2005052260W WO2006008689A1 WO 2006008689 A1 WO2006008689 A1 WO 2006008689A1 IB 2005052260 W IB2005052260 W IB 2005052260W WO 2006008689 A1 WO2006008689 A1 WO 2006008689A1
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 46
- 238000000034 method Methods 0.000 claims description 15
- 229910052710 silicon Inorganic materials 0.000 claims description 15
- 239000010703 silicon Substances 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 12
- 125000004429 atom Chemical group 0.000 claims description 9
- 239000013078 crystal Substances 0.000 claims description 8
- 238000009792 diffusion process Methods 0.000 claims description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 5
- 229910052732 germanium Inorganic materials 0.000 claims description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 4
- 238000000407 epitaxy Methods 0.000 claims description 3
- 125000004432 carbon atom Chemical group C* 0.000 claims description 2
- 230000007423 decrease Effects 0.000 claims description 2
- 239000002019 doping agent Substances 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 6
- 230000005684 electric field Effects 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 239000002800 charge carrier Substances 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000002028 premature Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- -1 oxygen ions Chemical class 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/7317—Bipolar thin film transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1004—Base region of bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66265—Thin film bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
- H01L29/365—Planar doping, e.g. atomic-plane doping, delta-doping
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/735—Lateral transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the invention relates to a semiconductor device with a semiconductor body comprising a bipolar transistor having an emitter region, a base region and a collector region of, respectively, a first conductivity type, a second conductivity type opposite to the first conductivity type, and the first conductivity type, wherein, viewed in projection, the emitter region is situated above or below the base region, and the collector region laterally borders the base region.
- a semiconductor device with a semiconductor body comprising a bipolar transistor having an emitter region, a base region and a collector region of, respectively, a first conductivity type, a second conductivity type opposite to the first conductivity type, and the first conductivity type, wherein, viewed in projection, the emitter region is situated above or below the base region, and the collector region laterally borders the base region.
- Such a device is particularly suitable for high-frequency applications, because the collector-substrate capacitance and the base-collector capacitance are comparatively small.
- the invention also relates to a method of manufacturing such a device
- the emitter region may be situated, in a corresponding manner, below the base region.
- the collector region is situated in all cases next to, not below or above, the base region.
- a drawback of the known device is that it is less suitable for certain applications. Particularly if it is used as a power transistor, it exhibits shortcomings. The size of the voltage range over which the transistor can be used and the robustness of said transistor with respect to short-lived, high voltage peaks are comparatively small. As a result, the use of said transistor is limited. Therefore, it is an object of the present invention to provide a device which is suited for said applications, and which can be used over a large voltage range and exhibits a good resistance to short-lived, high voltage peaks.
- a device of the type mentioned in the opening paragraph is characterized in accordance with the invention in that the base region contains a highly doped sub-region the doping concentration of which has a delta-shaped profile in the thickness direction, and said highly doped sub-region extends laterally as far as the collector region.
- the invention is based first of all on the recognition that said drawbacks are caused by excessively high currents and/or premature breakdown between the base and the collector.
- the invention is further based on the recognition that in the known transistor these phenomena are connected with the occurrence of avalanche multiplication of charge carriers, which in turn is caused by a high electric field strength at the location of the collector-base junction. Said high electrical field strength in turn is caused by a high doping concentration present in the base.
- said doping concentration must be high in order to counteract punch-through.
- the invention is further based on the recognition that a highly doped, delta region does not have the above-mentioned drawbacks.
- the doping concentration in the base (sub-)region can be sufficiently high to preclude punch-through, on the other hand, the occurrence of a high field strength is precluded by the fact that such a delta-shaped profile has a small width.
- the avalanche multiplication of charge carriers depends not only on the height of the maximum field strength but also on the spatial distribution of the electric field. Both factors result in that the maximum electric field near the base-collector junction in a device in accordance with the invention is reduced with respect to a more conventional (lateral) bipolar transistor.
- the thickness of the base region is several tens ofnanometers.
- the doping concentration of the sub-region ranges between 10 19 and approximately 10 20 at/cm 3
- the thickness of the sub-region ranges between 1 and 15 nm, preferably between 1 and 10 nm.
- the base region contains a mixed crystal of silicon and germanium.
- the base region contains a mixed crystal of silicon and germanium.
- the sub-region is provided with atoms which decelerate the diffusion of the doping atoms of the sub-region.
- the doping used comprises boron (atoms).
- the transistor is of the npn type, which is the fastest type.
- Atoms that proved suitable for decelerating the diffusion of boron atoms in the sub-region are carbon atoms.
- a concentration that proved to be suitable does not exceed the silicon or the silicon-germanium mixed crystal by more than one or a few atom percent.
- SRB Strain Relaxed Buffer layer
- Such a device may also advantageously comprise a strained silicon layer as the top layer.
- C Bipolar MOS
- IC Integrated Circuit
- Another factor that plays a role in this respect is that the masks necessary for the manufacture fit in well with the technology customarily used for said manufacture. The fact that only a limited number of masks/masking steps are necessary is an important advantage in this connection.
- the semiconductor body is preferably separated from the semiconductor substrate by an electrically insulating layer.
- the collector region preferably is in an oblique position with respect to the surface of the semiconductor body, such that the distance from the collector region to the emitter region, viewed in projection, decreases in the thickness direction.
- a large part of the injection current (of electrons) will flow from the emitter to the base in the thickness direction, while a small part will flow sideways to the collector.
- the lateral Gummel number will generally be (much) higher, however.
- the (electron) current diffuses across the base. This diffusion current may flow in the thickness direction as well as in the lateral direction.
- the collector region is formed by means of ion implantation.
- This technique is excellently suited for placing a formed semiconductor region in an oblique position, because the implantation can be carried out at an angle with respect to the surface.
- ion implantation is a very suitable technique for forming the collector region resides in the fact that, in the device in accordance with the invention, the collector region borders on the surface.
- a method of manufacturing a semiconductor device with a semiconductor body which is provided with a bipolar transistor with an emitter region, a base region and a collector region of, respectively, a first conductivity type, a second conductivity type opposite to the first conductivity type, and the first conductivity type, wherein, viewed in projection, the emitter region is formed above or below the base region, and the collector region is formed so as to border laterally on the base region, is characterized in accordance with the invention in that a highly doped sub-region is formed in the base region, the doping concentration of said highly doped sub-region being provided with a delta-shaped profile in the thickness direction, and said highly-doped sub-region being formed so as to extend laterally as far as the collector region.
- a device in accordance with the invention is thus obtained in a simple manner.
- the base region is formed by means of epitaxy.
- This technique can very suitably be used to form particularly narrow, delta-shaped doping profiles in a formed semiconductor region.
- the formation of a mixed crystal, for example of silicon and germanium, can be readily carried out in this way.
- Fig. 1 is a diagrammatic cross-sectional view, at right angles to the thickness direction, of an embodiment of a semiconductor device in accordance with the invention
- Fig. 2 shows the normalized, maximum electric field strength (E p ) of the bipolar transistor of the device shown in Fig. 1, as a function of the thickness (d) of the sub-region of the base region,
- Fig. 3 shows the current density (J) of the bipolar transistor of the device of Fig. 1, as a function of the base-emitter voltage (Vbe),
- Fig. 4 shows the cut-off frequency (fT) of the bipolar transistor of the device of Fig. 1, as a function of the base-emitter voltage (Vbe), and
- Fig. 5 is a diagrammatic cross-sectional view, at right angles to the thickness direction, of the device of Fig. 1 in a stage of the manufacturing process by means of an embodiment of a method in accordance with the invention.
- FIG. 1 is a diagrammatic cross-sectional view, at right angles to the thickness direction, of an embodiment of a semiconductor device in accordance with the invention.
- a device 10 shown in this example comprises (see Fig. 1) a substrate 11, in this case a p-type silicon substrate covered with an insulating layer 5, in this case of silicon dioxide.
- a semiconductor layer structure comprising a first semiconductor layer 4, here of SiGe, which is n-type doped and composed of various sub- layers which will be discussed hereinafter.
- a second semiconductor layer 2 which is lightly p-type doped and composed, in this case, of three sub-layers 2A, 2B, 2C.
- the first sub-layer 2A constitutes, in this case, a sub- region 2A of the base region 2 and is delta-shaped. This means that the doping concentration is very high, here approximately 10 20 at/cm 3 , and the thickness is very small, here approximately 2 nm.
- the first two sub-layers 2A, 2B contain an SiGe mixed crystal with a Ge content of approximately 20 at.%. In addition, approximately 1 at.% C is added to the first sub- layer 2A, causing the diffusion of the, in this case boron, atoms in the base sub-region 2A to be limited.
- the third sub- layer 2C contains silicon, and an emitter region 1 is locally formed therein.
- the silicon layer 2C is strained, which can be used to advantage during the formation, in said silicon layer, of the channel region of a MOS transistor, such as in the case of a Bi(C)MOS IC. Such a MOST is not shown in the drawing.
- the base sub-region 2A is connected, on one side, to a highly doped, in this case p-type, base connection region 20 which is recessed in the surface of the semiconductor body 12.
- the base sub-region 2 A is connected to a collector region 3, in this case of the n-conductivity type, which is highly doped and recessed in the surface of the semiconductor body 12.
- the emitter region 3 of the (semi-)lateral transistor is, in this case, obliquely positioned with respect to the surface of the semiconductor body 12.
- Fig. 2 shows the normalized, maximum electric field strength (E p ) of the bipolar transistor of the device of Fig. 1, as a function of the thickness (d) of the sub-region of the base region.
- Curve 21 illustrates the effect of a thin, delta-shaped, highly doped base sub-region 2 A in a device 10 in accordance with the invention comprising a lateral bipolar transistor.
- E p is substantially reduced.
- This maximum field strength E p is normalized to a field strength belonging to a thickness d of approximately 15. E p thus represents the reduction of the maximum field strength by a measure according to the invention.
- the maximum field strength E p is approximately 30% lower, which is a substantial reduction.
- Fig. 3 shows the current density (J) of the bipolar transistor of the device shown in Fig. 1, as a function of the base-emitter voltage (Vbe), and Fig. 4 shows the cut-off frequency (fT) of the bipolar transistor of the device of Fig. 1, as a function of the base- emitter voltage (Vbe).
- Curve 51 of Fig. 3 corresponds to the collector current Ic
- curve 52 corresponds to the base current Ib, while the collector-base voltage is zero.
- This so-termed Gummel plot shows that the bipolar transistor has substantially ideal properties.
- curve 40 of Fig. 4 shows that, in principle, the device operates well. Further optimization to obtain the best parameters is possible, of course.
- Fig. 5 is a diagrammatic cross-sectional view, at right angles to the thickness direction, of the device of Fig. 1 in a stage of the manufacturing process by means of an embodiment of a method in accordance with the invention.
- an insulating layer 5 on which a monocrystalline semiconductor layer structure 4, 2, as discussed in part hereinabove, is provided.
- a second sub- layer 42 contains the same mixed crystal ' but, in this case, approximately 1 at.% C has been added, and said second sub- layer has a thickness of approximately 5 nm.
- a third sub- layer 43 which also contains the same mixed crystal and which has a thickness of 70 nm.
- the fourth sub ⁇ layer 44 contains SiGe with a Ge content of approximately 20 at.%, and has a thickness, in this case, of approximately 30 nm.
- the part 2 of the semiconductor layer structure, formed above said fourth sub ⁇ layer, has already been described hereinabove and is used for the formation of the heterojunction bipolar transistor of this example and for the formation of a MOS transistor, if necessary, as in the case of a Bi(C)MOS IC.
- the use of epitaxy when forming, in particular, the base sub-region 2A enables the latter to the readily provided with the desired delta-shaped doping profile.
- a doping gas such as diborane, is added to the gas mixture used to epitaxially deposit the layers. This enables the desirable, very thin, highly doped layer 2A to be readily formed at a low growth rate, a low pressure and a high gas rate.
- the buried insulating layer 5 can be formed by means of an ion implantation of oxygen ions.
- Above said layer there is a thin monocrystalline silicon layer, not shown in the Figure, which can be used as a nucleation layer for the growth process of the layers 2, 4.
- the structure of Fig. 5 is obtained using a so-termed substrate-transfer technique.
- the layers 2, 4 are grown on a silicon substrate, after which, subsequent to the provision of the layer structure onto an auxiliary plate, the substrate is removed by means of polishing and/or etch techniques. Instead of the removed substrate, a silicon substrate provided with a thermal oxide layer is then provided, after which the auxiliary plate is removed again.
- CMOS complementary metal-oxide-semiconductor
- manufacture of the bipolar transistor and, if necessary, a MOST can be carried out using customary CMOS technology. This can be done, for example, as described in detail in the above-mentioned United States patent specification US 6,384,469.
- the device of this example is only diagrammatically shown in Fig. 1.
- the device 10 does not have to be a planar device.
- a connection region of the emitter region 3, whether or not provided with spacers, may project above the surface of the semiconductor body 12.
- STI Shallow Trench Isolation
- the invention is not limited to the examples given hereinabove, and, within the scope of the invention, many variations and modifications are possible to those skilled in the art.
- a BiCMOS Bipolar Complementary Metal Oxide Semiconductor
- IC Integrated Circuit
- the invention can also be applied to a pnp transistor.
- the highly doped part of the emitter region may also be formed by means of out-diffusion from in-situ doped poly crystalline silicon, or by means of gas-phase doping, or by means of a monocrystalline, local deposition of highly doped silicon.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007520947A JP5090163B2 (en) | 2004-07-15 | 2005-07-07 | Bipolar transistor and manufacturing method thereof |
DE602005007904T DE602005007904D1 (en) | 2004-07-15 | 2005-07-07 | BIPOLAR TRANSISTOR AND MANUFACTURING METHOD THEREFOR |
US11/632,614 US7671447B2 (en) | 2004-07-15 | 2005-07-07 | Bipolar transistor and method of manufacturing the same |
EP05759723A EP1771887B1 (en) | 2004-07-15 | 2005-07-07 | Bipolar transistor and method of manufacturing the same |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP04103382.0 | 2004-07-15 | ||
EP04103382 | 2004-07-15 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2006008689A1 true WO2006008689A1 (en) | 2006-01-26 |
Family
ID=34972814
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IB2005/052260 WO2006008689A1 (en) | 2004-07-15 | 2005-07-07 | Bipolar transistor and method of manufacturing the same |
Country Status (7)
Country | Link |
---|---|
US (1) | US7671447B2 (en) |
EP (1) | EP1771887B1 (en) |
JP (1) | JP5090163B2 (en) |
AT (1) | ATE400063T1 (en) |
DE (1) | DE602005007904D1 (en) |
TW (1) | TW200620652A (en) |
WO (1) | WO2006008689A1 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8669640B2 (en) * | 2009-07-14 | 2014-03-11 | Freescale Semiconductor, Inc. | Bipolar transistor |
US9059195B2 (en) | 2013-05-29 | 2015-06-16 | International Business Machines Corporation | Lateral bipolar transistors having partially-depleted intrinsic base |
US9496184B2 (en) | 2014-04-04 | 2016-11-15 | International Business Machines Corporation | III-V, SiGe, or Ge base lateral bipolar transistor and CMOS hybrid technology |
US11245639B2 (en) | 2014-09-03 | 2022-02-08 | International Business Machines Corporation | Composition of persistent object instances linking resources across multiple, disparate systems |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01241156A (en) * | 1988-03-23 | 1989-09-26 | Hitachi Ltd | Semiconductor device |
US6384469B1 (en) * | 1998-04-22 | 2002-05-07 | France Telecom | Vertical bipolar transistor, in particular with an SiGe heterojunction base, and fabrication process |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5198692A (en) * | 1989-01-09 | 1993-03-30 | Kabushiki Kaisha Toshiba | Semiconductor device including bipolar transistor with step impurity profile having low and high concentration emitter regions |
EP0441635B1 (en) * | 1990-02-09 | 1995-05-24 | Canon Kabushiki Kaisha | Ink jet recording system |
JPH0499328A (en) * | 1990-08-18 | 1992-03-31 | Nec Corp | Bipolar transistor |
JPH05166825A (en) * | 1991-12-17 | 1993-07-02 | Hitachi Ltd | Semiconductor device |
JP3233690B2 (en) * | 1992-07-16 | 2001-11-26 | ローム株式会社 | Manufacturing method of bipolar transistor |
JPH06252158A (en) * | 1993-02-26 | 1994-09-09 | Toshiba Corp | Semiconductor device |
JP3708881B2 (en) * | 2001-01-31 | 2005-10-19 | 松下電器産業株式会社 | Semiconductor crystal film, manufacturing method thereof, semiconductor device and manufacturing method thereof |
JP2002270815A (en) * | 2001-03-14 | 2002-09-20 | Hitachi Ltd | Semiconductor device and driver circuit constituted of the semiconductor device |
DE10160509A1 (en) * | 2001-11-30 | 2003-06-12 | Ihp Gmbh | Semiconductor device and method for its manufacture |
JP3565274B2 (en) * | 2002-02-25 | 2004-09-15 | 住友電気工業株式会社 | Bipolar transistor |
JP3719998B2 (en) * | 2002-04-01 | 2005-11-24 | 松下電器産業株式会社 | Manufacturing method of semiconductor device |
-
2005
- 2005-07-07 US US11/632,614 patent/US7671447B2/en active Active
- 2005-07-07 DE DE602005007904T patent/DE602005007904D1/en active Active
- 2005-07-07 AT AT05759723T patent/ATE400063T1/en not_active IP Right Cessation
- 2005-07-07 EP EP05759723A patent/EP1771887B1/en active Active
- 2005-07-07 WO PCT/IB2005/052260 patent/WO2006008689A1/en active IP Right Grant
- 2005-07-07 JP JP2007520947A patent/JP5090163B2/en not_active Expired - Fee Related
- 2005-07-12 TW TW094123615A patent/TW200620652A/en unknown
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01241156A (en) * | 1988-03-23 | 1989-09-26 | Hitachi Ltd | Semiconductor device |
US6384469B1 (en) * | 1998-04-22 | 2002-05-07 | France Telecom | Vertical bipolar transistor, in particular with an SiGe heterojunction base, and fabrication process |
Non-Patent Citations (6)
Title |
---|
CHAN M ET AL: "A high performance lateral bipolar transistor from a SOI CMOS process", SOI CONFERENCE, 1995. PROCEEDINGS., 1995 IEEE INTERNATIONAL TUCSON, AZ, USA 3-5 OCT. 1995, NEW YORK, NY, USA,IEEE, US, 3 October 1995 (1995-10-03), pages 90 - 91, XP010196577, ISBN: 0-7803-2547-8 * |
JIN CAI ET AL: "Vertical sige-base bipolar transistors on cmos-compatible soi substrate", PROCEEDINGS OF THE 2003 BIPOLAR/BICMOS CIRCUITS AND TECHNOLOGY MEETING. ( BCTM ). TOULOUSE, FRANCE, SEPT. 28 - 30, 2003, IEEE BIPOLAR/BICMOS CIRCUITS AND TECHNOLOGY MEETING, NEW YORK, NY : IEEE, US, 28 September 2003 (2003-09-28), pages 215 - 218, XP010688512, ISBN: 0-7803-7800-8 * |
KRÜGER D ET AL: "Ultrashallow secondary ion mass spectroscopy depth profiling of doping spikes and Si/SiGe/Si heterostructures using different primary species", JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B: MICROELECTRONICS PROCESSING AND PHENOMENA, AMERICAN VACUUM SOCIETY, NEW YORK, NY, US, vol. 16, no. 1, January 1998 (1998-01-01), pages 292 - 297, XP012006613, ISSN: 0734-211X * |
PATENT ABSTRACTS OF JAPAN vol. 013, no. 574 (E - 863) 19 December 1989 (1989-12-19) * |
SAWANO K ET AL: "Surface smoothing of SiGe strain-relaxed buffer layers by chemical mechanical polishing", MATERIALS SCIENCE AND ENGINEERING B, ELSEVIER SEQUOIA, LAUSANNE, CH, vol. 89, no. 1-3, 14 February 2002 (2002-02-14), pages 406 - 409, XP004334441, ISSN: 0921-5107 * |
TOMINARI T ET AL: "Study on extremely thin base SiGe:C hbts featuring sub 5-ps ecl gate delay", PROCEEDINGS OF THE 2003 BIPOLAR/BICMOS CIRCUITS AND TECHNOLOGY MEETING. ( BCTM ). TOULOUSE, FRANCE, SEPT. 28 - 30, 2003, IEEE BIPOLAR/BICMOS CIRCUITS AND TECHNOLOGY MEETING, NEW YORK, NY : IEEE, US, 28 September 2003 (2003-09-28), pages 107 - 110, XP010687683, ISBN: 0-7803-7800-8 * |
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DE602005007904D1 (en) | 2008-08-14 |
TW200620652A (en) | 2006-06-16 |
EP1771887A1 (en) | 2007-04-11 |
JP5090163B2 (en) | 2012-12-05 |
JP2008507125A (en) | 2008-03-06 |
EP1771887B1 (en) | 2008-07-02 |
US20080083968A1 (en) | 2008-04-10 |
US7671447B2 (en) | 2010-03-02 |
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