WO2006003023A2

WO2006003023A2 - Method and arrangement for detecting unidirectional errors with systematic unordered codes

Info

Publication number: WO2006003023A2
Application number: PCT/EP2005/007430
Authority: WO
Inventors: Steffen Tarnick
Original assignee: 4Tech Gesellschaft Für Technologie Und Know-How-Transfer Mbh
Priority date: 2004-07-06
Filing date: 2005-07-06
Publication date: 2006-01-12
Also published as: EP1766787A2; DE102004033584A1; WO2006003023A3

Abstract

The invention relates to a method and an arrangement for the detection of unidirectional errors in words of systematic unordered codes. These codes are Bose-AUED codes and Biswas-Sengupta-AUED codes. The error detection method consists in translating the code words into words of a Berger-type code which are then checked by using a method for the corresponding Berger-type code. The inventive error detection arrangement which comprises a translation circuit and a Berger-type code checker can be tested with a very low number of code words. It has the characteristic of being self-testing almost independently of the amount of code words provided and is therefore extremely suitable as embedded checker. Said checker has two outputs emitting a two-rail-signal or one output carrying a periodic signal. Moreover, this checker is not code-splitting in the conventional sense, but yet capable of detecting all unidirectional errors.

Description

Method and arrangement for error detection with systematic disordered codes

description

The invention relates to a method for detecting unidirectional errors in words x of a systematic disordered code C and an arrangement for implementing this method. The goal is to detect signal bit errors caused by faulty circuitry as they occur, with the outputs of the circuit being words of code C. The method and arrangement are therefore well suited for the online test.

The online test is often implemented using self-checking circuits with coded outputs and self-testing code checkers that monitor the outputs of the circuits under test. The ability of a checker to be self-testing guarantees that it can signal its own circuit faults in the same way as bit errors produced by the supervised circuit. A circuit is called self-testing for a set of skip errors if for each error from that set there exists an input codeword for which the circuit generates a non-codeword output in the presence of the error. The ability to detect bit errors that transform codewords generated by the monitored circuit into non-codewords is achieved by the property of the checker to be code-separating. A circuit is called code-separating when it maps (input) codewords to (output) codewords and non-codewords to non-codewords.

However, the ability of a Checker to be code-divisive is not always required (JE Smith, "The Design of Totally Self-Checking Check Circuits for a Class of Unordered Codes" Journal of Design Automation & Fault-Tolerant Computing, Vol. 2 , October 1977, pp. 321-342). The main task of a checker is not primarily to distinguish codewords from non-codewords, but to detect errors, in this case unidirectional errors. The ability to distinguish codewords from non-codewords is a sufficient but not necessary condition for detecting errors. It will be shown that the checkers described herein are capable of detecting all unidirectional errors, even in the case that they are not code-separating in the usual sense. Certain non-codewords would be signaled as codewords. However, no unidirectional error is able to change a codeword to one of these non-codewords. The definition of the code separation is extended as follows:

Let E be a class of bit errors. A circuit is code-separating with respect to E if it is code-separating the word set, which consists of all codewords and all those non-codewords that can be generated by the modification of codewords with errors from E. (A similar definition is These are not self-testing with respect to all circuit errors, but with respect to a certain class of errors.If this restriction is omitted, it is usually assumed that this class is the set of all simple sticking errors, which also applies to the checkers considered here Is accepted.)

The checkers discussed here are code-separating with respect to all unidirectional errors. They are suitable for use in systems where no other type of bit error is expected or even can not emerge as a result of simple trapping errors (see, eg, FY Busaba and PK Lala, "Self-Checking Combinational Circuit Design for Single and Unidirectional Multibit Error." Journal of Electronic Testing, Vol. 5, No. 1, February 1994, pp. 19-28).

The ability of a checker to self-test depends not only on its architecture, but also on the amount of codewords the checker receives from the circuit to be monitored. If some code words are not generated by the circuit then some checker errors could not be tested. If such errors are not detected, then the checker loses the property of being code-separating. Since such checkers are not considered as isolated circuits that theoretically receive all codewords, but are embedded in a system in which the amount of codewords they receive depends on the particular environment of the checker, such checkers are called embedded checkers. There are a variety of methods in the literature for designing embedded checkers. These are essentially based on the addition of hardware or additional control signals, the ability to test the checker in a special test mode, design the checker based on the particular characteristics of the code, or a combination of various such methods. Typically, checkers have two outputs which in the error-free case form a two-rail signal, ie the output of the checker is ol or 10. Compared to checkers with two outputs, checkers with a single output outputting a periodically changing signal have one Set of advantages. If only checkers with a periodic output signal were used in a complex system consisting of different subsystems with different error-detecting codes, then the size of the global two-rail checker, which evaluates the signals of all the subcheckers, is reduced. Likewise, the number of lines is reduced.

Berger codes (JM Berger, "A Note on Error Detection Codes for Asymmetry Channels," Information and Control, Vol. 4, 1961, pp. 68-73) have been shown to provide optimal systematic AUED (all-unidirectional error detecting ) Codes are. However, in the event that the number of information bits is a power of 2, evil has developed a systematic AUED code which requires one check bit less than a corresponding Berger code and thus has a higher information rate (B. Böse, " On Unordered Codes, "IEEE Transactions on Computers, Vol. 40, No. 2, February 1991, pp. 125-131). The principle of this code construction has been extended by Biswas and Sengupta (GP Biswas and I. Sengupta, "Design of t-UED / AUED Codes from Berger's AUED Code," The International Conference on VLSI Design, January 1997, pp. 364-369 ). Codes with 2 ^k information are of particular interest because ^k 2 a common word width.

Architectures for Berger code checkers are usually based on the regeneration of the test symbols from the information bits that are compared with the test symbols of the code words (see, for example, MA Marouf and AD Friedman, "Design of Self-Checking Checkers for Berger Codes," International Symposium on Fault-Tolerant Computing, Toulouse, France, June 1978, pp. 179-184). Other Checker designs use threshold circuits (X. Kavousianos and D. Nikolos, "Novel Single and Double Output TSC Berger Code Checkers," 16th IEEE VLSI Test Symposium, Monterey, CA, April 1998, pp. 348-353), or averaging circuits (AP Stroele and S. Tarnick, "Programmable Embedded Self-Testing Checkers for All-Unidirectional Error Detecting Codes," 17th IEEE VLSI Test Symposium, Dana Point, CA, April 1999, pp. 361-369). A checker for Bose AUED codes was published in SW Burns and NK Jha, "A Totally Self-Checking Checker for a Parallel Unordered Coding Scheme," IEEE Transactions on Computers, Vol. 4, April 1994, pp. 490-495 discussed. For Biswas Sengupta AUED codes, no checker design has been presented in the literature so far. The object of the invention is to provide methods and arrangements for detecting unidirectional errors using a systematic disordered code C, which extend and improve the state of the art, in particular to make it possible to test the arrangements with particularly few code words.

This object is achieved by the features in the characterizing part of claims 1, 2, 3 and 5 in cooperation with the features in the preamble. Advantageous embodiments of the invention are contained in the subclaims.

A method according to the invention for detecting unidirectional errors, in particular in safety-critical circuits or systems, is characterized in that the circuit or the system uses words x

(Information bit vector) and χ ( ^c )

(Check symbol) of the code C generated, wherein the weight w (χW) = Σ _j = o ^x _{j of} the information bit vector ^χ (') at least one predetermined value Iv ₀ > 0 and / or at most a predetermined value W ₁ <n takes , ie WQ <w (χW) <Wi, and

• For all check symbols, x ^ is the binary representation of the number k _{0 of} the zeros of the information bit vector x ^ reduced by n - Wi or

• For all check symbols, it holds that χ ( ^c ) is the bitwise complement of the binary representation of the number reduced by M / k k = w / (χW) of the ones of the information bit vector xW

and the error detection comprises comparing the weight of the information bit vector χ (') with the value of the check symbol x ^.

Another method according to the invention has the advantage that the test symbol can be selected flexibly by predefinable values WQ and Wj _. satisfy the condition I / I / I - W ₀ <2 ^k - 2, where WQ denotes a specifiable minimum and w _\ a specifiable maximum weight of the information bit vector χ (') and

• For all check symbols it holds that χ ( ^c ) is the binary representation of the number k _{0 of} the zeros of the information bit vector χ (') increased by a value s - n + W ₁ or

• applies to all check symbols that χ ^(c) by 2 ^k - ₁ + W where - s - 1 bitwise complement diminished the binary representation is reduced by the number WQ / ci of ones of Informationsbit- vector χ ( '), wherein the predetermined constant value s satisfies the condition 0 <s <2 ^k - w _\ + WQ - 1 and the error detection comprises the comparison of the weight of the information bit vector χ ⁽ ' ⁾ with the value of the check symbol χ ^(c) .

In a further method according to the invention, a word x of the code C is pinned such that

A weight averaging operation maps the π-bit information bit vector χ ⁽ ' ⁾ of x, an n-bit information bit vector yW and a bit C _Q to an n-bit information bit vector zW and a bit cψ such that w (z ^) + cjp / 2 = (w (χW) + w (yW) + C ₀ ^) / 2 holds, wherein the value of the output quantity z ^ is used to the operating cycle t - l as input value yW to the working cycle t, ie y ^ (t) = z ^ (t - 1), and

• a value averaging operation the / c-bit check symbol

y ^ and a bit C _Q on a / c-bit check symbol z ^ and a bit dι such that zW + dχ / 2 = (x ^ + yW + c ^ ^c) ) / 2 applies, the value of the output size z ^{(c) is used} for the working cycle t-1 as an input value y ^ for the working cycle t, ie _y W (t) = zW (t-1),

where y (0) = y ⁽ ' ⁾ (0) y ^(c) (0) for the operating cycle 0 (initial value) is a word of the systemic random code C to be tested, the value of C _{Q is} equal to the value of cjr , ie C _Q = C _n \ and the

c ^ to the working cycle t is the inverted value of O ₁ at the working time t-1, ie, cjj \ t) = dι (t-1), whereby the sequence of the values di (t), di (tH-1), d _x (t + 2), dχ (t + 3),. , , in the case that the sequence of vectors x (t), x (t + 1), x (t + 2), x (t + 3),. , , Words of the code C are a periodic sequence 0, 1, 0, 1,. , , is and a unidirectional error is detected by the fact that the periodicity of this sequence is violated.

This method additionally constitutes a special realization of the method according to claim 1 or 2, wherein the comparison of the weight of the information bit vector xW with the value of the check symbol χ ^(c) is performed by comparing x with a word y for which the comparison of the weight of y ⁽ ' ⁾ with the value of y ^ has already taken place.

Another method according to the invention for detecting unidirectional errors in words x of a systematic disordered code C provides that the words x are translated into words x 'of a specifiable code C, and then x' is checked by a method for checking the specifiable code C, where the translation is controlled solely by the check symbol of x. In a preferred embodiment of the method according to the invention it is provided that the predefinable code C is a code according to one of claims 1 or 2 (Berger type code).

In another preferred embodiment of the method according to the invention, the translation from x to x 'X ^ j ₁ of x is complementary and x is complementary

Xf ^ J _{1 is added} to the check symbol x ^ of x. In alternative embodiments, it is contemplated that the translation from x to x 'be such that all of the most significant check bit

or be associated with its complement x £ _ _x a XOR operation or that the translation from x to x 'is performed so that the the most significant parity bit xj [_ _χ x complementary value x [_ _x, an additional information bit xή forms.

Code C is a Biswas Sengupta AUED code

k), then the translation from x to x 'is such that the value 1 is added to the check symbol x ^ of x, if χ ( ^c ) <2 / - 1, otherwise χ ( ^c ) remains unchanged, or that the Translation from x to x 'is done by inverting all bits of those words x whose check symbol χ ( ^c ) is less than 2 / if 2 / <2 ^{k ~ x} , or by inverting all bits of those words x, whose check symbol χ ( ^c ) is greater than or equal to 2 / if 2 /> 2 ^{k ~ x} , or if the translation from x to x 'is such that an additional information bit xή is considered which takes the value 0 if x ^(c) > 2 / - 1 and the value 1 if x ^ <2 / - 1.

An arrangement for detecting unidirectional errors using a systematically disordered code C comprises at least one chip and / or processor which is / are arranged such that a method for detecting unidirectional errors using the code C according to claim 1 , 2 or 5 is feasible.

In a special embodiment of this arrangement, the chip (s) and / or processors are set up in such a way that a method for detecting unidirectional errors can be carried out using a systematic disordered code C according to claim 3.

The invention will be explained in more detail below with reference to the figures in various embodiments Aus¬. Show it: FIG. 1 shows an averaging circuit (MS),

FIG. 2 shows the structure of an embedded Berger code checker with an output,

FIG. 3 shows a half adder (HA),

FIG. 4 shows a B * (2 ^k , k) -to-B ₀ (2 ^k , / c) code translator,

FIG. 5 shows a β _# (2 *, / c) -to-β _o ^-1 (2 ^{/ c} , k-1) code translator,

FIG. 6 shows an example of a size comparator,

Figure 7 shows the comparison of the gate numbers for different translation circuits.

The following statements describe new methods for detecting unidirectional errors in words of systematic disordered codes. In particular, the invention includes new embedded checker architectures having an output for Bose AUED codes and Biswas Sengupta AUED codes. The underlying design idea is to translate the codewords into words of a code similar to a Berger code and then check the obtained words with a Berger-type code checker. The architecture of the Berger-type code checker is based on the Checker designs described in AP Stroele and S. Tarnick, "Programmable Embedded Self-Testing Checkers for All-Unidirectional Error-Detecting Codes," 17th IEEE VLSI Test Symposium, Dana Point, CA, April 1999, pp. 361-369 were proposed.

Systematic disordered codes

This invention relates to disordered codes. They have the ability to detect single bit errors as well as multiple unidirectional errors. It has been proven that a code is an all-unidirectional error detecting (AUED) code if it is a disordered code (B. Böse and TRN Rao, Theory of Unidirectional Error Correcting / Detecting Codes, IEEE Transactions on Computers , Vol. C-31, No. 6, June 1986, pp. 521-530). This invention deals with systematic disordered codes in which each codeword is subdivided into an information part and a test part. Berger codes (JM Berger, "A Note on Error Detection Codes for Asymmetry Channels," Information and Control, Vol. 4, 1961, pp. 68-73) and other Berger-type codes, as well as Bose-AUED codes, are discussed. Codes (B. Böse, "On Unordered Codes," IEEE Transactions on Computers, Vol. 40, No. 2, February 1991, pp. 125-131) and Biswas Sengupta AUED codes (Biswas and I.G. Sengupta, "Design of t-UED / AUED Codes from Berger's AUED Code," lOth International Conference on VLSI Design, January 1997, pp. 364-369), both of which can be considered as the union of two different Berger type subcodes.

A Berger codeword x has n information bits and k = [Log ₂ (n + I)] check bits. The information bit vector of x is denoted by X ^ and the check symbol by x ^ ^c \ There are two classes of Berger codes. In the first class, denoted by βo (π, k), the check symbol is the binary representation of / co, where / c ₀ denotes the number of zeros in the information bit vector. In the other class, βi (π, k), the check symbol represents the bitwise complement of ki, where / ci denotes the number of ones in the information bit vector. If n = 2 ^k - 1, then BQ (Π, k) and ßi (π, k) coincide.

In general, the check symbol of a βi (π, / c) codeword is obtained by adding 2 ^k -1-n to the check symbol of the corresponding βo (π, / c) codeword. Moreover, βo (n, k) and βi (n, k) are two extreme cases of a more general class of systematic disordered codes. The codes of this class differ in the number s G {0, 1,. , , , 2 ^k - 1 - n}, which is added to the check symbol of the corresponding word in ßo (π, k). Such a code is denoted by βo (n, k). The same code can also be denoted by βf ^{2 + 1 + n + s} (n, k). As an example, the last column of Table 1 shows the check symbols of a βo (8, 4) code (and, for comparison, the check symbols of the classic Berger codes). It is easy to prove that every ß _g code, 0 <s <2 ^k - 1 - n, is a disordered code.

representative check bits

Information Bits βo (8,4) βi (8,4) β _O ² (8,4)

00000000 1000 1111 1010

00000001 Olli 1110 1001

00000011 0110 1101 1000

0000 Olli 0101 1100 Olli

00001111 0100 1011 0110

00011111 0011 1010 0101

00111111 0010 1001 0100

Olli 1111 0001 1000 0011

11111111 0000 Olli 0010

Table 1

There is another way to extend the classic Berger code. For example, if the π bit information bit vector only weights in a subinterval of 0,. , , , n then it is not always necessary to use [log ₂ (π + I)] check bits. Let n '= max (w (χ ⁽ ' ⁾ )) - min (i / t / (χW)), where w (x ^ ⁾ denotes the weight of χ ⁽ ' ⁾ . Then you only need [Iog ₂ (n '+ I)] check bits. The example of Table 2 shows a code with n = 11, which has at least 2 and at most 9 zeros. Because H = 7, only k = 3 check bits are needed. The check symbol represents the number of zeros minus 2 in such a Berger type code is also denoted by B _Q (Π, k), where s G {// - max (w (χW)),. , , , 2 ^k - 1 - max (w (χW))} and k =

+ I)]. These codes are not as efficient as the JE Smith codes, "On Separable Unordered Codes," IEEE Transactions on Computers, Vol. C-33, no. 8, August 1984, pp. 741-743, which are optimal in the event that not all information bit vectors occur. However, they are of practical interest for the design of checkers for Bose AUED codes and Biswas Sengupta AUED codes.

representative check bits

Information Bits β _o - ² (II, 3)

0000 0000 011 111

0000 0000 111 110

0000 0001 111 101

0000 0011 111 100

0000 Olli 111 011

0000 1111 111 010

0001 1111 111 001

0011 1111 111 000

Table 2

A Bose Aued codeword x has 2 ^k information bits and k check bits. The information part of x is again denoted by χ ⁽ ' ⁾ , the test part by χ ^(c) and the code by B * (2 ^k , k). Let / co be the number of zeros in χ ⁽ ' ⁾ and let / ci be the number of ones (the weight of χ ⁽ ' ⁾ ), ie / ci = w (x ^). The check symbols of the code are defined as follows:

0 <w (χW) <2 ^ ¹ -> xW z = k ₀

2 ^k - ^χ <w (χt ' ⁾ ) <2 ^k - 1 -> x ^ = k _o ~ l

The information bit vectors, which consist only of zeros and only ones, do not occur. They are replaced by the vectors in which the first 2 ^{k ~ x} bits are inverted. Therefore the code needs an additional, but simple, decoding logic. The check symbol of these two codewords is X ^ = Zc _0-1 . Table 3 shows the code for k = 3. K representatively modified

Information part information part

8 0000 0000 1111 0000 011

7 0000 0001 111

6 0000 0011 110

5 0000 Olli 101

4 0000 1111 100

3 0001 1111 010

2 0011 1111 001

1 Olli 1111 000

0 1111 1111 0000 1111 011

Table 3

Let msb (x) be the most significant bit of the vector x. As one can easily see gehö¬ ren those words of B ^. (2 ^k, k) with msb (x ^ ^c ^) = 1 for Berger type code Bo (2 ^k, k), where x ^ the binary of / c is ₀ , and the words of 6 ^ (2 ^, k) with msb (χ ( ^c )) = 0 belong to the Berger-type code Bχ {2 ^k , k), where χ ( ^c ) is the bitwise complement of kx. The following facts apply: Let x GB * (2 ^k , k). If x belongs to the Berger type code β _o (2 \ k), then x is a 6 ₁ (2 ^, / c) codeword and vice versa, where x denotes the bitwise complement of x.

It has been found that Bose-AUED codes are a special class of a more general code class (GP Biswas and I. Sengupta, "Design of t-UED / AUED Codes from Berger's AUED Code," The International Conference on VLSI Design, January 1997, pp. 364-369). These codes are constructed by modifying an S ₀ -Berger code. The modification is based on the fact that the numbers 2 / and 2 / - 1 are unordered in the binary representation. The information bit vector of weight 0 is modified to a vector of weight w '(with 2 / as the associated check symbol), and 2 / -1 is assigned to the modified information bit vector as a check symbol. In order to avoid coverage problems with codewords whose information bit vector has a weight greater than w ', the check symbols of these codewords are decremented by one. The information bit vector with weight 2 ^k is modified in the same way as the information bit vector with weight 0. Usually, one of these two vectors starts with 2 ^k -2i ones, followed by 2 / zeros, whereas in the other bit of information. Vector the bits appear in reverse order. For k check bits, there are 2 ^{k 1} ^ - I different ways to construct a Biswas Sengupta AUED code, and one of these codes (if 2 / = 2 ^k ~ ^x ) coincides with a Bose AUED code. These codes are denoted by β * (π, / c), where (2 /) indicates that the number of zeros of the information bit vectors with weight 0 and 2 ^{k have been} modified to 2 /. Table 4 shows the check symbols of three different Biswas Sengupta codes for k = 3. Here, the code β * (8, 3) is equivalent to the Bose AUED code shown in Table 3. The modified information bit vectors with weight 0 and 2 ^k 11111100 and 00111111 for ß £ ²⁾ (8, 3) and 11000000 and 00000011 for ß £ ⁶⁾ (8, 3).

Check bits vv (χW) ßf (8,3) ßi ⁴⁾ (8,3) ßf (8,3)

0 001 011 101

1 111 111 111

2 110 110 110

3 101 101 100

4 100 100 011

5 011 010 010

6 010 001 001

7,000,000,000

8 001 011 101

Table 4

Again, it can be seen that an 8 ^{2 2 /)} (2 *, / c) code is composed of words from B _Q (2 ^k , k) and β ₁ (2 ^{/ t} , k). A codeword belongs to ßi (2 ^{/ c} , k) if its check symbol is smaller than 2 /, otherwise it belongs to B ₀ (2 ^k , k). Unfortunately, the fact established for Bose-AUED codes holds that a word from B _Q (2 ^k , k) is converted into a word from βi (2 ^{/ c} , k) by complementation, and vice versa is not unrestricted for β * '' ( 2 ^k , / f) codes (except if 2 / = 2 ^{k ~ x} if they coincide with a Bose AUED code).

In a Bose-AUED code, the number of mutually different check symbols of words belonging to B ₀ (2 ^k , k) is equal to the number of different check symbols of words belonging to B i (2 ^{/ c} , k) which is ^{2k ~ x} . In all other Biswas sengupta codes, the number of different B _Q (2 ^k , / c) check symbols is smaller than those of the B i (2 ^k , k) check symbols or vice versa. For Biswas-Sengupta AUED codes: Let x GB ^ '' (2 ^k , k). If x belongs to the Berger type code with the smaller number of check symbols in B * '(2 ^k , k), then x belongs to the Berger type code with the larger number of check symbols in

Embedded checker for systematic unordered codes

In AP Stroele and S. Tarnick, "Programmable Embedded Self-Testing Checkers for AII Unidirectional Error Detecting Codes," 17th IEEE VLSI Test Symposium, Dana Point, CA, April 1999, pp. 361-369 Berger code checkers were presented, consisting of an averaging circuit and a register for storing codewords. An averaging circuit (MS) consists of two parts, as shown in FIG. The upper part carries out a weight averaging operation on the pieces of information χ (') and yW of the codewords x and y, and supplies the information part of the result z. The lower part operates on the check symbols χ ( ^c ) and y ^ and calculates its mean value z ^ ^c \ The least significant sum bit d _\ is the remainder of the division (x ^ + y ^) / 2. The two D flip Flops are initialized complementarily. It should be noted that in the upper subcircuit (in contrast to an adder with carry forwarding), the roles of the sum bit and the output carry bit are interchanged, ie the sum output of the / full adder (VA) is mixed with the carry output. Input of the / + 1 th full adder, and the carry output of the / th full adder is the / th bit of the result of the operation. The following equations apply to these two circuits:

_(;) do _ w (x ⁽ 0) + vKy «) + 4 ^i]

2

_Jc) 4 χ «0 _{+ y} ( ^c ) _{+ q} ( ^c )

2 2

Let x be a Berger codeword generated by the monitored circuit, and let y be a codeword stored in the register. Then, the weight of the information piece of z is the average weight of the pieces of information of x and y, and the value of the check symbol of z is the mean of the check symbols of x and y. Thus, z is again a Berger codeword. This word is stored in the register. The signals d ₀ and d _\ are used as an error signal, which in the error-free case is a two-rail signal and in the event that a non-codeword appears or the checker is faulty, a non-two-rail signal.

Here a second, modified architecture of this checker is shown. It differs from that of the Checkers AP Stroele and S. Tarnick, "Programmable Embedded Self-Testing Checkers for All-Unidirectional Error Detecting Codes," 17th IEEE VLSI Test Symposium, Dana Point, CA, April 1999, pp. 361-369 in that the two Teilschaltun¬ conditions of the averaging circuit are now connected. The sum output d _{0 of} the last Full adder of the weight averaging circuit (information part) is connected to the carry input of the first full adder (for the least significant bit) of the value averaging circuit (test part). The sum output O ₁ is fed back via an inverter and a D flip-flop to the carry input of the weight averaging circuit. Using this architecture, the Berger Code Checker works in a similar fashion to the m-out-of-n code checker described in AP Stroele and S. Tarnick, "Programmable Embedded Self-Testing Checks for All-Unidirectional Error Detecting Codes," 17th IEEE VLSI Test Symposium, Dana Point, CA ₁ April 1999, pp. 361-369: the leftmost D flip-flop changes value in each clock, and bits C _Q and d _x always have the same values. Since d _{\ is} a periodically changing signal, it is used as the Checker's error signal (with one output). The new checker is shown in FIG.

Example: Table 5 demonstrates the working principle of the checker for a B _Q (9, 4) orbiter code. x and y denote the two inputs of the MS and z the output. The weight of zW is obtained with

, Bit d ₀ = cj ^c) is the remainder of this division. The check symbol is obtained in the same way: z < ^c > = | _ (x ^{c) + y ^(c) + c { ⁰⁾ ) / 2j, and dι is the remainder of the division. If x and y are words of the same Berger code, then z is also a word of this code, and d ± = C _Q. The operation is shown for both types of Berger codes (above for β _o (9, 4), below for βi (9, 4)), for both C _Q = 0 and

C _Q information part cfe Check symbol O ₁

X 010111001 0100 y 010000100 Olli

Z 0 010010100 1 0110 0

Z 1 010101001 0 0101 1 ^c JoO Information part do Test symbol di

X 010111001 1010 y 010000100 1101

Z 0 010010100 1 1100 0

Z 1 010101001 0 1011 1

Table 5

It should be noted that in Table 5 the most significant bit X ^ ₁ appears to the left (as in the previous tables), while in Figure 2 (as in the other figures) x [_ _{x is} on the right. The proposed Berger code checker is self-testing with respect to all simple adhesion errors, provided that no checker input line receives a constant signal, the monitored circuit generates at least two code words with complementary test symbols and the code words appear in random sequence. (The proof is similar to the proof of Theorem 4 in AP Stroele and S. Tarnick, "Programmable Embedded Self-Testing Checkers for All-Unidirectional Error-Detecting Codes," 17th IEEE VLSI Test Symposium, Dana Point, CA, April 1999, pp 361-369.)

The same checker can also be used for B _Q (Π, / c) -erger type codes, 0 <s <2 ^k -l-n, and is self-testing if the above conditions apply. In this way, the checker is programmable. The concrete code being tested depends only on the code affiliation of the word with which the checker register was initialized. It can easily be shown that this checker architecture can also be used for the other Berger type codes described in the previous section.

It should be noted that some errors are signaled with a delay of several clocks and that there is a low probability of error masking. Both depend on the "Ruler" function of the error weight (the "Ruler" function r (x) denotes the largest number / for which 2 'x shares). The details of this behavior have been reported in A.P. Stroele and S. Tarnick, "Programmable Embedded Self-Testing Checkers for All-Unidirectional Error Detecting Codes," 17th IEEE VLSI Test Symposium, Dana Point, CA, April 1999, pp. 43-44. 361-369 and are omitted here. It has been shown that error delay and masking probability are very low. They can be reduced or avoided by iterating the combinatorial part of the checker, but this leads to an increase in checker hardware.

The easiest way to a checker for a Bose-Aued Code B * (2 ^k, k) to design, is to use two Checker parallel - a ^(k 2, k) for Berger type code Bo and one for Berger Type code Bι (2 ^k , k). For a Bose-AUED codeword one of the two checkers must signal an error and the other that no error is present. Another, but more efficient, method is to translate the Bose-AUED codewords into Berger-type codewords and check the received words with a Berger-type code checker. Therefore, the Bose-AUED code checkers described here consist of a translation circuit and a Berger type code checker. For the checker to be self-testing, it must meet the following two conditions: 1. The translation circuit must be self-testing. This means that an error will produce a non-Berger type codeword for at least one codeword, and a test codeword will be provided for each error.

2. No Berger Type Code Checker input line receives a constant signal and there are at least two complementary check symbols (see AP Stroele and S. Tarnick, "Programmable Embedded Self-Testing Checkers for All-Unidirectional Error Detecting Codes"). IEEE VLSI Test Symposium, Dana Point, CA ₁ April 1999, pp. 361-369).

Three different architectures for Bose-AUED code checkers are considered. The first draft of Checker is based on the approach outlined in SW Bums and NK Jha, "A Tally Self-Checking Checker for a Parallel Unordered Coding Scheme," IEEE Transactions on Computers, Vol. 4, April 1994, pp. 490-495 was discussed. There, the words of the β * (2 ^fc , k) code are translated into Bo ( ^2k -1, k) Berger codewords, which are then checked with a Berger code checker. The Berger code information bit vector consists of only 2 ^ - 1 bits. The remaining information bit, for example X _Q , is used to control the transformation of the check bits. If X _Q = 0 then the value of the most significant check bit x £ _ _{x is} subtracted from the check symbol χ ( ^c ) when X becomes _Q = 1 then

to χ ( ^c ) added. The check symbol transformation is implemented with half adder / half subtractor modules, where X _{Q is} the signal that controls whether the modules operate as half adders or half subtractors.

Here a simpler approach is used. Only x [_ _{x is added} to X ^. Therefore, only half adders (HA) are required for the check symbol transformation (see FIG. 3). The translation circuit is shown in FIG. The circuit translates a B * (2 ^k, k) - code in a SSO ^, / c) code. For X ^ ₁ , the HA is reduced to an OR because no carry output is needed and the first AND gate never receives the signal combination xy = 11 at its inputs. The information bits remain unchanged.

The B * {2 ^k ,

/ c) code translator based on half-adders maps each (single or multiple) unidirectional error to a non-β _o (2 ^{/ t} , / c) word. This can be shown as follows. An error that does not affect bit X ^ ₁ is mapped to a βo (2 ^{/ c} , k) non-codeword x 'which has an error at the same bit positions as x. If x ^ _ _{x is} affected, the value of x '^ deviates by at least 2 ^ ^-1 - 1 from the correct check symbol value, and the error is detected by the ßo (2 ^{/ c} , / c) code checker. It can easily be verified that the test symbols 2 '- 1 (/ = 0, ..., k) and 2 ^{k ~ x test} the entire translator (with respect to simple adhesion errors). Each HA receives all 4 bit combinations, and the OR gate receives all combinations except 11, which is not necessary for the test either. Since there are no two B * (2 ^k , / c) code check symbols χ ( ^c ) and y ^ among these vectors, which have 6 ₀ (2 ^, / c) code check symbols x '^ and y' ^ For example, if complementary signals are generated, an additional check symbol is needed (for example, y ^ - 011 .110, for which / W = 011 .1 111 is complementary to x '^ = x ^ = 100. .000 ). Thus, only k + 3 codewords are needed to test the entire checker (always assuming that no information bit is constant). Since k is small (k = log ₂ n), only a small number of codewords are needed to test the checker.

It is important to note that the described checker (consisting of the B * (2 ^k , k) -to-β _o (2 ^{/ t} , / c) code translator and a 6 ₀ (2 ^, / c ) Code checker) is not code-separating. As an example, consider the β, "(8, 3) codewords 11110000 011 and 00001111 011, which represent the information bit vectors consisting of all zeros and all ones. Every other word which has the same check symbol and an information part with weight / ci = 4 is a non-codeword. In the codeword translation, such a non-codeword is transformed into a valid B ₀ (2 ^k , / c) codeword and is not recognized. However, the purpose of the Bose AUED code and the checker is to detect unidirectional errors, but a unidirectional error is unable to transform a B * ( ^2k , k) codeword into a Berger type codeword not part of the B _% (2 ^k , / c) code. Therefore, the checker's property of not being code-divisive does not prevent it from recognizing all unidirectional errors.

The second architecture is based on the property that the word complementary to a B ₀ (2 ^k , / c) word belongs to B 1 (2 ^k , k) and vice versa. The idea is, each B ^, (2 ^k, / c) -Bose- Aued codeword x ^k on a Bχ {2, / c) -Berger type codeword x map '. If x already belongs to Bι (2 ^k , k), then it remains unchanged. If x belongs to B ₀ (2 ^k , k), then every bit of x is inverted. Which Berger-type code x belongs to is determined by the most significant check bit X ^ ₁ , which is 1 for B ₀ (2 ^k , k) and 0 for B _x (2 ^k , k). Therefore the translation is done by bitwise XOR of all bits of x with x ^ _ _x . The obtained word x 'has only k-1 check bits. x [_ _x is not needed because XOR of x £ _ _χ always yields 0 with itself. But this bit is not needed anyway, because x'M can never have a weight smaller than 2 ^{k ~ λ} and thus the ßi-check symbol can not be larger than 2 ^{k ~ x} - 1. The translation circuit is shown in FIG. It translates a B ^. (2 ^k , / c) code into a Sf ² (2 ^k , k-1) code which is identical to a β _o ^{~ 1} (2 ^{/ c} , k-1) code , On analogously, a B _it {2 ^k , / c) code can also be translated into a B ₁ ¹ (2 ^k , k-1) code by bitwise XOR of all codeword bits with the inverse of X ^ ₁ . The following considerations also apply to this translation and are omitted.

The XOR-based β * (2 ^k , / f) -to-β _o ^"1 (2 ^{/ c} , k-1) code translator forms any (single or multiple) unidirectional error on a non-β ¹ (2 ^{/ c} , k - 1) word. This can be proven as follows. An error that does not affect bit X ^ ₁ is mapped to a B _Q ¹ (2 ^{I <} , k-I) non-codeword x 'which has an error at the same bit positions as x. Just be now

affected by the error and assume that this is of the 0 -) ► 1 type. Now that X ^ ₁ = 1, all bits of the codeword are inverted. Since for x ^ ₁ = 0 k _x > 2 ^{k ~ ι} always holds, k _o '> 2 * - \ where k _Q ' denotes the number of zeros in x '. Since _BQ ¹ (2 ^{I <} , k - 1) always holds 1 <k _Q '<2 ^k ~ ^x , the only case in which the error would not be detected is if / f ₀ = kγ = 2 ^{k ~ λ} . But this can only happen if all other bits except xζ_ _x would be affected by a 1 -> ^■ O error. But then the error can not be unidirectional. Now suppose that beside

also other check bits and / or information bits are affected by a 0-> 1 error. This leads to the same situation, that k _o '> 2 ^{k ~ ι} , so that x' becomes a non-codeword in ß ^ ^"1 (2 ' ^c , / c - 1) An analogous argumentation can be used if the error of 1 -) • O type.

For the test of the translation circuit, it is only necessary that each XOR gate receive all 4 bit combinations. A minimum test amount is given in Table 6. Since this set also contains vectors whose check symbols χ ( ^c ) are transformed into complementary check symbols x '^ from B _Q ¹ (2 ^{I <} , k-1), condition 2 is fulfilled.

x (0 (c)

00. ..0 11 .. .1 10. ..0

11. ..1 00 .. .0 10. ..0

10. .. 0 00 .. .0 11. ..1

Oil .1 11 .. .1 00. ..0

00. ..0 11 .. .1 01. .. 1

11. ..1 00 .. .0 01. .. 1

Table 6

Again, this checker architecture is not code-breaking in the usual sense. But again, the only non-codewords that the checker is unable to never be caused by unidirectional errors, and the checker's ability to be non-code-breaking does not prevent it from recognizing all unidirectional errors.

The third architecture follows a similar idea as the HA-based architecture, with the difference that, depending on x [_ _x, the value of the check symbol is not increased by 1, but the weight of the information bit vector. An inverted copy of the most significant check bits is simply added to the information bits such that x "=

the additional information bit is. Thus, after code transformation, all codewords have a check symbol representing / C _Q -1. In this way, the B * (2 ^k , / c) code is translated into a β _o ^{~ 1} (2 ^{/ (} + l, / e) ~ code, where β _o ^{~ 1} (2 ^{/ t} + l, / c ) Code has an information bit vector at least one and at most 2 ^k zeros, so that 0 </ C _Q - 1 <2 ^{f e} - 1 and thus k check bits are sufficient The B _A (2 ^k ,

+ l, / φ code translation circuit consists of a simple inverter.

The B * (2 ^k , / c) -to-β _o ^-1 (2 ^{/ c} + 1, / c ^ code translation circuit also makes each (single or multiple) unidirectional error a non-β ¹ ( ., 2 ^'c 4 l / c) word from this can be shown as follows an error that does not affect bit x ^ _ _x is a ß _o ^"1 (2 ^{/ c} + l, k) - not codeword x 'shown that as x has a fault at the same bit positions now let bit x ^ _ _x affected by the error, it is assumed that the fault is a 0 -... is> ^• 1 fault This means that the check symbol x ^ at least 2 ^{k ~ ι} indicates more zeros, but in χ (') there can be at most one more zero (information bit Xn, which now equals 0 instead of 1 due to the error.) If additional information bits are involved, then the number is zero The zeros in χ (') are even lower and the difference to the erroneous χ ( ^c ) is even larger. Similar statements apply to 1 - ¥ 0 errors.

It is easy to see that the checker consisting of the B * (2 ^k , / c) -to-β _o ^"1 (2 ^{/ c} + 1, / c) code translator and the β ^ ¹ (2 ^{/ c} + 1, / c) -Code ~ Checker is self-testing under the condition that no input line receives a constant signal, the code words appear in random order and there are at least two complementary check symbols The checker is again not code - separating, but able to detect all unidirectional errors.

The checker architectures for Biswas-Sengupta-Aued codes B * (2 ^k, k) are to those ^(k 2, k) similar for Bose-Aued codes B *. The main difference is that the distinction as to whether a code word to B ₀ (2 ^k, k) or ^k B _x {2, belongs k), can not be made solely with the aid of the most significant test bits X ^. ₁ Instead, it is done by examination, whether χ ^(c) > 2 / - 1. This is implemented by using a magnitude comparator.

These size comparators are very simple, since x ^ is compared to a constant value. An example is shown in FIG. The circuit checks for a 5-bit check symbol x ^(c) if x ^ = x ^ xf * ^c) xf> x ^[c) xf ^1> 01,101th The magnitude comparator requires at most k - 1 gate with two inputs. In the example bit xjf 'is not necessary. For a Bose AUED code (which is a special Biswas Sengupta AUED code), no gate is necessary at all - it will be easy

taken. The comparator needs at most k + 1 test vectors.

It will now be shown that a unidirectional error can not be mapped to a Berger type codeword. In the HA-based translation circuit shown in Figure 4, the inverted output of the magnitude comparator is now added to χ ^(c) instead of the inverted value of x [ ^c ] _v. The function implemented by the magnitude comparator is f (x ^), ie

0 for x <«<2 / - 1, f {x ^) =

1 for xM> 2 / - l.

In the half adder-based translation circuit, no (single or multiple) unidirectional error can be transformed into an So ^, / c) codeword. This can be proven as follows. First, consider the case where the error acts only on the check symbol χ ^(c) . Assume that the β * (2 ^fc , / c) codeword is of the βi type, ie, χ ^(c) <2 / -1 and f (χ ^(c) ) = 0, which means 1 to χ ^{(c) is} added. If the error does not affect f (x ^) then it is mapped to a βo, k) non-codeword x 'which has an error at the same bit positions as x. If the error affects f (x ^), then it can only be of the 0 -> 1 type because χ ^(c) must have become greater than 2 / - 1, which in the case of a unidirectional error is only possible by changing of zeros in ones. Since now f (χ ^(c) ) = I ₁ , no 1 is added to χ ^(c) . The only possibility that the error is not recognized is that the value of χ ^{(c) is} nevertheless increased by one. This can only be the case when the least significant check bit X _{Q changes} from 0 to 1. The only case where the addition of 1 to x ^ changes the value of f (x ^) from 0 to 1 occurs when χ ^(c) = 2 / - 1. Because in this case, x ^ = 1 is, the error can not be of the 0 -> 1 type, resulting in a contradiction. Similarly, this can be shown for β * (2 ^fc , / c) codewords that are of the βo type. It is easy to see from the above argument that a 0 -> 1 error can only increase x ¹ ^. If additional or only Information bits are affected, then the number of zeros is reduced and the error is detected by the Bo (2 ^k , / c) code checker, which checks x '. Similar statements apply if the error is of the 1 -> O type.

The XOR-based translation of Biswas Sengupta AUED codes is slightly different from that for Bose AUED codes. Bitwise complementation is allowed here only for those words that belong to the Berger type code with the smaller number of check symbols in B * {2 ^k , k). Another difference is that the most significant bit check bit x £ _ _x is still necessary so that the ß * ^l '(2 ^k, / c) code in a Berger type code with k instead k - 1 check bits is translated. Consequently, the XOR operation with the output or inverted output of the magnitude comparator must also be performed for check bit X ^ ₁ . One problem is that the XOR gates for the more significant check bits may not get either the Ol or 10 signal combination. This is solved by replacing each of the affected XOR gates with an AND gate with an inverted input. Test The minimum number of codewords, all of XOR gates and AND gates, 2 ^k / (2 ^k - ¹ - \ 2i - 2 ^k - ¹ \) +. 4

In the XOR-based translation circuit with a size comparator, no (single or multiple) unidirectional error can be transformed into a code word. This fact can be proved as follows. First consider the case where the error only affects the check symbol χ ( ^c ). Assume that the B * (2 ^k , / c) codeword is of the .beta.-type, which is assumed to be the Berger-type code with the smaller number of check symbols in

k) is. If the error f (χ ( ^c) ) is not affected, then it is mapped to a non-codeword x 'which has an error at the same bit positions as x. If the error f (x) is affected, then he kan only from 0 -> ^• 1 type be because χ ^(c) greater than 2 / - must have been one, which in the case of a unidirectional error is only possible through the Change from zeros to ones. Because of f (x ^) = 1, the codeword is inverted bit by bit. Now that x 'is of the β _o type, the check symbol value is increased by 1 (compared to when x' would be of the β i type). But since x ^ has become larger due to the error, the inverted check symbol has become smaller. Thus, the action of the error on f (x ^) does not prevent its detection. Similar statements apply if the ß _o ~ type code is one code for it is assumed that he Berger the type code with the smaller number of check symbols in

k) is. An error in a word x which belongs to a Berger type code with the larger number of check symbols in β * (2 ^k , k) and / or in the information bit vector χ (') is mapped to a non-codeword x' which has an error at the same bit positions as x and thus recognized. In the inverter-based translation circuit with a size comparator, no (single or multiple) unidirectional error can be transformed into a β ¹ (2 ^{/ t} + 1, / c) codeword In the half-adder-based translation circuit, the complement of the magnitude comparator output f (x ^) is added to χ ( ^c ) In the inverter-based translator, the complement of f (χ ( ^c )) is the additional information bit xj For example, if f (x ^) = 0 (which corresponds to the addition of 1 to χ ( ^c ) in the HA-based translator), then x "= 1 (which means that χ (') has one zero less as if f (x ^) = 1, and this in turn corresponds to an increase of x ^ by 1).

The following comparison shows the advantages of the various Checker architectures compared to the prior art. The comparison includes hardware size, size of the mini¬ mimal test amount and the property of being code-separating.

All checker architectures considered here are based on a Berger type code checker. This checker has a similar structure to that described in AP Stroele and S. Tarnick, "Programmable Embedded Seal Testing Checkers for All-Unidirectional Error Detecting Codes," 17th IEEE VLSI Test Symposium, Dana Point, CA, April 1999, pp. 361-369 and its properties are not discussed here. The version with an output shown in Figure 2 consists of 2 ^k + k full adders, 2 ^k + / r + 1 D flip-flops and an inverter. The two-output version has an additional D flip-flop and an additional inverter. The checker is self-testing provided that no input line receives a constant signal, it receives two check symbols which are complementary and the codewords appear in random order. Two codewords are enough to test the entire checker. Thus, the property of being self-testing is practically achieved independently of the amount of code words made available by the circuit to be monitored.

The hardware size is compared to that of an embedded B ₀ (2 ^k , k + 1) aggravator code checker. The numbers indicate how many gates are more or less needed. The hardware size difference thus includes the gate count for the respective translation switch and parts of the Berger type code checker which, due to changed code parameters, in addition to the 60 (2 *, k + 1) -gerger code checker needed or saved. The following values are used to determine the gate numbers: AND and OR gates with two inputs each count as one gate and two inverters are counted as one gate. According to Theorem 4 in AP Stroele and S. Tarnick, "Pro For the information part of the Berger Code Checker, the full adders for the Berger Code Checker consist of two separate subscales: "Embedded Selective Testing Checkers for All-Unidirectional Error Detecting Codes," 17th IEEE VLSI Test Symposium, Dana Point, CA, April 1999, pp. 361-369 For the test part, the full adders for the test part are as described in AP Stroele and S. Tarnick, "Embedded Checker Architectures for Cyclic and Low Cost Arithmetic Codes," Journal of Electronic Testing, Vol. 16, August 2000, pp. 355-367, so that they consist of 12 and 15 gates, respectively, a half-adder consists of 3.5 gates, and D-flip-flops and XOR gates are assumed to consist of 4 gates Bose AUED code checker compared.

The Checker Architecture of SW Bums and NK Jha, "A Totally Self-Checking Checker for a Parallel Unordered Coding Scheme," IEEE Transactions on Computers, Vol. 4, April 1994, pp. 490-495 requires 6 (/ c - 2) + 11 gates for the translation circuit. In addition, the code translation saves an information bit and a check bit so that the B ₀ (2 ^k -1, k) Berger code checker is compared to a Bo (2 ^k , / c + 1) encoder. Code checker two full adders and two D flip-flops are not needed. Summarized is the additional gate number 6 (/ c - 2) - 24. (Although in the original architecture of Burns and Jha a Berger code checker with a different architecture is used, to simplify the comparison, a Berger code Code checker according to Figure 2 accepted.) The minimum test set consists of at most 2 / c + 16 codewords. Of all the architectures discussed here, it is the only one that is code-separating in the traditional sense.

The HA-based translator requires 3.5 (/ c - 1) +1.5 gates, and it saves a full adder for the check symbols and a D-type flip-flop, which together add 3.5 (/ c - 1) - 17 , 5 additional gates results. The minimum test set consists of k + 3 codewords. The checker is code separating with respect to unidirectional errors.

The gate count for the XOR-based translator is 4 (2 ^ + k-1). Since 2 less check bits are needed, the number of extra gates is reduced to 4 (2 ^ + k - 1) - 38. The minimum test set consists of 6 vectors and the checker is code-separating with respect to unidirectional errors.

The inverter-based translator requires only one inverter. An additional bit of information is required, but a check bit is saved, so that the checker saves 2.5 gates compared to a Berger code checker. The minimum test set consists of 2 vectors. Compared to other architectures, this is not a special test set. The only requirement is that it contains complementary check symbols. The checker is code-separating with respect to unidirectional errors.

Table 7 summarizes the properties of the different Checker architectures for Bose AUED codes. The first column enumerates the architectures, where Burns, HA, XOR, and INV denote the architecture of Burns and Jha, as well as the half-adder, XOR, and inverter-based architecture. The second column shows the number of extra gates compared to an embedded Berger code checker, and the third column shows the size of a minimum test set. Column 4 indicates that only the Checker of Burns and Jha is fully code-separating. All others are code-separating with respect to all unidirectional errors. FIG. 7 compares the numbers of gates additionally required for a B ₀ (2 ^k , k + 1) -gerger code checker for the various architectures.

Architecture no. add. Gate min. Number Code-separating tests

Burns 6 (A - 2) - 24 2k + 16 yes

HA 3.5 (/ r-1) -17.5 k + 3 unidir. error

XOR 4 (2 * + k - 1) - 38 6 unidir. error

INV -2.5 2 unidir. error

Table 7

The figure shows that the architecture of SW Burns and NK Jha, "A Totally Self-Checking Checker for a Parallel Unordered Coding Scheme," IEEE Transactions on Computers, Vol. 4, April 1994, pp. 490-495 for k <5 requires the least number of gates. The XOR-based architecture has only advantages for the case k = 2, which is not of practical interest. However, in the translation circuit, if XOR gates are counted as a gate (eg, if implemented with pass-transistor logic) then the number of additional gates is only ^2k + k-39, so the XOR based architecture is k < 5 is the best (curve "XOR *"), also due to the fact that it requires the least number of codeword tests among all architectures which are advantageous for k <5 in terms of hardware requirements. For k> 6, the inverter-based architecture requires the least hardware. Furthermore, it requires only 2 codeword tests for all k, and the property of being self-testing is achieved almost independent of the amount of codewords provided by the monitored circuit. Compared with a corresponding Berger code checker not only a line for the check bits is saved but also the hardware requirement is slightly lower. The embedded Biswas-Sengupta code checkers additionally have a size comparator which consists of at most k-l additional gates and requires at most / c + 1 additional codeword tests (except the XOR-based architecture, which ^uses 2 ^fc / (2 ^{/ t ~ 1} - 12 / - 2 * ^"1 !) + k + 5 test vectors required).

The numbers of test vectors given in column 3 of Table 7 do not mean that after applying the vectors of the corresponding test set, the corresponding Checker architecture is tested. Rather, it is necessary for these vectors to appear repeated in random order. Such a vector sequence (which can also contain additional vectors) is able to test the corresponding checker. A detailed proof will be in AP. Stroele and S. Tarnick, "Programmable Embedded Self-Testing Checkers for All-Unidirectional Error-Detecting Codes," 17th IEEE VLSI Test Symposium, Dana Point, CA, April 1999, pp. 361-369 given. Moreover, the size of the test set is not the main testability criterion. It is important that the translation circuit is tested and the test conditions for the Berger-type code checker (no input line is kon¬ constant, the code words appear in random order and there are two codewords with complementary test symbols) are met. The size of the codeword test set differs from case to case and depends on which codeword set generates the monitored circuit. The scopes of the smallest of these test amounts are given in Table 7.

So far, the testability analysis only considered simple trapping errors. However, the checker architectures presented here are also self-testing with respect to a significantly larger amount of other errors. The half adders and XOR gates of the translation circuits receive all the signal combinations so that they are completely tested and any combinatorial error is recognized. In AP Stroele and S. Tarnick, "Programmable Embedded Self-Testing Checkers for All-Unidirectional Error-Detecting Codes," 17th IEEE VLSI Test Symposium, Dana Point, CA, April 1999, pp. 361-369 it has been shown that in the considered Berger code checker in the adder adders, each combinatorial error in the subcircuits calculating buzzer and carry is tested, and that in each adder for the test part, each gate with all possible bit combinations, with the exception of an XOR gate. The same statements apply to the Berger type code checkers considered here. Thus, in addition to all simple sticking faults, most of the combinatorial faults within a module are detected, as most of the modules are fully tested. The testability analysis for errors that result in sequential behavior generally requires knowledge of the specific architecture of each module, which has been left open. Under the Assuming that the codewords appear repeatedly in a random sequence, every 2-vector tests are also generated for each module of a translator. Thus, all se¬ quentiellen errors are detected within a module, regardless of the module architecture. For the Berger type code checker, however, the assessment of the detectability of sequential errors is not possible without knowledge of the module architecture and the codeword set generated by the monitored circuit.

So far, only the basic architectures of the checkers have been discussed. In these architectures, the signal propagation times are relatively large. This is mainly due to the adder chains of the Berger type code checker. There are two approaches to improving the speed of the checker. The first possibility consists of splitting the connected average circuit shown in Figure 2 into two independent sub-circuits such that each of the two sub-circuits comprises at most \ (n + k) / 2] full adders. This modified averaging circuit then resembles the circuit shown in FIG. 1, with the upper part consisting of only | ^~ (π + k) / 2] full adders and the remaining n - \ (n + k) / 2] full adders are placed while maintaining their connection structure between the D flip-flop and the input C _{Q of} the lower sub-circuit. In this way, the longest path that signal C _Q must travel is at most \ {n + k) / 2] full adders, instead of n or n + k. Another way to accelerate is to implement the media scheme with a structure similar to a carry-select adder. This can be done directly with the sub-circuit for the check symbols since this is an adder. But a modification of this subcircuit is generally not necessary since k is small compared to n. In the weight-average circuit, the only difference with an adder is that the roles of the sum bit and the carry bit are reversed, so that this becomes a sum-select structure. However, this modification requires more hardware than the basic architecture. Both acceleration options can of course be combined with each other.

The versions of the discussed checker with one and two outputs hardly differ in their architecture. The code translation circuits are the same for both versions. The difference is based on the architecture of the Berger type code checker, which can have two outputs that output a two-rail signal in the error-free case, or an output that changes its value every clock. Both versions have their advantages. In a self-checking system, if checkers with two outputs are replaced by checkers with a periodic output, then complementary outputs of two checkers with one output again form a two-rail signal. That way, the size becomes a global two-rail code checker, which evaluates the signals of all subordinate sub-checker reduced. Thus, the Checker versions with an output lead to less hardware overhead for the entire system. The two-output versions, on the other hand, have a higher operating speed, especially if the averaging circuit is split as described in the previous paragraph.

In NK Jha, "Design of Sufficiently Strongly Self-Checking Embedded Checkers for Sys- tematic and Separable Codes," International Conference on Computer Design, Cambridge, MA, October 1989, p. 120-123, a very general method for designing embedded checkers for systematic codes has been proposed. But this method requires full knowledge of the subcode generated by the circuit, the Checker architecture depends on the content of that subcode, and words belonging to the code but not the subcode are considered errors. Compared to this, the architectures of the checkers discussed here are independent of the subcode, the property of being self-testing depends only on weak conditions on the subcode, and codewords that do not belong to the subcode are not signaled as errors. Such codewords can not even appear because a unidirectional error is not able to falsify a codeword (which belongs to the subcode) into another codeword (which does not belong to the subcode). Thus, the architectures presented are very well suited even in the event that the partial code is not completely known.

LIST OF REFERENCE NUMBERS

D-FF D flip-flop

GMS weight averaging circuit

MS averaging circuit

HA half adder

VA full adder

Claims

claims

1. A method for detecting unidirectional errors using a systematic unordered code C ₁ whose words x an n-bit information bit vector _x (0 = _χ W _χ ( ^< ) _{^ x} W _{1 and a k} _ _{B] t} check symbol x < ^c ) = xj ^c) x { ^c) . , , X ^ ₁ , characterized in that the weight w (x ^) = ΣJI _Q X _{j of} the information bit vector χ (') at least one predetermined value W ₀ > 0 and / or at most a predetermined value w _\ <n ¬ takes, ie W ₀ <ι / ι / (χW) <Wi, and

• for all check symbols, x ^ is the binary representation of the number k ₀ of zeros of the information bit vector χ (') reduced by n - Wχ, or

• For all check symbols it holds that χ ( ^c ) is the bitwise complement of the binary representation of the number k _\ = w (χW) of the ones of the information bit vector χ ('^' ) reduced by W ₀

and the error detection comprises comparing the weight of the information bit vector χ (') with the value of the check symbol χ ( ^c ).

2. A method for detecting unidirectional errors using a systematic unordered code C whose words x an n-bit information bit vector x «= _x p _χ W. , , X ^ ₁ and an Ar-bit check symbol χ («= x ^ ^c) x [ ^c) . , , X ^ ₁ , characterized in that predetermined values WQ and wi satisfy the condition w _\ -W ₀ <2 ^k - 2, where W ₀ denotes a predeterminable minimum and wi a specifiable maximum weight of the information bit vector χ (') and

• For all check symbols it holds that χ ( ^c ) is the binary representation of the number k _{0 of} the zeros of the information bit vector χ (') increased by a value s - n + Wi or

• applies to all check symbols that χ ^(c) to ^k 2 - W ₁ + w ₀ - s - 1 decreased bitwise complement of the binary representation is to w ₀ ₁ Zf reduced number of ones of the vector x ^ Informationsbit-,

wherein the predetermined constant value s satisfies the condition 0 <s <2 ^k - Wi + W ₀ - 1 and the error detection comprises the comparison of the weight of the information bit vector x ^ with the value of the check symbol χ ( ^c ).

3. A method for detecting unidirectional errors using a systematic unordered code C whose words x a π-bit information bit vector ^{χ (} ' ⁾ = 4 ⁰ Xi ⁰ ■ ■ -4- ₁ ^{and a} ^ r-bit check symbol ^{χ (c)} = x _o ^{c) x [ ^c) . , , X ^ ₁ , where

A weight averaging operation the π bit information bit vector χ ⁽ ' ^{) of} the word x to be tested, a π bit information bit vector y ^ and a bit C _Q to a π bit information bit vector z ^ and a bit cfi mapping such that w (z) + cψ / 2 = (iv (χ ⁽ ^'')) + n / _(y ⁽⁰⁾ + _C W) / ₂ holds, where the value of the output variable z ^ for operating cycle t - 1 is used as the input value y ^ to the working clock ε, ie y ^(;) (f) = z ^(/) (f-1), and

A value averaging operation maps the / c-bit check symbol χ ^(c) , a / c-bit check symbol y ^ and a bit c ^ onto a / c-bit check symbol z ^ and a bit c / χ such that z ^{( /)} + c / i / 2 = (x ^(c) + y ^(c) +

the value of the output quantity z 1 at the operating cycle t-1 is used as the input value y ^(c) for the operating cycle ε, ie y ^(c) (t) = z ^(c) (t-1)

where y (0) = y ^ (0) y ^(c) (0) at operating cycle 0 (initial value) is a word of the systematic random code C to be tested, characterized in that the value of c ^ ^c) equals the value of cfi, ie c ^ = cP, and the value of C _Q at the operating cycle t is the inverted value of dι to the working cycle £ - 1, ie cj ° (t) = rfι (tl), whereby the sequence of values ^ (f ), (h (t + l), d ^ t + 2), d ^ t + 3),. , , in the case that the sequence of vectors x (£), x (£ + 1), x (£ + 2), x (f + 3),. , , Words of the code C are a periodic sequence 0, 1, 0, 1,. , , is and a unidirectional error is detected by the fact that the periodicity of this sequence is violated.

4. The method according to claim 1 or 2, characterized in that the method comprises method steps according to claim 3.

5. A method for detecting unidirectional errors in words x of a systematic disordered code C, wherein the words x are translated into words x 'of a predetermined code C, and then x' is checked by a method for testing the specifiable code C, characterized characterized in that the translation is controlled solely by the check symbol of x.

6. The method according to claim 5, characterized in that the predeterminable code C is a code according to one of claims 1 or 2.

7. The method according to claim 6, characterized in that the code C is a Bose-AUED code B * (n, k) and the translation of x to x 'der¬ art done that the most significant check bit X ^ Z ₁ of x complementary value X ^ _{1 is added} to the check symbol χ ( ^c ) of x.

8. The method according to claim 6, characterized in that the code is a Bose-C Aued Code B * (n, k), and the translation from x to x 'is performed so that all of the most significant parity bit X ^ ₁ different bits of x with x £ _ _x or with its complement

be linked.

9. The method according to claim 6, characterized in that the code C is a Bose-AUED code B * (n, k) and the translation from x to x 'de¬ rart takes place that the most significant check bit x ^ _x of x complementary value Xj ^ _{1 forms} an additional information bit xή.

10. The method according to claim 6, characterized in that the code C is a Biswas Sengupta AUED code

k) and the translation from x to x 'is such that the value 1 is added to the check symbol χ ( ^c ) of x when χ ( ^c ) <2 / -1, otherwise χ ( ^c ) remains unchanged.

11. The method according to claim 6, characterized in that the code C is a Biswas Sengupta AUED code ß * '' (n, k) and the translation from x to x 'is such that all bits of those words inverted x whose check symbol χ ( ^c ) is less than 2 / if 2 / <2 ^{k ~ x} or all bits of those words x whose check symbol χ ( ^c ) is greater than or equal to 2 / if 2 / > 2 * ^"1 is.

12. The method according to claim 6, characterized in that the code C is a Biswas Sengupta AUED code

k) and the translation from x to x 'is such that an additional information bit xn' is considered which takes the value 0 if x ^(c >> 2 / - 1 and the value I ₁ if x ^(c) <2 / - 1.

13. Arrangement with at least one chip and / or processor, which is such that a method for the detection of unidirectional errors using a systematic disordered code C according to claim 1, 2 or 5 can be carried out.

14. Arrangement according to claim 13, characterized in that

Chip (s) and / or processor (s) is (are) arranged such that a method for detecting unidirectional errors using a systematic ungeord¬ Neten code C according to claim 3 is feasible.