WO2005122264A2 - Method and process intermediate for electrostatic discharge protection in flat panel imaging detectors - Google Patents

Method and process intermediate for electrostatic discharge protection in flat panel imaging detectors Download PDF

Info

Publication number
WO2005122264A2
WO2005122264A2 PCT/US2005/017821 US2005017821W WO2005122264A2 WO 2005122264 A2 WO2005122264 A2 WO 2005122264A2 US 2005017821 W US2005017821 W US 2005017821W WO 2005122264 A2 WO2005122264 A2 WO 2005122264A2
Authority
WO
WIPO (PCT)
Prior art keywords
layer
shorting bar
etching
metal layer
metal
Prior art date
Application number
PCT/US2005/017821
Other languages
French (fr)
Other versions
WO2005122264A3 (en
Inventor
Zhong Shou Huang
Original Assignee
Perkinelmer, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Perkinelmer, Inc. filed Critical Perkinelmer, Inc.
Priority to KR1020077000041A priority Critical patent/KR101136815B1/en
Priority to CN2005800178319A priority patent/CN101091257B/en
Priority to EP05751054A priority patent/EP1751801A4/en
Publication of WO2005122264A2 publication Critical patent/WO2005122264A2/en
Publication of WO2005122264A3 publication Critical patent/WO2005122264A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14692—Thin film technologies, e.g. amorphous, poly, micro- or nanocrystalline silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

Definitions

  • This invention relates generally to the field of fabrication processing of flat panel imaging detectors and more particularly to the use of one or more shorting elements employing conductive materials in the underlying process for electrostatic discharge protection between components, the shorting elements removed during standard forming processes for the detector.
  • Photosensitive element arrays for converting incident radiant energy into an electrical signal are commonly used in imaging applications, for example, in x-ray imagers and facsimile device arrays.
  • Hydrogenated amorphous silicon (a-Si:H) and alloys of a-Si are commonly used in the fabrication of photosensitive elements for such arrays due to the advantageous characteristics of a-Si and the relative ease of fabrication.
  • photosensitive elements such as photodiodes
  • TFTs thin film transistors
  • X-ray imagers are formed on a substantially flat substrate, typically glass.
  • the imager includes an array of pixels with light-sensitive imaging elements, typically photodiodes, each of which has an associated switching element, such as a TFT or one or more additional addressing diodes.
  • a scintillator In conjunction with a scintillator, x-rays are transformed into visible light for imaging with the photosensitive elements.
  • the photosensitive elements are connected at one surface to a switching device, typically a TFT, and at the other surface to a common electrode which contacts all the photodiodes in parallel.
  • the array is addressed by a plurality of row and column address lines having contact pads
  • the voltage on the row lines, and hence the TFTs, are switched on in turn, allowing the charge on that scanned line's photodiodes to be read out via the column address lines, which are connected to external amplifiers.
  • the row address lines are commonly referred to as “scan lines” and the column address lines are referred to as “data lines.”
  • the address lines are electrically contiguous with contact fingers which extend from the active region toward the edges of the substrate, where they are in turn electrically connected to contact pads. Connection to external scan line drive and data line read out circuitry is made via the contact pads.
  • ESD electrostatic discharge
  • ESD damage such as oxide and nitride breakdown can occur within 10ns. Therefore, TFT type ESD protection devices are only effective for relatively slow charge building up.
  • the most effective ESD protection method in the prior art is simply to connect all metal traces together to the ground, so there would not be any bias voltage buildup between them.
  • Metal traces are later separated by using laser or mechanical glass scriber to allow panel testing or assembly. However, laser cutting inevitably generates conductive debris or particles. Mechanical scribing through metal traces will itself introduce ESD risk during scribing. It is also possible to separate metal traces from ground by using wet or dry etching processes. But that requires an additional process step.
  • the present invention constitutes a method for providing electrostatic discharge protection during fabrication processing of photodiode array panels.
  • a first metal layer having first trace and pad features is deposited on a glass substrate.
  • the first metal layer is etched to define the trace and pad contours and a dielectric layer is deposited over the first metal layer.
  • the dielectric layer is etched to provides first vias through the dielectric layer and a second metal layer is deposited contacting the first metal layer through the first vias providing a shorting bar for contact between the traces during further handling and processing for ESD protection.
  • a second dielectric layer is then deposited and a second via surrounding the shorting bar is created during normal processing for connection of a third metal layer to the second metal layer.
  • the third metal layer is deposited and masked for etching.
  • the photoresist around the shorting bar is removed and wet etching of the third metal layer removes the shorting bar allowing normal operation of the array.
  • additional ESD protection is provided by leakage paths created through undoped layers of FET silicon as well as metal shorting bars. Etching of the metal shorting bars leaves the FET silicon bars as leakage paths for continued ESD protection until etching for photodiode bottom contact during which the FET silicon shorting bars are simultaneously removed.
  • FIG. 1 is a top view of exemplary traces and circuit features of an imager array with a first embodiment of the present invention
  • FIG. 2a is a side section view of the layers of the array prior to etching
  • FIG. 2b is a side section view of the layers of the array after etching
  • FIG. 3 a is a side section view of the layers of an array employing an alternative embodiment of the invention before the second metal deposition step
  • FIG. 3b is a side section view of the layers of the array of FIG. 3a after the second metal deposition step and after the second metal etching
  • FIG. 3c is a side section view of the layers of the array after deposition of amorphous silicon nitride and diode etching
  • FIG. 4 is a top view of the array of FIGs. 3a-c showing the etched portion of the shorting bar of the present invention after diode etching.
  • FIG. 1 shows trace 10, a scan line for the embodiment shown and trace 12, a ground line for the embodiment shown, which are representative of the traces for the array as created during the various deposition processes as described subsequently.
  • supplemental pad features 14 and 16 extend from the first and second trace, respectively, for interconnection by a shorting bar 18.
  • the features employed for shorting bar connection are not specific to that purpose but are existing features which have a continuing purpose after removal of the shorting bar as described subsequently.
  • the shorting bar is deposited during normal processing for forming the traces.
  • the first trace and pad features are deposited in a first metal layer 20 on a glass substrate 22. Etching processes to define the trace and pad contours have been performed and a first dielectric layer of a-Si 24 deposited over the first metal. Etching of the a-Si layer provides first vias 26 through the a-Si layer.
  • a second metal layer 28 is deposited for the TFT source and drain electrodes in the embodiment of the array shown. This second metal layer contacts the first metal layer through the first vias providing shorting contact between the first and second traces as well as the a-Si elements during further handling and processing for ESD protection.
  • a second dielectric SiO 2 multilayer 30 is deposited and a second via 32 is created surrounding the shorting bar during normal processing for connection of a third metal layer 34 to the second metal layer.
  • this second via is approximately 20 ⁇ m x 40um.
  • the third metal layer which for the embodiment shown is for data lines in the array, is then deposited.
  • the shorting bar is masked for etching and, after deposition of the third metal layer, the photoresist around the shorting bar is removed.
  • the top metal layer is etched away first, and then the shorting bar is removed by the same process. In the region of the second via, both the second and third metal layers are etched away.
  • the shorting bar is sized with a relative width narrow enough to allow the same etching recipe to perform the etching.
  • the shorting bar width is only 5 ⁇ m, whereby side etching occurs faster than top etching and the shorting bar is eliminated in its entirety during the etch.
  • the total etching time in the process step is the same as if no shorting bar was present.
  • the second metal layer is thicker than the first metal layer resulting in poorer step coverage.
  • the second metal constituting the shorting bar is surrounded by the second via therefore any tunneling etching along the poor step coverage of the second metal is confined by the second via.
  • the area of the second via is shown in section view in FIG.
  • FIGs. 1, 2a and 2b after the wet etch showing the removal of the shorting bar.
  • the first embodiment disclosed with respect to FIGs. 1, 2a and 2b relies on a metal layer as the shorting bar which is removed in one etching step near the end of the array processing.
  • a second embodiment which relies on multiple shorting elements in different layers is disclosed in FIGs. 3a-c and 4. This embodiment provides a first shorting element in a thin metal layer employed in the process and an amorphous silicon phosphor doped layer with the intrinsic layer as a second shorting element. As represented in FIG.
  • a TFT deposition process first generates continuously three layers inside PECVD chamber, an amorphous Silicon Nitride (a- SiN) layer 40, an undoped a-Si:H layer 42 and a phosphorus doped a-Si:H layer 44 which are jointly referred to as FET silicon.
  • the n+ a-Si:H is then capped by a thin metal layer 46 of molybdenum in the embodiment shown.
  • metal traces are shorted with shorting bar traces deposited in this metal cap for ESD protection.
  • a second metal layer 48 which for the present embodiment is the same material as the thin metal cap layer, is deposited for the traces in the array. After metal etching as shown in FIG.
  • the metal shorting bars are removed since the thin metal cap layer is etched with the second metal layer leaving metal traces 50 and 52. All metal traces, 50 and 52 as exemplary, are still connected through undoped FET silicon bars 54 (as best seen in FIG.4) that continuously provides a leakage current path for static charges.
  • the following process is deposition of an a-SiN passivation layer 56 on the TFT panel and opening vias at each pixel in the array for photodiode bottom contact. A via 58 is also put right above the FET silicon shorting bar. During etching of about 1 ⁇ m of a-Si:H for diode, the thin FET silicon is also removed, which then completely isolates all traces as shown in FIG.
  • the partially completed photodiode array panels comprise a process intermediate which provides ESD protection for the panels during handling and further processing.
  • the first embodiment provides a metal shorting bar which remains a part of the process intermediate until the etching of the third metal layer is accomplished.
  • the second embodiment provides ESD protection through two paths, a first set of metal shorting bar traces and leakage path through undoped FET silicon, each of which is removed at predetermined process steps.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electromagnetism (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Nanotechnology (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Thin Film Transistor (AREA)

Abstract

Shorting bars (18) are provided for electrostatic discharge protection as a portion of trace (10, 12) deposition in a photodiode array. During normal processing for etching of the metal layers, the shorting bars are removed without additional processing requirements. Additional shorting elements are provided by employing FET silicon layers (40, 42, 44) having traces (54) in contact with the array traces to provide extended ESD protection until removal of those shorting elements during normal processing for opening vias for photodiode bottom contact.

Description

METHOD AND PROCESS INTERMEDIATE FOR ELECTROSTATIC DISCHARGE PROTECTION IN FLAT PANEL IMAGING DETECTORS
BACKGROUND OF THE INVENTION Field of the Invention This invention relates generally to the field of fabrication processing of flat panel imaging detectors and more particularly to the use of one or more shorting elements employing conductive materials in the underlying process for electrostatic discharge protection between components, the shorting elements removed during standard forming processes for the detector. Description of the Related Art Photosensitive element arrays for converting incident radiant energy into an electrical signal are commonly used in imaging applications, for example, in x-ray imagers and facsimile device arrays. Hydrogenated amorphous silicon (a-Si:H) and alloys of a-Si are commonly used in the fabrication of photosensitive elements for such arrays due to the advantageous characteristics of a-Si and the relative ease of fabrication. In particular, photosensitive elements, such as photodiodes, can be formed from such materials in conjunction with necessary control or switching elements, such as thin film transistors (TFTs), in relatively large arrays. X-ray imagers, for example, are formed on a substantially flat substrate, typically glass. The imager includes an array of pixels with light-sensitive imaging elements, typically photodiodes, each of which has an associated switching element, such as a TFT or one or more additional addressing diodes. In conjunction with a scintillator, x-rays are transformed into visible light for imaging with the photosensitive elements. The photosensitive elements, typically photodiodes, are connected at one surface to a switching device, typically a TFT, and at the other surface to a common electrode which contacts all the photodiodes in parallel. The array is addressed by a plurality of row and column address lines having contact pads
-l- located along the sides of the array. In operation, the voltage on the row lines, and hence the TFTs, are switched on in turn, allowing the charge on that scanned line's photodiodes to be read out via the column address lines, which are connected to external amplifiers. The row address lines are commonly referred to as "scan lines" and the column address lines are referred to as "data lines." The address lines are electrically contiguous with contact fingers which extend from the active region toward the edges of the substrate, where they are in turn electrically connected to contact pads. Connection to external scan line drive and data line read out circuitry is made via the contact pads. As with most microcircuit devices, the elements of these arrays are subject to damage by electrostatic discharge (ESD). This is particularly true where the relative size, length and separation of traces may result in smaller relative capacitance values. To provide protection from ESD, prior art circuits have employed sacrificial capacitors to absorb ESD energy and therefore protect the image array from damage. But damaged capacitors generate a hard short between traces that needs to be completely removed by laser repair or an additional process step. Some of the known prior art devices use a TFT as an ESD protection device. The gate of the TFT is connected to drain electrode, so large static voltage will turn on the transistor and. leak the static charge away before causing any damage. The on-resistance of the TFT is normally larger than 500KΩ, for an average line capacitance such as 50pf, 100ns is needed to completely discharge the static charge. ESD damage such as oxide and nitride breakdown can occur within 10ns. Therefore, TFT type ESD protection devices are only effective for relatively slow charge building up. The most effective ESD protection method in the prior art is simply to connect all metal traces together to the ground, so there would not be any bias voltage buildup between them. Metal traces are later separated by using laser or mechanical glass scriber to allow panel testing or assembly. However, laser cutting inevitably generates conductive debris or particles. Mechanical scribing through metal traces will itself introduce ESD risk during scribing. It is also possible to separate metal traces from ground by using wet or dry etching processes. But that requires an additional process step. It is therefore desirable to provide ESD protection for microcircuit elements during processing wherein the protection device is eliminated during processing without additional processing steps. It is further desirable that no debris or other contaminates from the protection device be present to contaminate processes elements or impart residual features on the final product which could impact performance.
SUMMARY OF THE INVENTION The present invention constitutes a method for providing electrostatic discharge protection during fabrication processing of photodiode array panels. A first metal layer having first trace and pad features is deposited on a glass substrate. The first metal layer is etched to define the trace and pad contours and a dielectric layer is deposited over the first metal layer. The dielectric layer is etched to provides first vias through the dielectric layer and a second metal layer is deposited contacting the first metal layer through the first vias providing a shorting bar for contact between the traces during further handling and processing for ESD protection. A second dielectric layer is then deposited and a second via surrounding the shorting bar is created during normal processing for connection of a third metal layer to the second metal layer. The third metal layer is deposited and masked for etching. The photoresist around the shorting bar is removed and wet etching of the third metal layer removes the shorting bar allowing normal operation of the array. In an alternative embodiment, additional ESD protection is provided by leakage paths created through undoped layers of FET silicon as well as metal shorting bars. Etching of the metal shorting bars leaves the FET silicon bars as leakage paths for continued ESD protection until etching for photodiode bottom contact during which the FET silicon shorting bars are simultaneously removed. BRIEF DESCRIPTION OF THE DRAWINGS These and other features and advantages of the present invention will be better understood by reference to the following detailed description when considered in connection with the accompanying drawings wherein: FIG. 1 is a top view of exemplary traces and circuit features of an imager array with a first embodiment of the present invention; FIG. 2a is a side section view of the layers of the array prior to etching; FIG. 2b is a side section view of the layers of the array after etching; FIG. 3 a is a side section view of the layers of an array employing an alternative embodiment of the invention before the second metal deposition step; FIG. 3b is a side section view of the layers of the array of FIG. 3a after the second metal deposition step and after the second metal etching; FIG. 3c is a side section view of the layers of the array after deposition of amorphous silicon nitride and diode etching; and, FIG. 4 is a top view of the array of FIGs. 3a-c showing the etched portion of the shorting bar of the present invention after diode etching. DETAILED DESCRIPTION OF THE INVENTION Referring to the drawings, FIG. 1 shows trace 10, a scan line for the embodiment shown and trace 12, a ground line for the embodiment shown, which are representative of the traces for the array as created during the various deposition processes as described subsequently. For the embodiment shown, supplemental pad features 14 and 16 extend from the first and second trace, respectively, for interconnection by a shorting bar 18. In alternative embodiments, the features employed for shorting bar connection are not specific to that purpose but are existing features which have a continuing purpose after removal of the shorting bar as described subsequently. The shorting bar is deposited during normal processing for forming the traces. As shown in FIG.2a, the first trace and pad features are deposited in a first metal layer 20 on a glass substrate 22. Etching processes to define the trace and pad contours have been performed and a first dielectric layer of a-Si 24 deposited over the first metal. Etching of the a-Si layer provides first vias 26 through the a-Si layer. A second metal layer 28 is deposited for the TFT source and drain electrodes in the embodiment of the array shown. This second metal layer contacts the first metal layer through the first vias providing shorting contact between the first and second traces as well as the a-Si elements during further handling and processing for ESD protection. A second dielectric SiO2 multilayer 30 is deposited and a second via 32 is created surrounding the shorting bar during normal processing for connection of a third metal layer 34 to the second metal layer. For the embodiment shown, this second via is approximately 20μm x 40um. The third metal layer, which for the embodiment shown is for data lines in the array, is then deposited. Using known photoresist masking techniques, the shorting bar is masked for etching and, after deposition of the third metal layer, the photoresist around the shorting bar is removed. During wet etching of the third metal layer, the top metal layer is etched away first, and then the shorting bar is removed by the same process. In the region of the second via, both the second and third metal layers are etched away. The shorting bar is sized with a relative width narrow enough to allow the same etching recipe to perform the etching. For the embodiment shown, the shorting bar width is only 5 μm, whereby side etching occurs faster than top etching and the shorting bar is eliminated in its entirety during the etch. The total etching time in the process step is the same as if no shorting bar was present. In the embodiment shown, the second metal layer is thicker than the first metal layer resulting in poorer step coverage. The second metal constituting the shorting bar is surrounded by the second via therefore any tunneling etching along the poor step coverage of the second metal is confined by the second via. The area of the second via is shown in section view in FIG. 2b after the wet etch showing the removal of the shorting bar. The first embodiment disclosed with respect to FIGs. 1, 2a and 2b relies on a metal layer as the shorting bar which is removed in one etching step near the end of the array processing. A second embodiment which relies on multiple shorting elements in different layers is disclosed in FIGs. 3a-c and 4. This embodiment provides a first shorting element in a thin metal layer employed in the process and an amorphous silicon phosphor doped layer with the intrinsic layer as a second shorting element. As represented in FIG. 3a, a TFT deposition process first generates continuously three layers inside PECVD chamber, an amorphous Silicon Nitride (a- SiN) layer 40, an undoped a-Si:H layer 42 and a phosphorus doped a-Si:H layer 44 which are jointly referred to as FET silicon. The n+ a-Si:H is then capped by a thin metal layer 46 of molybdenum in the embodiment shown. At this time, metal traces are shorted with shorting bar traces deposited in this metal cap for ESD protection. For the embodiment shown, a second metal layer 48, which for the present embodiment is the same material as the thin metal cap layer, is deposited for the traces in the array. After metal etching as shown in FIG. 3b, the metal shorting bars are removed since the thin metal cap layer is etched with the second metal layer leaving metal traces 50 and 52. All metal traces, 50 and 52 as exemplary, are still connected through undoped FET silicon bars 54 (as best seen in FIG.4) that continuously provides a leakage current path for static charges. The following process is deposition of an a-SiN passivation layer 56 on the TFT panel and opening vias at each pixel in the array for photodiode bottom contact. A via 58 is also put right above the FET silicon shorting bar. During etching of about 1 μm of a-Si:H for diode, the thin FET silicon is also removed, which then completely isolates all traces as shown in FIG. 4 as a top view of the array elements shown in section in FIGs. 3a-c. For both the embodiments described, the partially completed photodiode array panels comprise a process intermediate which provides ESD protection for the panels during handling and further processing. The first embodiment provides a metal shorting bar which remains a part of the process intermediate until the etching of the third metal layer is accomplished. The second embodiment provides ESD protection through two paths, a first set of metal shorting bar traces and leakage path through undoped FET silicon, each of which is removed at predetermined process steps. Having now described the invention in detail as required by the patent statutes, those skilled in the art will recognize modifications and substitutions to the specific embodiments disclosed herein. Such modifications are within the scope and intent of the present invention as defined in the following claims.

Claims

WHAT IS CLAIMED IS:
1. A method for providing electrostatic discharge protection during fabrication processing of photodiode array panels comprising the steps of: depositing first trace and pad features in a first metal layer on a glass substrate; etching to define the trace and pad contours; depositing a first dielectric layer over the first metal layer; etching the first dielectric layer to provides first vias through the dielectric layer; depositing a second metal layer contacting the first metal layer through the first vias providing a shorting bar for contact between the traces during further handling and processing for ESD protection; depositing a second dielectric layer; creating a second via surrounding the shorting bar during normal processing for connection of a third metal layer to the second metal layer; depositing the third metal layer; masking the third metal for etching; removing the photoresist around the shorting bar; and, etching the third metal layer and the shorting bar.
2. A method as defined in claim 1 wherein the second via is about 20μm x 40μm.
3. A method as defined in claim 1 wherein the shorting bar is sized with a relative width narrow enough to allow the same etching recipe for removal of the third metal layer to perform the etching of the shorting bar.
4. A method as defined in claim 3 wherein the shorting bar width is defined so side etching occurs faster than top etching and the shorting bar is eliminated in its entirety during the etch.
5. A method as defined in claim 4 wherein the shorting bar width is about 5 μm.
6. A method as defined in claim 1 wherein the first dielectric layer is a-Si.
7. A method as defined in claim 1 wherein the second dielectric layer is a SiO2 multilayer.
8. A method for providing electrostatic discharge protection during fabrication processing of photodiode array panels comprising the steps of: conducting a TFT deposition process to first generate a plurality of FET silicon dielectric layers, at least one of which is undoped; capping the dielectric layers by a thin metal layer having shorting bar traces for ESD protection; depositing a second metal layer for the traces in the array having contact with the shorting bar traces; metal etching to remove the metal shorting bars leaving metal traces with all metal traces still connected through undoped FET silicon bars to continuously provide a leakage current path for static charges; depositing a passivation layer; opening vias at each pixel in the array for photodiode bottom contact and a via above each FET silicon shorting bar; and, etching the FET silicon for diodes and simultaneously removing the undoped
FET silicon bars to completely isolate all traces.
9. The method of claim 8 wherein the plurality of dielectric layers are three layers comprising an amorphous Silicon Nitride (a-SiN) layer, an undoped a-Si:H layer and a phosphorus doped a-Si:H layer.
10. The method of claim 9 wherein the passivation layer is a-SiN.
11. The method of claim 10. wherein the step of etching the FET silicon comprises etching about lμm of the a-Si:H.
12. The method of claim 8 wherein the thin metal cap layer is molybdenum.
13. The method of claim 8 wherein the second metal layer is the same material as the thin metal cap layer
14. A process intermediate providing electrostatic discharge protection during fabrication processing of photodiode array panels comprising: first trace and pad features deposited in a first metal layer (20) on a glass substrate (22) which are etched to define the trace and pad contours; a first dielectric layer (24) deposited over the first metal layer and etched to provides first vias (26) through the dielectric layer; a second metal layer (28) deposited and contacting the first metal layer through the first vias providing a shorting bar for contact between the traces during further handling and processing for ESD protection; a second dielectric layer (30) deposited over the second metal layer creating a second via (32) surrounding the shorting bar during normal processing for connection of a third metal layer (34) to the second metal layer; a third metal layer (34) which is masked for etching including removing the photoresist around the shorting bar.
15. A process intermediate as defined in claim 14 wherein the first dielectric layer is a-Si.
16. A process intermediate as defined in claim 14 wherein the second dielectric layer is SiO2.
17. A process intermediate as defined in claim 14 wherein the second via is about
20μm x 40μm.
18. A process intermediate as defined in claim 14 wherein the shorting bar is sized with a relative width narrow enough to allow the same etching recipe for removal of the third metal layer to perform the etching of the shorting bar.
19. A process intermediate as defined in claim 18 wherein the shorting bar width is defined so side etching occurs faster than top etching and the shorting bar is eliminated in its entirety during the etch.
20. A process intermediate as defined in claim 4 wherein the shorting bar width is about 5 μm.
21. A process intermediate providing electrostatic discharge protection during fabrication processing of photodiode array panels comprising: a plurality of FET silicon dielectric layers (40, 42, 44), at least one of which is undoped providing shorting bars; a thin metal layer (46) capping the FET silicon and having shorting bar traces for ESD protection; a second metal layer (48) for the traces in the array in contact with the shorting bar traces of the thin metal cap and the undoped FET silicon bars; the metal shorting bars connecting the metal traces when present and with all metal traces connected through undoped FET silicon bars to continuously provide a leakage current path for static charges upon removal of the metal shorting bars by etching.
22. The process intermediate of claim 21 wherein the thin metal cap layer is molybdenum.
23. The process intermediate of claim 21 wherein the second metal layer is the same material as the thin metal cap layer.
24. The process intermediate of claim 21 wherein the plurality of dielectric layers are three layers comprising an amorphous Silicon Nitride (a-SiN) layer, an undoped a- Si:H layer and a phosphorus doped a-Si:H layer.
PCT/US2005/017821 2004-06-02 2005-05-19 Method and process intermediate for electrostatic discharge protection in flat panel imaging detectors WO2005122264A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020077000041A KR101136815B1 (en) 2004-06-02 2005-05-19 Method and process intermediate for electrostatic discharge protection in flat panel imaging detectors
CN2005800178319A CN101091257B (en) 2004-06-02 2005-05-19 Method and process intermediate for electrostatic discharge protection in flat panel imaging detectors
EP05751054A EP1751801A4 (en) 2004-06-02 2005-05-19 Method and process intermediate for electrostatic discharge protection in flat panel imaging detctors

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/859,678 2004-06-02
US10/859,678 US7217591B2 (en) 2004-06-02 2004-06-02 Method and process intermediate for electrostatic discharge protection in flat panel imaging detectors

Publications (2)

Publication Number Publication Date
WO2005122264A2 true WO2005122264A2 (en) 2005-12-22
WO2005122264A3 WO2005122264A3 (en) 2007-06-28

Family

ID=35449538

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/017821 WO2005122264A2 (en) 2004-06-02 2005-05-19 Method and process intermediate for electrostatic discharge protection in flat panel imaging detectors

Country Status (6)

Country Link
US (2) US7217591B2 (en)
EP (1) EP1751801A4 (en)
KR (1) KR101136815B1 (en)
CN (1) CN101091257B (en)
TW (1) TWI300992B (en)
WO (1) WO2005122264A2 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100926725B1 (en) * 2007-10-02 2009-11-16 인파크 테크놀러지 컴퍼니 리미티드 Abnormal voltage protection device of electronic circuit and manufacturing method
CN102244082B (en) * 2010-05-13 2014-12-17 上海天马微电子有限公司 Manufacturing method of array substrate
CN102298239A (en) * 2011-08-25 2011-12-28 南京中电熊猫液晶显示科技有限公司 Metal-layer electrode on thin film transistor-liquid crystal display array substrate
US9733331B2 (en) 2012-09-10 2017-08-15 Apple Inc. Method of manufacturing touch sensors
CN103943611B (en) * 2013-02-22 2016-11-23 上海天马微电子有限公司 A kind of array base palte and panel
KR102352316B1 (en) 2015-08-11 2022-01-18 삼성전자주식회사 Printed circuit board
CN106707715B (en) * 2017-01-11 2019-05-21 中国科学院长春光学精密机械与物理研究所 A kind of semiconductor devices and preparation method thereof

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4803536A (en) 1986-10-24 1989-02-07 Xerox Corporation Electrostatic discharge protection network for large area transducer arrays
JPH02137366A (en) 1988-11-18 1990-05-25 Nec Corp Diode-type active matrix substrate
US5220443A (en) 1991-04-29 1993-06-15 Nec Corporation Matrix wiring substrate and active matrix display having non-linear resistance elements for electrostatic discharge protection
US5313319A (en) 1992-06-17 1994-05-17 General Electric Company Active array static protection devices
JPH06186590A (en) 1992-12-21 1994-07-08 Sharp Corp Active matrix type liquid crystal display panel
US5353142A (en) 1993-04-29 1994-10-04 Honeywell Inc. Electro static discharge protection for processing active matrix liquid crystal displays
DE69528384D1 (en) * 1995-07-31 2002-10-31 Fire Technology Inc SEMICONDUCTOR SWITCH MATRIX WITH PROTECTION AGAINST ELECTRICAL DISCHARGE AND MANUFACTURING PROCESS
JP3642876B2 (en) * 1995-08-04 2005-04-27 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device using plasma and semiconductor device manufactured using plasma
CN1221843C (en) * 1995-10-03 2005-10-05 精工爱普生株式会社 Active matrix base plate and its producing method
JP4388648B2 (en) * 1999-10-29 2009-12-24 シャープ株式会社 Thin film transistor, liquid crystal display device, and manufacturing method thereof
KR100503128B1 (en) * 2000-09-04 2005-07-25 엘지.필립스 엘시디 주식회사 Array substrate for Liquid crystal display and method for fabricating thereof
KR100870013B1 (en) * 2002-08-27 2008-11-21 삼성전자주식회사 a thin film transistor array panel and a method for manufacturing the panel
US7532264B2 (en) * 2004-10-28 2009-05-12 Dpix Llc On-substrate ESD protection for array based image sensors

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
None
See also references of EP1751801A4

Also Published As

Publication number Publication date
CN101091257B (en) 2011-09-28
TW200610173A (en) 2006-03-16
US7217591B2 (en) 2007-05-15
TWI300992B (en) 2008-09-11
KR20070067064A (en) 2007-06-27
EP1751801A2 (en) 2007-02-14
KR101136815B1 (en) 2012-04-19
US7323372B2 (en) 2008-01-29
EP1751801A4 (en) 2011-03-02
WO2005122264A3 (en) 2007-06-28
US20050272240A1 (en) 2005-12-08
US20070184598A1 (en) 2007-08-09
CN101091257A (en) 2007-12-19

Similar Documents

Publication Publication Date Title
US6680216B2 (en) Method of making imager structure
EP2178123B1 (en) ESD induced artifact reduction design for a thin film transistor image sensor array
US7323372B2 (en) Method and process intermediate for electrostatic discharge protection in flat panel imaging detectors
US7449357B2 (en) Method for fabricating image sensor using wafer back grinding
EP1179852B1 (en) Solid state imager having gated photodiodes and method for making same
US7633091B2 (en) Structure for an image TFT array for an indirect X-ray sensor
US6093580A (en) Photosensitive imager contact
US11495629B2 (en) Photoelectric conversion apparatus and equipment
US7265327B1 (en) Photodetecting sensor array
US6617561B1 (en) Low noise and high yield data line structure for imager
US7145152B2 (en) Storage capacitor design for a solid state imager
KR100654774B1 (en) X-ray detecter and a method for fabricating the same
US20240031699A1 (en) Imaging element and imaging device
KR20020014537A (en) Image sensor formation method capable of preventing damage of spacer and field oxide and reducing floating diffusion area

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KM KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NG NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SM SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2005751054

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 200580017831.9

Country of ref document: CN

NENP Non-entry into the national phase

Ref country code: DE

WWW Wipo information: withdrawn in national office

Country of ref document: DE

WWE Wipo information: entry into national phase

Ref document number: 1020077000041

Country of ref document: KR

WWP Wipo information: published in national office

Ref document number: 2005751054

Country of ref document: EP