WO2005119760A1 - Technique de creation d'une contrainte mecanique differente dans differentes regions de canal en formant une couche d'arret d'attaque chimique ayant une contrainte intrinseque modifiee de maniere differente - Google Patents

Technique de creation d'une contrainte mecanique differente dans differentes regions de canal en formant une couche d'arret d'attaque chimique ayant une contrainte intrinseque modifiee de maniere differente Download PDF

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WO2005119760A1
WO2005119760A1 PCT/US2005/010516 US2005010516W WO2005119760A1 WO 2005119760 A1 WO2005119760 A1 WO 2005119760A1 US 2005010516 W US2005010516 W US 2005010516W WO 2005119760 A1 WO2005119760 A1 WO 2005119760A1
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Prior art keywords
layer
stress
dielectric layer
transistor
forming
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PCT/US2005/010516
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English (en)
Inventor
Kai Frohberg
Matthias Schaller
Massud Aminpur
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Advanced Micro Devices, Inc.
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Priority claimed from DE102004026149A external-priority patent/DE102004026149B4/de
Application filed by Advanced Micro Devices, Inc. filed Critical Advanced Micro Devices, Inc.
Priority to KR1020067025068A priority Critical patent/KR101134157B1/ko
Priority to GB0624048A priority patent/GB2442995B/en
Priority to JP2007515062A priority patent/JP4890448B2/ja
Publication of WO2005119760A1 publication Critical patent/WO2005119760A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer

Definitions

  • the present invention relates to the formation of integrated circuits, and, more particularly, to the formation of field effect transistors having a channel region with a specified intrinsic stress to improve the charge carrier mobility.
  • BACKGROUND ART The fabrication of integrated circuits requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout.
  • CMOS technology is currently the most promising approach due to the superior characteristics in view of operating speed and/or power consumption.
  • N-channel transistors and P-channel transistors are formed on a substrate including a crystalline semiconductor layer.
  • a MOS transistor irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely doped channel region disposed between the drain region and the source regions.
  • the conductivity of the channel region i.e., the drive current capability of the conductive channel
  • the conductivity of the channel region upon formation of a conductive channel depends on the dopant concentration, the mobility of the majority charge carriers, and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length.
  • the conductivity of the channel region substantially determines the performance of the MOS transistors.
  • the reduction of the channel length, and associated therewith the reduction of the channel resistivity renders the channel length a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
  • the shrinkage of the transistor dimensions entails a plurality of issues associated therewith that have to be addressed to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors.
  • One major problem in this respect is the development of enhanced photolithography and etch strategies to reliably and reproducibly create circuit elements of critical dimensions, such as the gate electrode of the transistors, for a new device generation.
  • epitaxially grown regions are formed with a specified offset to the gate electrode, which are referred to as raised drain and source regions, to provide an increased conductivity of the raised drain and source regions, while at the same time maintaining a shallow PN junction with respect to the gate insulation layer.
  • raised drain and source regions epitaxially grown regions are formed with a specified offset to the gate electrode, which are referred to as raised drain and source regions, to provide an increased conductivity of the raised drain and source regions, while at the same time maintaining a shallow PN junction with respect to the gate insulation layer.
  • the continuous size reduction of the critical dimensions i.e., the gate length of the transistors
  • the charge carrier mobility in the channel region for a given channel length.
  • at least two mechanisms may be used, in combination or separately, to increase the mobility of the charge carriers in the channel region.
  • the dopant concentration within the channel region may be reduced, thereby reducing scattering events for the charge carriers and thus increasing the conductivity.
  • the lattice structure in the channel region may be modified, for instance by creating tensile or compressive stress, which results in a modified mobility for electrons and holes, respectively.
  • creating tensile stress in the channel region increases the mobility of electrons, wherein, depending on the magnitude of the tensile stress, an increase in mobility of up to 20% may be obtained, which, in turn, may directly translate into a corresponding increase in the conductivity.
  • compressive stress in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors. Consequently, it has been proposed to introduce, for instance, a silicon/germanium layer or a silicon/carbon layer in or below the channel region to create tensile or compressive stress. Although the transistor performance may be considerably enhanced by the introduction of stress-creating layers in or below the channel region, significant efforts have to be made to implement the formation of corresponding stress layers into the conventional and well-approved CMOS teclmique. For instance, additional epitaxial growth techniques have to be developed and implemented into the process flow to form the germanium or carbon-containing stress layers at appropriate locations in or below the channel region.
  • the present invention is directed to a technique that enables the creation of desired stress conditions within the channel region of different transistor elements by modifying the stress characteristics of a contact etch stop layer that is formed after completion of the basic transistor structure for forming contact openings to the gate and drain and source terminals in an interlayer dielectric material.
  • a method comprises forming a dielectric layer over a first transistor element and a second transistor element, wherein the dielectric layer has a first specified intrinsic mechanical stress. Moreover, a mask layer is formed above the first and second transistor elements to expose a first portion of the dielectric layer formed above the first transistor element and to cover a second portion of the dielectric layer formed above the second transistor element.
  • a method comprises forming a first dielectric layer over a first transistor element and a second transistor element, wherein the first dielectric layer has a first specified intrinsic mechanical stress. Furthermore, a first portion of the first dielectric layer formed over the first transistor element is selectively removed. Additionally, a second dielectric layer is formed over the first transistor element and a second portion of the first dielectric layer formed above the second transistor element, wherein the second dielectric layer has a second intrinsic stress that differs from the first intrinsic stress.
  • a semiconductor device comprises a first transistor element having a first channel region and a first dielectric layer enclosing the first transistor element, wherein the first dielectric layer induces a first stress in the first channel region.
  • the semiconductor device comprises a second transistor element having a second channel region and a second dielectric layer, wherein the second dielectric layer encloses the second transistor element and induces a second stress in the second channel region, whereby the second stress differs from the first stress.
  • Figures la-lg schematically show cross-sectional views of a semiconductor device including two transistor elements at various manufacturing stages, wherein the intrinsic mechanical stress of a contact etch stop layer is modified by means of a treatment with non-reactive ions in accordance with illustrative embodiments of the present invention
  • Figures 2a-2j schematically show cross-sectional views of a semiconductor device including two different transistor elements, wherein the intrinsic stress of the contact etch stop layer is modified by a treatment with non-reactive ions in accordance with further illustrative embodiments of the present invention
  • Figures 3a-3g schematically show cross-sectional views of a semiconductor device including two different transistor types, which receive correspondingly designed contact etch stop layers by selectively removing portions thereof by means of dry etch techniques in accordance with further illustrative embodiments of the
  • the present invention is based on the concept that effective stress engineering in the channel region of different transistor types may efficiently be accomplished by modifying the intrinsic stress of a dielectric layer that is in contact with the transistor structure or that is at least located in the vicinity of the transistor structure.
  • the modification of the intrinsic stress of the dielectric layer may be accomplished by adjusting process parameters and/or by a treatment with non-reactive ions. Since the dielectric layer located above the transistor structure, which may also be used, at least partially, as a contact etch stop layer, covers a large area of the transistor structure, the mechanical coupling to the transistor structure enables effective stress engineering within the channel region without requiring significant modifications during the transistor formation process.
  • the present invention enables the modification or formation of corresponding dielectric layers with different stress characteristics at different die locations or even at different dies within the substrate.
  • the present invention enables the formation of different stress inducing dielectric layers at transistor elements that are arranged in close proximity, such as complementary transistor pairs of a CMOS device, thereby providing the potential for enhancing the overall performance of even complex CMOS devices, such as CPUs, memory chips, and the like.
  • CMOS devices such as CPUs, memory chips, and the like.
  • process non-uniformities resulting in a deviation of electrical characteristics of devices located at different positions of a wafer, or deviations in devices formed on different wafers may be reduced or compensated for by selectively adapting the stress level at different wafers or wafer positions, wherein the stress adaptation takes place at the transistor level, i.e., in the channel regions of the involved transistor devices and therefore renders the stress engineering highly efficient.
  • the stress-induced problems become more relevant with increasing shrinkage of feature sizes, and hence the present invention is particularly advantageous in combination with highly scaled semiconductor devices, thereby providing the prospect for further device scaling without substantial loss of performance caused by stress-induced problems.
  • Figure la schematically shows a cross-sectional view of a semiconductor device 150 comprising a first transistor element lOOn and a second transistor element lOOp.
  • the transistor elements lOOn, lOOp may represent different types of transistor elements, such as an N-channel transistor and a P-channel transistor, or transistors of the same or different types located at different die locations or substrate locations, and, in particular embodiments, the transistors lOOn may represent an N-channel transistor and the second transistors lOOp may represent a P-channel transistor, both of which are arranged to form a complementary transistor pair.
  • transistors lOOn and lOOp may differ from each other in size, conductivity type, location, function, and the like, for convenience, the transistors shown have substantially the same configuration, and hence corresponding components of the transistors lOOn and lOOp are denoted by the same reference numerals.
  • the present invention is particularly advantageous for transistor elements without any stress-inducing components, such as additional epitaxy layers formed in or below the respective channel regions, the present invention may also be combined with such additional stress- creating techniques.
  • transistor elements provided in the form of silicon-on- insulator (SOI) devices without any raised drain and source regions SOI
  • the semiconductor device 150 comprises a substrate 101 having formed thereon an insulating layer 102, such as a buried silicon dioxide layer, silicon nitride layer, and the like, followed by a crystalline semiconductor layer 103, which will be referred to as "silicon layer" in the following description, since the vast majority of integrated circuits including complex logic circuits is based on silicon. It should be appreciated, however, that the semiconductor layer 103 may be comprised of any appropriate semiconductor material in conformity with design requirements.
  • the first and second transistors lOOn, lOOp may be separated from each other by an isolation structure 120, for instance, in the form of a shallow trench isolation.
  • the first transistor lOOn further comprises a gate electrode structure 105 including a semiconductor portion 106, such as a polysihcon portion, and a metal-containing portion 108, for instance provided in the form of a metal suicide.
  • the gate electrode structure 105 further comprises a gate insulation layer 107 separating the gate electrode structure 105 from a channel region 104, which, in turn, laterally separates appropriately doped source and drain regions 111 having formed therein metal suicide regions 112.
  • a spacer element 110 is formed adjacent the sidewalls of the gate electrode structure 105 and is separated therefrom by a liner 109, which is also formed between the source and drain regions 111 and the spacer element 110. In some cases, the liner 109 may be omitted.
  • the second transistor lOOp may have substantially the same configuration and the same components, wherein the channel region 104 and the drain and source regions 111 may include different dopants compared to the respective regions of the transistor lOOn, when the first and second transistors lOOn, lOOp represent transistor elements of a different conductivity type.
  • a typical process flow for forming the semiconductor device 150 as shown in Figure la may comprise the following processes.
  • the substrate 101, the insulating layer 102, and the semiconductor layer 103 may be formed by advanced wafer bond techniques when the semiconductor device 150 is to represent an SOI device, or the substrate 101 may be provided without the insulating layer 102, as a bulk semiconductor substrate, wherein the semiconductor layer 103 may represent an upper portion of the substrate, or may be formed by epitaxial growth techniques.
  • the gate insulation layer 107 may be deposited and/or formed by oxidation in accordance with well-established process techniques followed by the deposition of a gate electrode material, such as polysihcon, by means of low pressure chemical vapor deposition (LPCVD).
  • LPCVD low pressure chemical vapor deposition
  • the gate electrode material and the gate insulation layer 107 may be patterned by sophisticated photolithography and etch techniques in accordance with well-established process recipes.
  • the spacer element 110 may be formed as two or more different spacer elements with intermediate implantation processes when a sophisticated laterally profiled dopant concentration is required for the drain and source regions 111. For example, extension regions of reduced penetration depth may be required.
  • the metal suicide regions 108 and 112 are formed by depositing a refractory metal and initiating a chemical reaction with the underlying silicon, wherein the spacer element 110 acts as a reaction mask for preventing or reducing the formation of the metal compound between the gate electrode structure 105 and the drain and source regions 111.
  • Figure lb schematically shows the semiconductor device 150 with a first dielectric layer 116 formed above the transistor elements lOOn and lOOp.
  • the transistor elements lOOn, lOOp are embedded in an interlayer dielectric material (not shown in Figure lb) over which corresponding metallization layers are to be formed to establish the required electrical connections between the individual circuit elements.
  • the interlayer dielectric material has to be patterned to provide contacts to the gate electrode structure 105 and the drain and source regions 111 by means of an anisotropic etch process.
  • the first dielectric layer 116 is designed to also act, at least partially, as an etch stop layer for a contact etch and may therefore also be referred to as contact etch stop layer.
  • the interlayer dielectric material is comprised of silicon dioxide and thus the first dielectric layer 116 may comprise silicon nitride, as silicon nitride exhibits a good etch selectivity for well-established anisotropic process recipes for etching silicon dioxide.
  • silicon nitride may be deposited in accordance with well-established deposition recipes, wherein the deposition parameters may be adjusted to provide a specified intrinsic mechanical stress while at the same time still maintaining the desired high etch selectivity to silicon dioxide.
  • silicon nitride is deposited by plasma enhanced chemical vapor deposition (PECVD), wherein, for example, parameters of the plasma atmosphere, such as the bias power supplied to the plasma atmosphere, may be varied to adjust the mechanical stress created in the silicon nitride layer as deposited.
  • PECVD plasma enhanced chemical vapor deposition
  • the deposition may be performed on the basis of well-established process recipes on the basis of silane (SiH ) and ammonia (NH 3 ), nitrogen oxide (N 2 0) or nitrogen (N 2 ) in a deposition tool for PECVD for a silicon nitride layer.
  • the stress in the silicon nitride layer may be determined by the deposition conditions, wherein, for instance, a compressive stress in silicon nitride of approximately 150 MPa may be obtained with a moderately high bias power according to well-established deposition recipes, while in other embodiments a tensile stress of approximately 0-1000 MPa may be achieved.
  • the stress created in the silicon nitride during the deposition depends on the gas mixture, the deposition rate, the temperature and the ion bombardment.
  • the corresponding amount of tensile or compressive stress in the layer may be adjusted by, for instance, varying any of these process parameters determining the plasma atmosphere during the deposition of the layer by PECVD.
  • the bias energy supplied to the plasma atmosphere may be varied to adjust the degree of ion bombardment during the deposition process, thereby creating tensile or compressive stress in the silicon nitride layer.
  • dual frequency CVD reactors are usually used to adjust a desired amount of bias power.
  • the first dielectric layer 116 may be deposited as a silicon nitride layer having a specified compressive stress.
  • FIG. lc schematically shows the semiconductor device 150 with a resist mask 140 formed thereon, wherein the resist mask 140 exposes the first transistor element lOOn and covers the second transistor element lOOp.
  • the resist mask 140 may be formed in accordance with photolithography masks also required for the formation of P- and N-type transistors, and thus the formation of the resist mask 140 may be readily incorporated into the conventional process flow.
  • the semiconductor device 150 is subjected to a treatment 160 with non-reactive ions, including, for instance, xenon, germanium, and the like, when the treatment 160 is performed as an ion implantation sequence. Due to the ion bombardment, the molecular structure of a first portion 116n of the layer 116 is modified to significantly reduce the intrinsic stress within the first portion 116n of the layer 116.
  • the process parameters of the treatment 160 when performed as an ion implantation process may be selected in accordance with a layer thickness of the first dielectric layer 116 and the type of ion species used. For instance, a dose of approximately 10 15 -10 16 ions/cm 2 may be used at an implantation energy of approximately 10-100 keV for a layer thickness of approximately 50-100 nm for the above-specified ion species. However, relevant parameter values may readily be determined by simulation.
  • the treatment 160 may be performed in a plasma atmosphere on the basis of inert gases such as argon, helium, and the like, which show a higher penetration depth at lower acceleration energies, thereby also rendering the ion energies created in a plasma atmosphere appropriate for relaxing the intrinsic stress in the portion 116n.
  • An appropriate plasma atmosphere may be generated in any appropriate plasma etch or plasma deposition tool.
  • Figure Id schematically shows the semiconductor device 150 after completion of the ion bombardment 160 with a stress-reduced or a substantially stress-free portion 116n, depending on the design requirements, provided over the first transistor lOOn and with a portion 116p still having the compressive stress of the initially deposited dielectric layer 116.
  • the reduced intrinsic stress of the first portion 116n or the significantly reduced compressive stress may be considered appropriate for achieving the desired modification of the electrical behavior of the channel region 104 of the first transistor lOOn to achieve a substantially symmetrical behavior of the first and second transistors lOOn, lOOp, and the further processing of the semiconductor device 150 may be continued by depositing an interlayer dielectric material, such as silicon dioxide, and forming corresponding contact openings while using the first and second portions 116n, 116p as etch stop layers.
  • Figure le shows the semiconductor device 150 in accordance with further illustrative embodiments when a more pronounced modification of the stress condition in the channel region 104 of the first transistor lOOn is desired.
  • a tensile stress within the channel region 104 may provide enhanced mobility of electrons. Therefore, a second dielectric layer 117 may be formed over the first and second transistors lOOn, lOOp having an intrinsic stress as is desired for the first transistor lOOn. For example, the dielectric layer 117 may be deposited to exhibit an intrinsic tensile stress of a specified magnitude. In some embodiments, the compressive stress in the second portion 116p may be selected to significantly overcompensate the tensile stress induced by the second dielectric layer 117 to achieve a desired total stress within the channel region 104 of the second transistor lOOp, e.g., a compressive stress condition.
  • the partial compensation of the compressive stress of the second portion 116p by the tensile stress of the dielectric layer 117 may be considered inappropriate and hence the intrinsic stress created by the dielectric layer 117 over the second transistor lOOp may be modified, for instance by a treatment similar to the treatment 160, or in other embodiments the portion of the layer 117 over the second transistor lOOp may be removed.
  • the second transistor lOOp is subjected to a plasma etch process 180 to remove the exposed portion of the layer 117.
  • the dielectric layer 117 may comprise a thin liner (not shown) formed on the first dielectric layer 116 to provide an indication when the etch front of the plasma etch process 180 approximately reaches the second portion 116p of the layer 116, or the liner may act as an etch stop layer.
  • Figure lg schematically shows the semiconductor device 150 after removal of the exposed portion of the layer 117 and after removal of the resist mask 170. Hence, a stress created in the channel region 104 of the first transistor lOOn is substantially determined by the second dielectric layer 117, while the stress in the channel region 104 of the second transistor lOOp is substantially determined by the second portion 116p.
  • the type and magnitude of the intrinsic stress in the first dielectric layer 116 and the second dielectric layer 117 may be selected in accordance with design requirements and may not necessarily be selected in the way described above.
  • the plasma etch process 180 shown in Figure If may be replaced by an ion bombardment, similar to the ion bombardment 160 in Figure lc, to reduce or relax the stress in the exposed portion of the dielectric layer 117 without removing the same.
  • the degree of stress relaxation may appropriately be controlled to achieve the desired total induced stress in the channel region 104 of the second transistor lOOp.
  • a substantially equivalent layer thickness for the layers 116 and 117 above the first and second transistor element lOOn, lOOp may be obtained, thereby providing for substantially identical etch conditions during a subsequent contact opening etch.
  • advantageously a tensile stress in N-transistors and a compressive stress in P-transistors is generated.
  • any other combination of stress may be created.
  • more than two different stress levels at more than two different substrate positions may be obtained.
  • the ion bombardment 160 may be performed in several steps possibly with varying parameters, wherein each step is carried out with a different resist mask 140.
  • a semiconductor device 250 comprises a first transistor element 200n and a second transistor element 200p.
  • the configuration of the first and second transistors 200n and 200p may be the same as described with reference to Figure la, and hence the same reference numerals are used, except for a leading "2" instead of a leading "1.” Therefore, a detailed description of these components is omitted.
  • Figure 2b schematically shows the semiconductor device 250 having formed thereon a first dielectric layer 216, which may comprise a first liner 216a, a stress-inducing layer 216b, and a second liner 216c.
  • the liners 216a and 216c may be formed of silicon dioxide, while the stress-inducing layer 216b may be comprised of silicon nitride. Deposition recipes for silicon dioxide are well established in the art and may therefore be readily applied to the formation of the liners 216a and 216c. Concerning the formation of the stress-inducing layer 216b, the same criteria apply as previously explained with reference to the dielectric layer 116 in Figure lb.
  • the stress-inducing layer 216b comprises compressive stress, which may be transferred to the second transistor element 200p, while the first transistor 200n is to receive a tensile stress.
  • the stress-inducing layer 216b may have tensile stress.
  • Figure 2c schematically shows the semiconductor device 250 with a resist mask 240 formed thereon, which covers the second transistor 200p and exposes the first transistor 200n. Furthermore, the semiconductor device 250 is subjected to a wet chemical etch process 260 to remove the exposed portion of the liner 216c.
  • the wet chemical etch process is based on diluted hydrofluoric acid (HF), which attacks the silicon dioxide of the liner 216c while having a significantly reduced etch rate for the resist mask 240.
  • HF diluted hydrofluoric acid
  • FIG 2d schematically shows the semiconductor device 250 after removal of the exposed portion of the liner 216c and after removal of the resist mask 240.
  • the second transistor element 200p is still covered by the liner 216c, while the stress-inducing layer 216b is exposed over the first transistor 200n.
  • the semiconductor device 250 is subjected to a further wet chemical etch process 261, which may be designed to selectively remove the stress-inducing layer 216b while substantially not attacking the liners 216a and 216c.
  • the stress-inducing layer 216b may be comprised of silicon nitride, and hence the etch chemistry may be based on hot phosphoric acid (H 3 P0 4 ), which exhibits an excellent etch selectivity with respect to silicon dioxide. Consequently, the stress-inducing layer 216b over the second transistor element 200p is maintained, except for minor under-etch areas (not shown), whereas the stress- inducing layer 216b over the first transistor element 200n is substantially completely removed.
  • Figure 2f schematically shows the semiconductor device 250 with a further resist mask 241 formed thereon that covers the first transistor element 200n while exposing the second transistor element 200p. Furthermore, the semiconductor device 250 is subjected to a further wet chemical etch process 262 to remove the exposed liner 216c over the second transistor element 200p. Similar to the etch process 260, the process 262 may be based on HF if the liner 216c is comprised of silicon dioxide, whereas the liner 216a on the first transistor 200n is protected by the resist mask 241.
  • Figure 2g schematically shows the semiconductor device 250 after completion of the wet chemical etch process 262 and after the removal of the resist mask 241.
  • the second transistor 200p has the exposed stress-inducing layer 216b formed thereon, while the first transistor 200n is still covered by the liner 216a.
  • a further dielectric layer having an intrinsic stress other than the intrinsic stress of the stress-inducing layer 216b may be deposited.
  • Figure 2h shows the semiconductor device 250 having formed thereon a second dielectric layer 217 with a specified intrinsic stress, such as a tensile stress, formed over the first and second transistor elements 200n, 200p.
  • layer characteristics such as layer thickness, material composition, etc., the same criteria apply as previously explained with reference to the layers 116, 117 and 216b.
  • the second dielectric layer 217 may be comprised of silicon nitride with a layer thickness that is appropriate for serving as a contact etch stop layer in subsequent manufacturing processes.
  • Figure 2i schematically shows the semiconductor device 250 having formed thereon a further resist mask 242, which covers the first transistor element 200n while exposing the second transistor element 200p. Since the stress induced in the channel region 204 of the second transistor element 200p is currently determined, at least in part, by the stress-inducing layer 216b and the dielectric layer 217, the second transistor 200p may, in accordance with one embodiment, be subjected to a treatment 263 for relaxing or reducing the intrinsic stress in the layer 217.
  • a treatment with non-reactive ions by means of an ion implantation on the basis of, for instance, xenon, germanium, and the like, may be performed, or a plasma treatment on the basis of argon, helium, and the like may be employed.
  • the process parameters of the treatment 263 may be selected on the basis of the desired total stress in the channel region 204 of the second transistor 200p and in conformity with the characteristics of the dielectric layer 217, such as layer thickness, material composition, and the like. Corresponding process recipes and process parameters may be readily established, for instance on the basis of test runs, simulation and the like.
  • the degree of stress relaxation and the position of the stress relaxation may be controlled during the treatment 263 by carrying out two or more steps with different resist masks 242 and with different process parameters.
  • the influence of the dielectric layer 217 on the stress induced in the channel region 204 of the second transistor element 200p may be avoided by removing the exposed portion of the layer 217 by a plasma etch process, wherein, advantageously, the liner 216c is not removed (see Figure 2f), and may therefore be used as an efficient etch stop layer or etch indicator layer during the plasma etch process to reliably control the removal of the exposed portion of the layer 217.
  • the stress in the channel region 204 of the second transistor 200p is substantially determined by the stress-inducing layer 216b, while the stress in the first transistor element 200n is substantially created by the remaining dielectric layer 217.
  • the exposed portion of the layer 217 is substantially relaxed, or the stress therein is significantly reduced, or adjusted to a desired level.
  • Figure 2j schematically shows the semiconductor device 250 after completion of the treatment 263 and the removal of the resist mask 242, thereby leaving a low stress layer 217p, which does not significantly contribute to the total stress of the second transistor element 200p.
  • Further processing may be continued by depositing an interlayer dielectric material, such as silicon dioxide, over the semiconductor device 250 and forming respective contact openings by using the layers 216b and 217, on the one hand, and the layer 217, on the other hand, as etch stop layers.
  • an interlayer dielectric material such as silicon dioxide
  • FIG. 3a schematically shows in cross-section a semiconductor device 350, including a first transistor element 300n and a second transistor element 300p, which may have the configuration as described with reference to Figures la and 2a.
  • FIG. 3b schematically shows the semiconductor device 350 having formed thereon a dielectric layer 316, which may comprise a stress-inducing layer 316b, for instance formed from silicon nitride, and a liner 316c, for instance formed from silicon dioxide.
  • a dielectric layer 316 which may comprise a stress-inducing layer 316b, for instance formed from silicon nitride, and a liner 316c, for instance formed from silicon dioxide.
  • the same criteria apply as previously outlined with reference to the liners 216a, 216c and the stress-inducing layer 216b.
  • the stress-inducing layer 316b may comprise compressive stress, which may be transferred to the second transistor element 300p while a tensile stress is to be created in the first transistor element 300n.
  • Figure 3c schematically shows the semiconductor device 350 with a resist mask 340 formed thereon, which covers the second transistor element 300p and exposes the first transistor element 300n. Furthermore, the semiconductor device 350 is subjected to a plasma etch process 360 to remove the exposed portions of the liner 316a and the stress-inducing layer 316b.
  • Corresponding plasma etch recipes are well established in the art and process parameters may be used as are also employed during the formation of the spacer elements 310.
  • Figure 3d schematically shows the semiconductor device 350 after completion of the plasma etch process 360 and after removal of the resist mask 340, thereby leaving the second transistor 300p with the stress- inducing layer 316b and the liner 316c, while the first transistor 3 OOn is subsequently completely exposed.
  • Figure 3e schematically shows the semiconductor device 350 having formed thereon a second dielectric layer 317 with a specified intrinsic stress, such as a tensile stress that is to be transferred to the channel region 304 of the first transistor element 300n.
  • a specified intrinsic stress such as a tensile stress that is to be transferred to the channel region 304 of the first transistor element 300n.
  • Figure 3f schematically shows the semiconductor device 350 with a further resist mask 341 formed thereon, which covers the first transistor element 3 OOn while exposing the second transistor element 300p. Furthermore, the semiconductor device 350 is exposed to a plasma etch atmosphere 361 to remove the exposed portion of the dielectric layer 317.
  • Corresponding etch recipes are well established, for instance in the form of recipes as are used during the formation of the spacer element 310.
  • the liner 316c acts as an etch stop layer or an etch indicator layer, thereby enabling reliable control of the etch process 361.
  • any remaining parts of the liner 316c that have not been consumed by the etch process 361 may, according to some embodiments, be removed by, for instance, a wet chemical etch process on the basis of HF. Thereafter, the resist mask 341 may be removed.
  • Figure 3g schematically shows the semiconductor device 350 with the layer 316b inducing, for instance, compressive stress in the channel region 304 of the second transistor 300p and with the remaining layer 317 inducing, for instance, tensile stress in the channel region 304 of the first transistor element 3 OOn.
  • further processing of the semiconductor device 350 may continue with the deposition of an interlayer dielectric material 380, for instance in the form of silicon dioxide, and with the forming of contact openings 381, wherein the stress-inducing layers 317 and 316b may effectively be used as etch stop layers during the anisotropic etch process.
  • the present invention provides a technique that enables the formation of stress-inducing dielectric layers that are in direct contact with transistor structures, or that are located in close proximity above the transistor structures, wherein conventional and well-approved processes such as wet chemical etch processes, plasma etch processes, ion implantation or plasma treatment processes may be employed to provide different types of stress-inducing layers at different locations.
  • the stress-determining parameters are well controllable and allow efficient stress engineering.
  • the stress induced in respective channel regions of transistor elements may be substantially controlled by the dielectric layer, which may also act as a contact etch stop layer, thereby also significantly facilitating the stress engineering, since the stress is substantially determined by a single, well-controllable component rather than by two or more components, such as sidewall spacers in combination with contact etch stop layers.
  • the illustrative embodiments described with reference to the drawings may be combined or certain process steps may be replaced by process steps of other embodiments in any appropriate fashion.

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Abstract

Une couche d'arrêt d'attaque chimique par contact (116) permet de contrôler efficacement la contrainte dans des régions de canal de différents types de transistor (100N, 100P) où l'on peut obtenir des portions de contrainte de traction et de compression de la couche d'arrêt d'attaque chimique par contact (116) grâce à des processus bien établis, comme l'attaque chimique humide, l'attaque chimique au plasma, l'implantation ionique, le traitement au plasma et similaire. On peut ainsi obtenir une amélioration significative des performances du transistor (100N, 100P) sans contribuer notablement à la complexité du processus.
PCT/US2005/010516 2004-05-28 2005-03-29 Technique de creation d'une contrainte mecanique differente dans differentes regions de canal en formant une couche d'arret d'attaque chimique ayant une contrainte intrinseque modifiee de maniere differente WO2005119760A1 (fr)

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KR1020067025068A KR101134157B1 (ko) 2004-05-28 2005-03-29 차등적으로 변형된 진성 응력을 가지는 식각 정지층을 형성함으로써 차등 채널 영역들 내에 차등적인 기계적 응력을 생성하는 기술
GB0624048A GB2442995B (en) 2004-05-28 2005-03-29 Technique for creating different mechanical stress in different channel regions by forming an etch stop layer having differently modified intrinsic stress
JP2007515062A JP4890448B2 (ja) 2004-05-28 2005-03-29 相異なるチャネル領域に相異なるよう調整された内在応力を有するエッチストップ層を形成することによって、相異なる機械的応力を生成するための技術

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DE102004026149A DE102004026149B4 (de) 2004-05-28 2004-05-28 Verfahren zum Erzeugen eines Halbleiterbauelements mit Transistorelementen mit spannungsinduzierenden Ätzstoppschichten
DE102004026149.0 2004-05-28
US11/058,035 2005-02-15
US11/058,035 US7517816B2 (en) 2004-05-28 2005-02-15 Technique for creating different mechanical stress in different channel regions by forming an etch stop layer having differently modified intrinsic stress

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US8828815B2 (en) 2007-02-13 2014-09-09 United Microelectronics Corp. Method for fabricating strained-silicon CMOS transistor

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