WO2005119757A2 - Packaged integrated circuit devices - Google Patents

Packaged integrated circuit devices Download PDF

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Publication number
WO2005119757A2
WO2005119757A2 PCT/IB2005/001591 IB2005001591W WO2005119757A2 WO 2005119757 A2 WO2005119757 A2 WO 2005119757A2 IB 2005001591 W IB2005001591 W IB 2005001591W WO 2005119757 A2 WO2005119757 A2 WO 2005119757A2
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuit
inteφoser
gel
lead frame
top surface
Prior art date
Application number
PCT/IB2005/001591
Other languages
French (fr)
Other versions
WO2005119757A3 (en
Inventor
Appolonius Jacobus Van Der Wiel
Jian Chen
Original Assignee
Melexis Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Melexis Nv filed Critical Melexis Nv
Priority to EP05748165A priority Critical patent/EP1751793A2/en
Priority to JP2007514204A priority patent/JP2008502130A/en
Publication of WO2005119757A2 publication Critical patent/WO2005119757A2/en
Publication of WO2005119757A3 publication Critical patent/WO2005119757A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49531—Additional leads the additional leads being a wiring board
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
    • B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
    • B29C33/00—Moulds or cores; Details thereof or accessories therefor
    • B29C33/02—Moulds or cores; Details thereof or accessories therefor with incorporated heating or cooling means
    • B29C33/06—Moulds or cores; Details thereof or accessories therefor with incorporated heating or cooling means using radiation, e.g. electro-magnetic waves, induction heating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14618—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates in general to packaged integrated circuit devices and to methods of encapsulating such devices in a protective package, and in particular to packaged integrated circuit sensor and/or emitter devices and to methods of encapsulating such devices in a protective package.
  • Integrated circuit sensor or emitter devices comprise integrated circuits incorporating an active element adapted to detect pressure, motion, or other physical parameter or to detect and or emit radiation (at visible, infrared or ultraviolet wavelengths).
  • the integrated circuit is encapsulated in a protective package, said package being adapted such that the integrated circuit may be electrically connected to external circuitry and such that the sensing element may be exposed to the external environment.
  • the active element should not be obscured by the package or damaged by the encapsulation process.
  • Conventional low cost encapsulation methods involve mounting the integrated circuit on a lead frame and inserting the integrated circuit and lead frame in to the cavity of a moulding tool. A suitable moulding compound is then injected into the cavity to wholly encapsulate the integrated circuit at pressures in the range of 20 to 80 bar. A number of techniques may be used to ensure that the active element may still be exposed to the external environment.
  • gel is applied to the active element before the integrated circuit is inserted into the moulding tool and the moulding tool is adapted such that the side of the moulding tool or a projection from the side of the moulding tool is in contact with the gel during the encapsulation process.
  • a passageway is provided between the active element and the exterior of the package through which the active element may be exposed to external environment.
  • the gel may be removed once the encapsulation process is complete.
  • the volume and placement of the dispensed gel is critical in these methods as this defines the area of the integrated circuit that will remain exposed.
  • Use of too little gel can result in plastic moulding compound contaminating or obscuring the active element, reducing or even destroying its operating capability.
  • use of too much gel can leave an overly large void in the package after encapsulation thus making failure of the package more likely.
  • the gel is removed after encapsulation, then exposure of additional components of the integrated circuit to the external environment can make circuitry failures more likely also. Uneven distribution of the gel can cause either or both of the above problems.
  • a method of encapsulating an integrated circuit device within a package comprising the steps of: providing an integrated circuit incorporating at least one active element on a top surface of said integrated circuit; providing an inte ⁇ oser incorporating electrical contacts, said interposer having a substantially equal coefficient of thermal expansion to the integrated circuit; electrically connecting said integrated circuit to said inte ⁇ oser; mounting said inte ⁇ oser on a lead frame; mounting said integrated circuit on to a top surface of said inte ⁇ oser to form an assembly; electrically connecting said inte ⁇ oser to said lead frame; dispensing a quantity of gel onto said integrated circuit so as to cover the top surface of said integrated circuit and the top surface of said silicon inte ⁇ oser, thereby forming a gel coated assembly; inserting the assembly into a cavity of a moulding tool, said moulding tool having a projection on one surface of the tool adapted to make contact with said gel; introducing a moulding compound into the cavity so as to encapsulate the assembly except for
  • the inte ⁇ oser is mounted on the lead frame before the integrated circuit is mounted on the inte ⁇ oser. This allows both mounting steps to be carried out using conventional die attach technology.
  • the moulding compound is injected in to the cavity to encapsulate the integrated circuit at pressures in the range of 20 to 80 bar.
  • the active element may be a sensing element or an emitting element. If the active element is a sensing element it is preferably a sensing element adapted for detecting one or more of pressure, motion temperature or radiation (at visible, infra red or ultra violet wavelengths). If desired, the device may comprise two or more sensing elements, each sensing element operable to sense the same and/or similar and/or different physical parameters. If the active element is an emitting element it is preferably a radiation emitting element (at visible, infra red or ultra violet wavelengths). In some preferred embodiments, the active elements may comprise a radiation sensing element and a radiation emitting element. In such embodiments, the emitting element and the sensing element may be adapted to operate at similar or different wavelengths as desired.
  • said gel covers substantially the whole top surfaces of both said inte ⁇ oser and said integrated circuit.
  • said gel is prevented from covering areas other than the top surfaces of said inte ⁇ oser and said integrated circuit by controlling the volume of gel dispensed.
  • said gel has sufficient surface tension to stop flowing when it reaches the edges of said inte ⁇ oser.
  • the inte ⁇ oser is a silicon inte ⁇ oser.
  • said integrated circuit is provided on a silicon wafer.
  • Said integrated circuit may be mounted onto said inte ⁇ oser by any suitable means, such as Flip-Chip mounting or any other suitable method.
  • said integrated circuit is electrically connected to said inte ⁇ oser by means of wires linking bond pads provided on the top surface of said inte ⁇ oser with bond pads provided on the top surface of said integrated circuit.
  • said integrated circuit may be provided with vias extending through to the bottom surface of said integrated circuit and adapted to be electrically connected to suitable formations provided on the top surface of said inte ⁇ oser.
  • said inte ⁇ oser is electrically connected to the periphery of said lead frame by means of wires linking bond pads provide on the top surface of said inte ⁇ oser with the periphery of the lead frame.
  • a pattern of electrical connections is provided on the upper surface of said inte ⁇ oser.
  • said connections run between bond pads connecting said inte ⁇ oser to said integrated circuit and bond pads connecting said inte ⁇ oser to said lead frame.
  • said inte ⁇ oser may additionally provide electronic circuitry means to interface between said integrated circuit and external processing means.
  • the integrated circuit is one of a plurality of similar integrated circuits formed on a single wafer. Most preferably said integrated circuits are formed in an array on said wafer, such as a rectangular or square array. Preferably, the wafer is then diced or sawn to separate the individual integrated circuits in the array. The individual integrated circuits are preferably then packaged according to the method described above.
  • a packaged integrated circuit device manufactured in accordance with the method of the first aspect of the invention.
  • the packaged integrated circuit device according to the second aspect of the present invention may inco ⁇ orate any of the features of the first aspect of the invention as desired or appropriate.
  • an integrated circuit device 100 comprises an integrated circuit 104 encapsulated in a protective package 108.
  • the integrated circuit 104 inco ⁇ orates at least one active element, which may be a sensing element responsive to an external stimulus such as radiation, pressure, temperature or similar; or a radiation emitting means.
  • the package is adapted to expose the active element to the external environment, whilst protecting the rest of integrated circuit 104.
  • a gel blob 107 is provided over the top surface of integrated circuit 104. This provides some measure of protection for the integrated circuit whilst still allowing the active element to operate. For instance if the active element was a radiation sensing or emitting element and the gel 107 was a transparent gel the operation of the radiation sensing or emitting element would not be adversely effected by the presence of the gel 107. Similarly, a pressure sensing element will still operate effectively as atmospheric pressure will be transferred through the gel. The blob of gel 107, may of course be removed if required or desired.
  • the integrated circuit 104 is mounted on and electrically connected to an inte ⁇ oser 103.
  • the inte ⁇ oser 103 has a substantially identical coefficient of thermal expansion to the integrated circuit 104.
  • the integrated circuit 104 is provided on a silicon wafer and likewise, the inte ⁇ oser 103 is a silicon wafer.
  • Electrical connections between the integrated circuit 104 and the inte ⁇ oser 103 are made by means of wires 106 linking bond pads provided on the top surface of the integrated circuit 104 to bond pads provided on the top surface of the inte ⁇ oser 103.
  • vias may be provided through the wafer upon which the integrated circuit 104 is provided allowing electrical connections to be made between the integrated circuit 104 and the inte ⁇ oser 103.
  • the inte ⁇ oser 103 is in turn mounted on and electrically connected to a lead frame 102. Electrical connections are made by wires 105 between bond pads provided on the top surface of the inte ⁇ oser 103 and peripheral portions 101 of the lead frame 102. A pattern of electrical connections is provided on the upper surface of the inte ⁇ oser 103, the electrical connections running between bond pads provided for electrically connecting the inte ⁇ oser 103 to the integrated circuit 104 and bond pads provided for electrically connecting the inte ⁇ oser 103 to the peripheral portions 101 of lead frame 102. In some embodiments, the inte ⁇ oser 103 may additionally inco ⁇ orate interface or processing circuitry.
  • the gel blob 107 covers the entire top surface of the inte ⁇ oser 103 and the entire top surface of the integrated circuit 104.
  • the protective package 108 encapsulates the whole of the device other than the ends of the peripheral portions 101 of the lead frame 102 and part of the top surface of the gel blob 107. In this manner the device can be encapsulated within a protective package without the integrated circuit 104 being in direct contact with the moulding compound 108. This reduces the adverse effects of stress or strain resulting from the different coefficients of thermal expansion of the integrated circuit 104 and the moulding compound 108.
  • the device 100 is manufactured according to the following process.
  • the inte ⁇ oser 103 is glued to the lead frame then the integrated circuit 104 is mounted onto the inte ⁇ oser 103.
  • the integrated circuit is then electrically connected to the inte ⁇ oser 103 by means of bond wires 106 and the inte ⁇ oser 103 is electrically connected to the peripheral portions 101 of the lead frame 102 by means of bond wires 105.
  • an alternative to a lead frame may be used such as an organic BGA substrate.
  • the integrated circuit 104 is one of an array of like integrated circuits formed on a single wafer, individual integrated circuits being separated from the array by suitable cuts.
  • the electrical connections from the inte ⁇ oser 103 to the peripheral portions or leads 101 of the lead frame 102 can be made before or after the inte ⁇ oser 103 is mounted on to the lead frame 102.
  • the blob of gel 107 is dispensed onto the top surface of said integrated circuit 104 so as to cover the top surface of both said integrated circuit 104 and also the top surface of said inte ⁇ oser 103 to form a gel covered assembly.
  • the quantity of gel dispensed is limited to restrain the gel from spreading any further than the edge 109 of the inte ⁇ oser 103. Gel dispersion is also limited by the surface tension of the gel 107.
  • the lead frame 102, inte ⁇ oser 103, integrated circuit 104 and gel blob 107 with all bond wires 105 and 106 are inserted into the cavity of a mould tool. Said cavity is provided with a projection on its inner surface that is adapted to make contact with said gel blob 107.
  • Plastic moulding compound 108 is then injected into the mould cavity to encapsulate the device in a protective package. After the packaged device is removed from the moulding tool, the gel 107 may be removed or retained as desired. The gel 107 may be removed, for example to allow radiation to pass between the active element and the exterior of the package with less attenuation or distortion.
  • the gel 107 may be retained for protection whilst transmitting radiation or pressure to the active element of the integrated circuit 104.
  • the projection of the moulding tool may be adapted to form the upper surface of the gel 107 into a desired shape. This may be used to provide a lens to focus incident on a radiation sensing element or to focus radiation emitted by an emitting element into a collimated beam.
  • the gel 107 being flexible does not provide significant strain on the integrated circuit 104 if changes in temperature do occur.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

An integrated circuit device (100) comprises an integrated circuit (104) encapsulated in a protective package (108). The integrated circuit (104) incorporates at least one active element, which may be a sensing element or a radiation emitting means. The integrated circuit (104) is mounted on and electrically connected to an interposer (103). The interposer (103) has a substantially identical coefficient of thermal expansion to the integrated circuit (104). The interposer (103) is glued to a lead frame (102). The integrated circuit (104) is electrically connected to the interposer (103) by means of bond wires (106) and the interposer (103) is electrically connected to the peripheral portions (101) of the lead frame (102) by means of bond wires (105). Once the integrated circuit (104), interposer (103) and lead frame (102) have been mounted upon one another and electrically connected, the blob of gel (107) is dispensed onto the top surface of said integrated circuit (104) to form a gel covered assembly. The gel coated assembly is inserted into the cavity of a mould tool. Said cavity is provided with a projection, (110) on its inner surface that is adapted to make contact with said gel blob (107). Plastic moulding compound (108) is then injected into the mould cavity to encapsulate the device in a protective package.

Description

PACKAGED INTEGRATED CIRCUIT DEVICES
The present invention relates in general to packaged integrated circuit devices and to methods of encapsulating such devices in a protective package, and in particular to packaged integrated circuit sensor and/or emitter devices and to methods of encapsulating such devices in a protective package.
Integrated circuit sensor or emitter devices comprise integrated circuits incorporating an active element adapted to detect pressure, motion, or other physical parameter or to detect and or emit radiation (at visible, infrared or ultraviolet wavelengths). Typically, the integrated circuit is encapsulated in a protective package, said package being adapted such that the integrated circuit may be electrically connected to external circuitry and such that the sensing element may be exposed to the external environment.
In order to ensure the device functions correctly, the active element should not be obscured by the package or damaged by the encapsulation process. Conventional low cost encapsulation methods involve mounting the integrated circuit on a lead frame and inserting the integrated circuit and lead frame in to the cavity of a moulding tool. A suitable moulding compound is then injected into the cavity to wholly encapsulate the integrated circuit at pressures in the range of 20 to 80 bar. A number of techniques may be used to ensure that the active element may still be exposed to the external environment.
In one such technique gel is applied to the active element before the integrated circuit is inserted into the moulding tool and the moulding tool is adapted such that the side of the moulding tool or a projection from the side of the moulding tool is in contact with the gel during the encapsulation process. In this manner a passageway is provided between the active element and the exterior of the package through which the active element may be exposed to external environment. In order to further expose the active element to the external environment, the gel may be removed once the encapsulation process is complete. Such a method is disclosed in US 5,897,338.
The volume and placement of the dispensed gel is critical in these methods as this defines the area of the integrated circuit that will remain exposed. Use of too little gel can result in plastic moulding compound contaminating or obscuring the active element, reducing or even destroying its operating capability. Alternatively, use of too much gel can leave an overly large void in the package after encapsulation thus making failure of the package more likely. In applications wherein the gel is removed after encapsulation, then exposure of additional components of the integrated circuit to the external environment can make circuitry failures more likely also. Uneven distribution of the gel can cause either or both of the above problems.
Such uneven distribution of gel can additionally lead to excessive stress on the integrated circuit with consequential damage or even breakage of the semiconductor in cases where no gel is present between the mould compound and sensor element.
A further problem which occurs even if the gel is correctly distributed is thermal coefficient of expansion mismatch between the integrated circuit and the package. This results in stress and or strain being placed on the integrated circuit.
This may cause errors in sensor accuracy, due to the stress and or strain or due to thermal drift and/or to hysteresis effects. This occurs initially whilst the package is cooling and setting after encapsulation and may also occur if the package is exposed to a large range of temperatures during operation. The effect is magnified if no gel is present between the active element and the mould compound forming the package.
It is therefore an object of the present invention to provide a method of packaging a sensor/radiator device that alleviates or overcomes at least some of the above problems.
According to the present invention there is provided a method of encapsulating an integrated circuit device within a package comprising the steps of: providing an integrated circuit incorporating at least one active element on a top surface of said integrated circuit; providing an inteφoser incorporating electrical contacts, said interposer having a substantially equal coefficient of thermal expansion to the integrated circuit; electrically connecting said integrated circuit to said inteφoser; mounting said inteφoser on a lead frame; mounting said integrated circuit on to a top surface of said inteφoser to form an assembly; electrically connecting said inteφoser to said lead frame; dispensing a quantity of gel onto said integrated circuit so as to cover the top surface of said integrated circuit and the top surface of said silicon inteφoser, thereby forming a gel coated assembly; inserting the assembly into a cavity of a moulding tool, said moulding tool having a projection on one surface of the tool adapted to make contact with said gel; introducing a moulding compound into the cavity so as to encapsulate the assembly except for the portion in contact with the projection; and removing the assembly from the cavity, whereby there is an opening defined in the moulding compound encapsulating the coated assembly through which the active element may be exposed.
With this method it is possible to provide low cost integrated circuit devices for use in detecting pressure, motion and/or any other suitable physical parameter and or detecting or emitting radiation (at visible, infra red or ultra violet wavelengths), without excess stress or strain being placed on the active element by a thermal mismatch between the integrated circuit and the moulding compound.
Preferably the inteφoser is mounted on the lead frame before the integrated circuit is mounted on the inteφoser. This allows both mounting steps to be carried out using conventional die attach technology.
Preferably, the moulding compound is injected in to the cavity to encapsulate the integrated circuit at pressures in the range of 20 to 80 bar.
The active element may be a sensing element or an emitting element. If the active element is a sensing element it is preferably a sensing element adapted for detecting one or more of pressure, motion temperature or radiation (at visible, infra red or ultra violet wavelengths). If desired, the device may comprise two or more sensing elements, each sensing element operable to sense the same and/or similar and/or different physical parameters. If the active element is an emitting element it is preferably a radiation emitting element (at visible, infra red or ultra violet wavelengths). In some preferred embodiments, the active elements may comprise a radiation sensing element and a radiation emitting element. In such embodiments, the emitting element and the sensing element may be adapted to operate at similar or different wavelengths as desired.
Preferably, said gel covers substantially the whole top surfaces of both said inteφoser and said integrated circuit. Preferably said gel is prevented from covering areas other than the top surfaces of said inteφoser and said integrated circuit by controlling the volume of gel dispensed. Most preferably, said gel has sufficient surface tension to stop flowing when it reaches the edges of said inteφoser.
Preferably the inteφoser is a silicon inteφoser. Preferably said integrated circuit is provided on a silicon wafer.
Said integrated circuit may be mounted onto said inteφoser by any suitable means, such as Flip-Chip mounting or any other suitable method. Preferably, said integrated circuit is electrically connected to said inteφoser by means of wires linking bond pads provided on the top surface of said inteφoser with bond pads provided on the top surface of said integrated circuit. Alternatively, said integrated circuit may be provided with vias extending through to the bottom surface of said integrated circuit and adapted to be electrically connected to suitable formations provided on the top surface of said inteφoser. Preferably said inteφoser is electrically connected to the periphery of said lead frame by means of wires linking bond pads provide on the top surface of said inteφoser with the periphery of the lead frame. Preferably, a pattern of electrical connections is provided on the upper surface of said inteφoser. Most preferably said connections run between bond pads connecting said inteφoser to said integrated circuit and bond pads connecting said inteφoser to said lead frame. Preferably said inteφoser may additionally provide electronic circuitry means to interface between said integrated circuit and external processing means.
Preferably, the integrated circuit is one of a plurality of similar integrated circuits formed on a single wafer. Most preferably said integrated circuits are formed in an array on said wafer, such as a rectangular or square array. Preferably, the wafer is then diced or sawn to separate the individual integrated circuits in the array. The individual integrated circuits are preferably then packaged according to the method described above.
According to a second aspect of the present invention there is provided a packaged integrated circuit device manufactured in accordance with the method of the first aspect of the invention.
The packaged integrated circuit device according to the second aspect of the present invention may incoφorate any of the features of the first aspect of the invention as desired or appropriate.
In order that the invention is more clearly understood, it will now be described further herein, by way of example only and with reference to the following drawings in which the single figure shows a cross-section of the integrated circuit device after encapsulation. Referring to figure 1 , an integrated circuit device 100 comprises an integrated circuit 104 encapsulated in a protective package 108. The integrated circuit 104, incoφorates at least one active element, which may be a sensing element responsive to an external stimulus such as radiation, pressure, temperature or similar; or a radiation emitting means. In such devices 100, the package is adapted to expose the active element to the external environment, whilst protecting the rest of integrated circuit 104.
In the example shown in figure 1, a gel blob 107 is provided over the top surface of integrated circuit 104. This provides some measure of protection for the integrated circuit whilst still allowing the active element to operate. For instance if the active element was a radiation sensing or emitting element and the gel 107 was a transparent gel the operation of the radiation sensing or emitting element would not be adversely effected by the presence of the gel 107. Similarly, a pressure sensing element will still operate effectively as atmospheric pressure will be transferred through the gel. The blob of gel 107, may of course be removed if required or desired.
The integrated circuit 104 is mounted on and electrically connected to an inteφoser 103. The inteφoser 103 has a substantially identical coefficient of thermal expansion to the integrated circuit 104. Typically, to achieve this, the integrated circuit 104 is provided on a silicon wafer and likewise, the inteφoser 103 is a silicon wafer. Electrical connections between the integrated circuit 104 and the inteφoser 103 are made by means of wires 106 linking bond pads provided on the top surface of the integrated circuit 104 to bond pads provided on the top surface of the inteφoser 103. In alternative embodiments, vias may be provided through the wafer upon which the integrated circuit 104 is provided allowing electrical connections to be made between the integrated circuit 104 and the inteφoser 103.
The inteφoser 103 is in turn mounted on and electrically connected to a lead frame 102. Electrical connections are made by wires 105 between bond pads provided on the top surface of the inteφoser 103 and peripheral portions 101 of the lead frame 102. A pattern of electrical connections is provided on the upper surface of the inteφoser 103, the electrical connections running between bond pads provided for electrically connecting the inteφoser 103 to the integrated circuit 104 and bond pads provided for electrically connecting the inteφoser 103 to the peripheral portions 101 of lead frame 102. In some embodiments, the inteφoser 103 may additionally incoφorate interface or processing circuitry.
The gel blob 107 covers the entire top surface of the inteφoser 103 and the entire top surface of the integrated circuit 104. The protective package 108 encapsulates the whole of the device other than the ends of the peripheral portions 101 of the lead frame 102 and part of the top surface of the gel blob 107. In this manner the device can be encapsulated within a protective package without the integrated circuit 104 being in direct contact with the moulding compound 108. This reduces the adverse effects of stress or strain resulting from the different coefficients of thermal expansion of the integrated circuit 104 and the moulding compound 108.
The device 100 is manufactured according to the following process. The inteφoser 103 is glued to the lead frame then the integrated circuit 104 is mounted onto the inteφoser 103. The integrated circuit is then electrically connected to the inteφoser 103 by means of bond wires 106 and the inteφoser 103 is electrically connected to the peripheral portions 101 of the lead frame 102 by means of bond wires 105. In some embodiments an alternative to a lead frame may be used such as an organic BGA substrate. Typically, the integrated circuit 104 is one of an array of like integrated circuits formed on a single wafer, individual integrated circuits being separated from the array by suitable cuts.
The electrical connections from the inteφoser 103 to the peripheral portions or leads 101 of the lead frame 102 can be made before or after the inteφoser 103 is mounted on to the lead frame 102.
Once the integrated circuit 104, inteφoser 103 and lead frame 102 have been mounted upon one another and electrically connected, the blob of gel 107 is dispensed onto the top surface of said integrated circuit 104 so as to cover the top surface of both said integrated circuit 104 and also the top surface of said inteφoser 103 to form a gel covered assembly. The quantity of gel dispensed is limited to restrain the gel from spreading any further than the edge 109 of the inteφoser 103. Gel dispersion is also limited by the surface tension of the gel 107.
The lead frame 102, inteφoser 103, integrated circuit 104 and gel blob 107 with all bond wires 105 and 106 are inserted into the cavity of a mould tool. Said cavity is provided with a projection on its inner surface that is adapted to make contact with said gel blob 107. Plastic moulding compound 108 is then injected into the mould cavity to encapsulate the device in a protective package. After the packaged device is removed from the moulding tool, the gel 107 may be removed or retained as desired. The gel 107 may be removed, for example to allow radiation to pass between the active element and the exterior of the package with less attenuation or distortion. Alternatively, the gel 107 may be retained for protection whilst transmitting radiation or pressure to the active element of the integrated circuit 104. In some embodiments, the projection of the moulding tool may be adapted to form the upper surface of the gel 107 into a desired shape. This may be used to provide a lens to focus incident on a radiation sensing element or to focus radiation emitted by an emitting element into a collimated beam. The provision of gel 107 between the integrated circuit 104 and the package
108 and the matched coefficients of thermal expansion between the integrated circuit 104 and the inteφoser 103 ensures that little or no strain is applied to the integrated circuit 104 when a change in temperature occurs. The gel 107 being flexible does not provide significant strain on the integrated circuit 104 if changes in temperature do occur.
It is of course to be understood that the invention is not to be limited to the details of the above embodiment which is described by way of example only.

Claims

1. A method of encapsulating an integrated circuit device within a package comprising the steps of: providing an integrated circuit incoφorating at least one active element on a top surface of said integrated circuit; providing an inteφoser incoφorating electrical contacts, said inteφoser having a substantially equal coefficient of thermal expansion to the integrated circuit; electrically connecting said integrated circuit to said inteφoser; mounting said inteφoser on a lead frame; mounting said integrated circuit on to a top surface of said inteφoser to form an assembly; electrically connecting said inteφoser to said lead frame; dispensing a quantity of gel onto said integrated circuit so as to cover the top surface of said integrated circuit and the top surface of said silicon inteφoser, thereby forming a gel coated assembly; inserting the assembly into a cavity of a moulding tool, said moulding tool having a projection on one surface of the tool adapted to make contact with said gel; introducing a moulding compound into the cavity so as to encapsulate the assembly except for the portion in contact with the projection; and removing the assembly from the cavity, whereby there is an opening defined in the moulding compound encapsulating the coated assembly through which the active element may be exposed.
2. A method as claimed in claim 1 wherein the inteφoser is mounted on the lead frame before the integrated circuit is mounted on the inteφoser.
3. A method as claimed in any preceding claim wherein the moulding compound is injected in to the cavity to encapsulate the integrated circuit at pressures in the range of 20 to 80 bar.
4. A method as claimed in any preceding claim wherein said gel covers substantially the whole top surfaces of both said inteφoser and said integrated circuit.
5. A method as claimed in claim 4 wherein said gel is prevented from covering areas other than the top surfaces of said inteφoser and said integrated circuit by controlling the volume of gel dispensed.
6. A method as claimed in claim 4 or claim 5 wherein said gel has sufficient surface tension to stop flowing when it reaches the edges of said inteφoser.
7. A method as claimed in any preceding claim wherein the inteφoser is a silicon inteφoser.
8. A method as claimed in any preceding claim wherein said integrated circuit is provided on a silicon wafer.
9. A method as claimed in any preceding claim wherein said integrated circuit is mounted onto said inteφoser by Flip-Chip mounting.
10. A method as claimed in any preceding claim wherein said integrated circuit is electrically connected to said inteφoser by means of wires linking bond pads provided on the top surface of said inteφoser with bond pads provided on the top surface of said integrated circuit.
11. A method as claimed in any one of claims 1 to 9 wherein said integrated circuit is provided with vias extending through to the bottom surface of said integrated circuit and adapted to be electrically connected to suitable formations provided on the top surface of said inteφoser.
12. A method as claimed in any preceding claim wherein said inteφoser is electrically connected to the periphery of said lead frame by means of wires linking bond pads provide on the top surface of said inteφoser with the periphery of the lead frame.
13. A method as claimed in any preceding claim wherein a pattern of electrical connections is provided on the upper surface of said inteφoser.
14. A method as claimed in claim 13 wherein said connections run between bond pads connecting said inteφoser to said integrated circuit and bond pads connecting said inteφoser to said lead frame.
15. A method as claimed in any preceding claim wherein said inteφoser additionally provides electronic circuitry means to interface between said integrated circuit and external processing means.
16. A method as claimed in any preceding claim wherein the active element is a sensing element.
17. A method as claimed in claim 16 wherein the sensing element is a sensing element adapted for detecting one or more of pressure, motion, temperature or radiation.
18. A method as claimed in claim 16 or claim 17 wherein the device may comprise two or more sensing elements.
19. A method as claimed in any preceding claim wherein the active element is an emitting element.
20. A method as claimed in claim 19 wherein the active element is a radiation emitting element.
21. A method as claimed in any preceding claim wherein there are two active elements, a radiation sensing element and a radiation emitting element.
22. A method as claimed in any preceding claim wherein the integrated circuit is one of a plurality of similar integrated circuits formed on a single wafer.
23. A method as claimed in claim 22 wherein said integrated circuits are formed in an array on said wafer.
24. A method as claimed in claim 23 wherein the wafer is then diced or sawn to separate the individual integrated circuits in the array.
25. A packaged integrated circuit device manufactured in accordance with the method of any preceding claim.
PCT/IB2005/001591 2004-06-04 2005-06-06 Packaged integrated circuit devices WO2005119757A2 (en)

Priority Applications (2)

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EP05748165A EP1751793A2 (en) 2004-06-04 2005-06-06 Packaged integrated circuit devices
JP2007514204A JP2008502130A (en) 2004-06-04 2005-06-06 Packaged integrated circuit device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB0412435.0 2004-06-04
GBGB0412435.0A GB0412435D0 (en) 2004-06-04 2004-06-04 Packaged intergrated circuit devices

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WO2005119757A3 WO2005119757A3 (en) 2006-09-14

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US9690578B2 (en) 2013-02-20 2017-06-27 Intel Corporation High dose radiation detector
JP2021071294A (en) * 2019-10-29 2021-05-06 セイコーエプソン株式会社 Vibration device, electronic device, and moving body

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KR20070024603A (en) 2007-03-02
WO2005119757A3 (en) 2006-09-14
JP2008502130A (en) 2008-01-24
GB0412435D0 (en) 2004-07-07

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