WO2005117092A2 - Ensemble de semi-conducteurs empilés ayant une structure et un isolement intercalaires adhésifs - Google Patents

Ensemble de semi-conducteurs empilés ayant une structure et un isolement intercalaires adhésifs Download PDF

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Publication number
WO2005117092A2
WO2005117092A2 PCT/US2005/017670 US2005017670W WO2005117092A2 WO 2005117092 A2 WO2005117092 A2 WO 2005117092A2 US 2005017670 W US2005017670 W US 2005017670W WO 2005117092 A2 WO2005117092 A2 WO 2005117092A2
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WIPO (PCT)
Prior art keywords
die
adhesive
package
spacer
spacer elements
Prior art date
Application number
PCT/US2005/017670
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English (en)
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WO2005117092A3 (fr
Inventor
Hyeog Chan Kwon
Marcos Karnezos
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Chippac, Inc.
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Publication date
Priority claimed from US10/969,303 external-priority patent/US20050258545A1/en
Application filed by Chippac, Inc. filed Critical Chippac, Inc.
Publication of WO2005117092A2 publication Critical patent/WO2005117092A2/fr
Publication of WO2005117092A3 publication Critical patent/WO2005117092A3/fr

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    • H—ELECTRICITY
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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Definitions

  • a multi-chip module includes one or more integrated circuit semiconductor chips, often referred to as circuit die, stacked one onto another to provide the advantages of light weight, high density, and enhanced electrical performance.
  • each chip can be lifted by a chip-bonding tool, which is usually mounted at the end of a pick-and-piace device, and mounted onto the substrate or onto a semiconductor chip mounted previously.
  • the upper die can be attached directly to the lower die without the use of spacers.
  • spacer die that is die without circuitry, can be used between the upper and lower die.
  • adhesives containing spacer elements typically micro spheres, are often used to properly separate the upper and lower die. See U.S. Patents Nos.
  • the invention features stacked semiconductor assemblies in which a device such as a die, or a package, or a heat spreader is stacked over a first wire-bonded die.
  • An adhesive/spacer structure is situated between the first wire-bonded die and the device stacked over it, and the device has an electrically non-conductive surface facing the first wire- bonded die. That is, the first die is mounted active side upward on a first substrate and is electrically interconnected to the substrate by wire bonding; an adhesive/spacer structure is formed upon the active side of the first die; and a device such as a die or a package or a heat spreader, having an electrically nonconductive side, is mounted upon the adhesive/spacer structure with the electrically nonconductive side facing the first wire bonded die.
  • the side of the device facing the first wire bonded die may be made electrically nonconductive by having an electrically insulating layer, such as a dielectric film adhesive.
  • the invention features a multiple-die semiconductor chip assembly.
  • a first die has a first surface bounded by a periphery and bond pads at the first surface. Wires are bonded to and extend from the bond pads outwardly past the periphery.
  • a second die has an electrically non-conductive second surface positioned opposite the first surface. The first and second die define a first region therebetween.
  • An adhesive/spacer structure comprising spacer elements within an adhesive, is within the first region. The adhesive/spacer structure contacts the first and second surfaces and adheres the first and second die to one another at a chosen separation.
  • the assembly may comprise a set of generally parallel wires which define a wire span portion of the first region. The adhesive/spacer structure is preferably located at other than the wire span portion of the first region.
  • the invention features a method for adhering first and second die to one another at a chosen separation in a multiple-die semiconductor chip assembly.
  • An adhesive/spacer material having spacer elements within an adhesive, is selected.
  • the adhesive/spacer material is deposited onto a first surface of a first die.
  • the first surface is bounded by a periphery and has bond pads.
  • a set of generally parallel wires is bonded to and extends from the bond pads outwardly past the periphery.
  • the set of generally parallel wires define a wire span portion of the first surface.
  • a second die, having an electrically non- conductive second surface is selected.
  • the second surface of the second die is located opposite the first surface of the first die and in contact with the adhesive/spacer material therebetween thereby securing the first and second die to one another at a chosen separation, the wire span portion of the first surface defining a wire span region between the first and second surfaces.
  • the adhesive/spacer material is deposited in a manner to prevent any spacer elements from entering the wire span region.
  • the invention features stacked semiconductor assemblies including an upper package stacked over a first wire-bonded die.
  • the first die has a first surface bounded by a periphery and bond pads at the first surface. Wires are bonded to and extend from the bond pads outwardly past the periphery.
  • An upper package has an electrically non- conductive second surface positioned opposite the first surface of the first die. The first die and the upper package define a first region therebetween.
  • An adhesive/spacer structure comprising spacer elements within an adhesive, is within the first region. The adhesive/spacer structure contacts the first and second surfaces and adheres the first die and the upper package to one another at a chosen separation.
  • the assembly may comprise a set of generally parallel wires which define a wire span portion of the first region.
  • the adhesive/spacer structure is preferably located at other than the wire span portion of the first region.
  • the upper package in the stacked semiconductor assembly includes at least one upper package die affixed to a die attach side of an upper package substrate.
  • the upper package is oriented so that the die attach side of the upper package substrate faces the first die; that is, the upper package is inverted.
  • the upper package is oriented so that the side of the upper package substrate opposite the die attach side faces the first die.
  • the upper package may be any of a variety of package types can be suitable as the upper package.
  • the invention features a method for adhering a die and a package to one another at a chosen separation in a stacked semiconductor package.
  • An adhesive/spacer material having spacer elements within an adhesive, is selected.
  • the adhesive/spacer material is deposited onto a first surface of a first die.
  • the first surface is bounded by a periphery and has bond pads.
  • a set of generally parallel wires is bonded to and extends from the bond pads outwardly past the periphery.
  • the set of generally parallel wires define a wire span portion of the first surface.
  • a package, having an electrically non-conductive second surface is selected.
  • the second surface of the package is located opposite the first surface of the die and in contact with the adhesive/spacer material therebetween thereby securing the die and the package to one another at a chosen separation, the wire span portion of the first surface defining a wire span region between the first and second surfaces.
  • the adhesive/spacer material is deposited in a manner to prevent any spacer elements from entering the wire span region.
  • FIG. 1 is a simplified plan view of a conventional peripheral bonded die
  • FIG. 2 is a simplified plan view of a conventional center bonded die
  • FIGs. 3 and 4 illustrate conventional forward loop and reverse wire bonds
  • FIG. 5 is a partial cross sectional view of a multi-die semiconductor assembly made according to the invention.
  • FIG. 6 is a top plan view of the assembly of FIG. 5 with the periphery of the upper die shown in dashed lines;
  • FIG. 7 illustrates an alternative embodiment to the assembly of FIG. 6;
  • FIG. 8 is a side cross sectional view of the assembly of FIGs. 5 and 6;
  • FIG. 9 shows the assembly of FIG. 8 After encapsulation with a molding compound to create a multiple die semiconductor chip package
  • FIG. 10 illustrates an alternative embodiment similar to that of FIG. 5 in which adhesive fills the wire span portion of the adhesive region; and [0021] FIG. 11 illustrates an alternative embodiment in a view similar to that of FIG. 9 but in which the upper die does not overhang the edge of the lower die, and in which adhesive fills the wire span portion of the adhesive region as in FIG. 10.
  • FIGs. 12 through 15 illustrate embodiments of assemblies according to various aspects of the invention in which a package and a die are stacked.
  • FIG. 1 illustrates a conventional peripheral bonded die 10 mounted to a substrate 12.
  • Die 10 has bond pads 14 along one, some or all of its peripheral edges 16 - 19.
  • Wires 20 connect bond pads 14 to corresponding bond pads 22 on substrate 12.
  • Wires 20 comprise sets of generally parallel wires along each peripheral edge 16 - 18 and define wire span areas 24, indicated by crosshatching in FIG. 1, along such edges.
  • Bond pads 14 on peripheral bonded die 10 are typically placed very close to the corresponding peripheral edge 16 - 19, typically within 100 micrometers of the peripheral edge.
  • FIG. 2 illustrates a conventional center bonded die 26, such as a DRAM, having bond pads 14 at a central region 28 of die 26.
  • Wires 20 extending from bond pads 14 define, in this example, wire span areas 24 between the two sets of bond pads 14 and peripheral edges 16, 18.
  • the distance between bond pads 14 and the corresponding peripheral edges for a center bonded die is preferably much more than 100 micrometers. More preferably, the distance between a bond pad 14 for a center bonded die 26 and the nearest peripheral edge is at least about 40% of the corresponding length or width of the die. For example, the distance between a bond pad 14A and peripheral edge 16 is at least about 40% of the length of peripheral edge 17.
  • FIGs. 3 and 4 illustrate conventional forward loop wire bonding and conventional reverse wire bonding techniques.
  • Forward loop wire bond 30 of FIG. 3 has a wire loop height 32, typically about 60 - 100 micrometers.
  • Wire 20 has a recrystalization zone 34. Recrystalization zone 34 is not as flexible as the remainder of wire 20 so that excessive flexion of wire 20 within zone 34 may cause wire 22 to break. Therefore, in it is important that wire 20, especially within recrystalization zone 34, not be deformed to any significant degree during manufacturing. This is especially important in the manufacture of multi-chip packages.
  • FIG. 5 illustrates a partial cross sectional view of a multi-die semiconductor assembly 40 made according to the invention. Assembly 40 includes a lower, peripheral bonded die 42 and an upper die 44. Assembly 40 protects against shorting of wires 20 against upper die 44 in two basic ways.
  • upper die 44 has electrically insulating layer 45, typically a dielectric film adhesive, such as available from Lintec Corporation as Lintec LE5000 or an Hitachi DF series film adhesive.
  • Structure 46 includes adhesive 48 and spacer elements 50.
  • Structure 46 may be a conventional material such as Loctite® QMI536-3, 4, or 6, which use nominal 3, 4 or 6 mil (75, 100 and 150 micrometers) diameter organic polymer spherical particles as spacer elements 50; or a spacer adhesive from the Ablestik 2025 Sx series. It is preferred that spacer elements 50 be of an organic polymer material and pliable and large enough to permit forward loop wire bonding.
  • Spacer elements 50 are typically about 30 - 250 micrometers in diameter. Structure 46 also helps to provide bond line thickness control and die tilt control. Prevention of the incursion of the adhesive/spacer material, and in particular spacers 50, into wire span portion 60 of first, adhesive region 58 (refer to FIG. 6) may be achieved by, for example, depositing the adhesive/spacer material at selected positions and carefully controlling the amount deposited at each position. Examples of suitable materials for spacer elements 50 include PTFE and other organic polymers. [0029] Spacer elements 50, prior to use, are typically spherical, ellipsoidal, cylindrical with hemispherical or ellipsoidal ends, or the like.
  • spacer elements 50 are compressible, spacer elements 50 are compressed to some degree and have flattened areas where they contact upper surface 52 of lower die 42 and the electrically non-conductive lower surface 54 of upper die 44; the shape of such spacers is collectively referred to as generally ellipsoidal.
  • an initially spherical spacer element 50 having an 8 mil (200 micrometer) diameter will typically compress to a height of about 7.5 mil (188 micrometers).
  • the height 56 of spacers 50 which is equal to the distance between surface 52 and 54, is preferably at least equal to loop height 32, is more preferably greater than loop height 32, is even more preferably at least about 10% greater than loop height 32.
  • FIG. 6 illustrates assembly 40 with upper die 44 indicated by dashed lines.
  • Lower and upper die 42, 44 define a first, adhesive region 58 therebetween.
  • region 58 is defined by the periphery of lower die 42 because upper die 44 extends beyond the entire periphery of the lower die.
  • Wire span areas 24, indicated by crosshatching, define wire span portions 60 of first, adhesive region 58.
  • the adhesive/spacer material is deposited in a manner so that, as shown in FIG.
  • FIG. 7 illustrates a multi-die semiconductor assembly 62 in which lower die 42 is a center bonded die such as shown in FIG. 2 and upper die 44, shown in dashed lines, is longer but narrower than lower die 42. Therefore, in this embodiment first, adhesive region 58 does not cover the entire lower die 42 but rather is bounded by peripheral edges 17 and 19 of lower die 42 and peripheral edges 16 and 18 of upper die 44.
  • Adhesive/spacer structure 46 is, in the embodiment of FIG. 6, located within first, adhesive region 58 at other than wire span portions 60. Adhesive/spacer structure 46 may define a single adhesive/spacer structure region as shown in FIG. 6 or two or more adhesive/spacer structure regions, such as shown in FIG. 7.
  • Adhesive/spacer material may be deposited using a conventional dispenser capillary. However, it is preferred that the adhesive/spacer material be deposited using a showerhead type of dispenser as shown in the above-mentioned US Provisional Patent Application entitled Adhesive/Spacer Island Structure For Multiple Die Package. Doing so can facilitate the positioning of the adhesive/spacer material at spaced apart locations to provide the desired coverage by adhesive/spacer structure 46. This may be especially advantageous when working with center bonded die.
  • FIG. 8 is a side cross sectional view of multi-die semiconductor assembly 40 of FIGs. 5 and 6 showing wires 20 extending from bond pads 14 of upper and lower die 44, 42 to bond pads 22 of substrate 12.
  • FIG. 9 illustrates the structure of FIG.
  • Spacer elements 50 may also be prevented from incursion into wire span portion 60 by sizing the spacer elements so as not to fit between the generally parallel wires 20. In this way wires 20 act as a sieve or strainer to permit a portion 47 of adhesive 48 to enter into wire span portion 60 but prevent spacer elements 50 from doing so. This is illustrated in Fig. 10, showing adhesive/spacer structure 46 including adhesive 48, with spacer elements 50 situated in regions other than the wire span portion of the adhesive region, and showing a portion 47 of adhesive 48 having entered into the wire span portion of the adhesive region.
  • the spacer elements provide a suitable distance between the two die, the lower surface of the upper die being electrically insulated by dielectric layer 45, as described above with reference to FIG. 5.
  • the full occupancy of adhesive region 58 by adhesive 48, particularly the portion 47 of the adhesive in the wire span region, eliminates the open overhang of the upper die above wires 20 shown in Fig. 5. This provides some support for the upper die, and helps to reduce or eliminate die breakage, which is especially useful for large and thin semiconductor devices.
  • the adhesive/spacer structure according to the invention can be useful for multi-die assembly structures in which the upper die 44 does not extend over the edge of the lower die 42, as illustrated in FIG. 11, which is a view similar to the view of FIG. 9.
  • spacer structure 46 including spacer elements 50 and adhesive 48 is formed between the upper die 44 with insulating layer 45, and the lower die 42.
  • the wires 20 prevent the spacer elements from entering into the wire span region, but permit a portion 47 of the adhesive 48 to fill the volume there and provide support for the part of the upper 44 die that overhangs the wire loops 20.
  • a stacked semiconductor assembly includes a package stacked with a die, separated by an adhesive/spacer material generally as described above for stacked die assemblies.
  • FIGs. 12 and 13 illustrate examples 102, 103 of such assemblies, in which an inverted package is stacked over a die.
  • a lower, peripheral bonded die 142 is mounted upon a substrate 112, and bond pads on the die are electrically interconnected with bond pads on the substrate by wire bonds 120.
  • An adhesive/spacer structure 146 is formed upon the die 142 including an adhesive and spacer elements as described above with reference to adhesive/spacer structure 46.
  • An upper package 100 is inverted and mounted upon the adhesive/spacer structure 146, in substantially the same manner as the upper die 44 is mounted upon adhesive/spacer structure 46 in the stacked die assembly 40, for example, of FIG. 8.
  • the upper package 100 in this example is a land grid array package, having a die 242 mounted onto a die attach side on upper package substrate 112. Die 242 in this example is wire bonded to substrate 112, and the die and wire bonds are enclosed in an encapsulation 217.
  • the package 100 is inverted so that the land side of the substrate 212 faces away from the first die 142 and substrate 212, and so that an upper surface of the encapsulation 217 faces toward the first die 142 and substrate 212. In the orientation of FIG.
  • the land side of the inverted upper package 212 is upward-facing, and the upper package is electrically interconnected with the bottom substrate 212 by wire bonds between bond pads on the land side of the upper package substrate 212 and bond pads on the upward-facing side of the lower substrate 112.
  • the assembly is then encapsulated (not shown in FIG. 12) to form a package, substantially as the stacked die assembly 40 of FIG. 8 is encapsulated to form the package 68 of FIG. 9.
  • Solder balls 118 are mounted onto pads on the downward-facing side of the substrate 112, for interconnection of the package to, for example, a motherboard.
  • Multiple chip modules having inverted package stacked over a die, in which the adhesive/spacer structures described herein may be particularly suitable, are described in U.S. Patent Application No. 11/014,257.
  • two (or more) die may be stacked using an adhesive/spacer structure over one another on a lower substrate, and a package may be stacked over the uppermost one of the stacked die, using an adhesive/spacer structure, as shown by way of example in FIG. 13.
  • a die 142 is mounted onto a lower substrate 112, and a die 144 is stacked over the die 142, and separated from it by an adhesive/spacer structure 246 as described above for stacked die assemblies.
  • Die 142 and 144 are electrically interconnectedd with substrate 112 by wire bonds 220.
  • An inverted pachage 100 is mounted over the stacked die 142, 144, separated by the die 144 by and adhesive/spacer structure 246, as described above with reference to FIG. 12.
  • either or both of the spacers, between the die, and between the die and the inverted package may be an adhesive/spacer structre as described above with referenbce to stacked die assemblies.
  • Any of a variety of packages may be stacked over the die in assemblies according to these embodiments of the invention. Stacked multi-package modules having inverted upper packages are described in U.S. Patent Application No. 10/681,572; and examples of suitable upper inverted package types are described therein. These include, for example, besides land grid array packages as illustrated in FIGs. 12 and 13, bump chip carrier packages; and the upper package may include more than one die.
  • the upper package encapsulant has a generally planar surface that contacts the adhesive/spacer structure, that surface (termed the "second" surface) is itself electrically nonconductive, and application of an additional insulating layer (as layer 45 in FIGs. 5, 8, 10 and 11) may be optional in such embodiments.
  • the second surface of the upper package is an electrically conductive material (such as a metal heat spreader, for example) or includes exposed electrically conductive areas or elements
  • an insulating layer 45 should be applied, as described above with reference for example to FIG. 5.
  • a stacked semiconductor assembly includes a package stacked with a die, separated by an adhesive/spacer material generally as described above for stacked die assemblies, the upper package is not inverted.
  • FIGs. 14 and 15 illustrate examples 104, 104 of such assemblies.
  • a lower, peripheral bonded die 142 is mounted upon a substrate 112, and bond pads on the die are electrically interconnected with bond pads on the substrate by wire bonds 120.
  • An adhesive/spacer structure 146 is formed upon the die 142 including an adhesive and spacer elements as described above with reference to adhesive/spacer structure 46.
  • An upper package 400 is inverted and mounted upon the adhesive/spacer structure 146, in substantially the same manner as the upper die 44 is mounted upon adhesive/spacer structure 46 in the stacked die assembly 40, for example, of FIG. 8. [0041]
  • the upper package 400 in this example is a land grid array package, having a die 442 mounted onto a die attach side on upper package substrate 412.
  • Die 442 in this example is wire bonded to substrate 412, and the die and wire bonds are enclosed in a mold cap 417.
  • the package 400 is oriented so that the land side of the substrate 412 faces toward the first die 142 and substrate 212, and so that the land side of the upper package substrate 412 faces toward the first die 142 and substrate 212.
  • the land side of the inverted upper package 412 is downward-facing, and the upper package is electrically interconnected with the bottom substrate 112 by wire bonds between bond pads on the upward-facing (die attach) side of the upper package substrate 412 and bond pads on the upward-facing side of the lower substrate 112.
  • the assembly is then encapsulated (not shown in FIG.
  • solder balls 118 are mounted onto pads on the downward-facing side of the substrate 112, for interconnection of the package to, for example, a motherboard.
  • two (or more) die may be stacked using an adhesive/spacer structure over one another on a lower substrate, and a package may be stacked over the uppermost one of the stacked die, using an adhesive/spacer structure, as shown by way of example in FIG. 15.
  • a die 142 is mounted onto a lower substrate 112, and a die 144 is stacked over the die 142, and separated from it by an adhesive/spacer structure 246 as described above for stacked die assemblies.
  • Die 142 and 144 are electrically interconnectedd with substrate 112 by wire bonds 220.
  • An inverted pachage 100 is mounted over the stacked die 142, 144, separated by the die 144 by and adhesive/spacer structure 246, as described above with reference to FIG. 14.
  • the spacers, between the die, and between the die and the inverted package may be an adhesive/spacer structre as described above with referenbce to stacked die assemblies.
  • Any of a variety of packages may be stacked over the die in assemblies according to these embodiments of the invention. Stacked multi-package modules suitable upper packages are described in U.S. Patent Applications Nos.
  • 10/632,549; 10/632,568; 10/632,551; 10/632,552; 10/632,553; and 10/632,550; and examples of suitable upper package types are described therein. These include, for example, besides land grid array packages as illustrated in FIGs. 14 and 15, bump chip carrier packages, and flip chip packages; and the upper package may include more than one die. Where the downward-facing surface of the upper package ("second" surface) had electrically conductive elements or areas, application of an additional insulating layer (as layer 45 in FIGs. 5, 8, 10 and 11) may be required and may be applied as described above with reference for example to FIG. 5, and as shown for example at 450 in FIGs. 14 and 15.
  • an additional insulating layer as layer 45 in FIGs. 5, 8, 10 and 11
  • This additional insulating layer may be applied as a film to the land side of the upper package substrate, and voids between the film and the substrate surface removed by heating at low pressure, according to techniques known in the art.
  • Other devices may be stacked over the first die, and separated therefrom by an adhesive/spacer structure as described above, and provided with an insulating layer as appropriate.
  • a metal heat spreader may be stacked upon an adhesive/spacer structure over the first die in place of the upper die or upper package in the descriptions above.
  • the assemblies and packages according to the invention can be useful in any of a variety of products, such as for example computers, mobile telecommunications devices, personal digital assistance devices, media storage devices, particularly portable cameras and audio and video equipment.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Wire Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

Ensembles semi-conducteurs empilés dans lesquels un dispositif tel qu'une filière, ou un ensemble, ou un dissipateur de chaleur est empilé par-dessus une première filière micro-câblée. Une structure à intercalaires adhésifs est située entre la première filière micro-câblée et le dispositif placé au-dessus de celle-ci, et le dispositif a une surface non-conductrice électriquement faisant face à la première filière micro-câblée. Ceci étant, la première filière est montée côté actif vers le haut sur un premier substrat et raccordée électriquement au substrat par micro câblage; une structure à intercalaires adhésifs est formée sur le côté actif de la première filière; et un dispositif tel qu'une filière ou un ensemble ou un dissipateur de chaleur, ayant un côté non conducteur électriquement, est monté sur la structure à intercalaires adhésifs avec un côté non conducteur électriquement faisant face à la première filière micro-câblée. Le côté du dispositif faisant face à la première filière micro-câblée peut être rendu électriquement non conducteur en ayant une couche d'isolement électrique, telle qu'un film diélectrique adhésif. Des méthodes pour la réalisation des ensembles sont également présentées.
PCT/US2005/017670 2004-05-24 2005-05-20 Ensemble de semi-conducteurs empilés ayant une structure et un isolement intercalaires adhésifs WO2005117092A2 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US57395604P 2004-05-24 2004-05-24
US60/573,956 2004-05-24
US10/969,303 2004-10-20
US10/969,303 US20050258545A1 (en) 2004-05-24 2004-10-20 Multiple die package with adhesive/spacer structure and insulated die surface

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WO2005117092A3 WO2005117092A3 (fr) 2007-10-11

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020096755A1 (en) * 2001-01-24 2002-07-25 Yasuki Fukui Semiconductor device
US6441496B1 (en) * 2000-11-22 2002-08-27 Wen Chuan Chen Structure of stacked integrated circuits
US6593662B1 (en) * 2000-06-16 2003-07-15 Siliconware Precision Industries Co., Ltd. Stacked-die package structure
US6650019B2 (en) * 2000-07-20 2003-11-18 Amkor Technology, Inc. Method of making a semiconductor package including stacked semiconductor dies
US6930396B2 (en) * 2002-04-05 2005-08-16 Nec Electronics Corporation Semiconductor device and method for manufacturing the same
US7053477B2 (en) * 2002-10-08 2006-05-30 Chippac, Inc. Semiconductor multi-package module having inverted bump chip carrier second package

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6593662B1 (en) * 2000-06-16 2003-07-15 Siliconware Precision Industries Co., Ltd. Stacked-die package structure
US6650019B2 (en) * 2000-07-20 2003-11-18 Amkor Technology, Inc. Method of making a semiconductor package including stacked semiconductor dies
US6441496B1 (en) * 2000-11-22 2002-08-27 Wen Chuan Chen Structure of stacked integrated circuits
US20020096755A1 (en) * 2001-01-24 2002-07-25 Yasuki Fukui Semiconductor device
US6930396B2 (en) * 2002-04-05 2005-08-16 Nec Electronics Corporation Semiconductor device and method for manufacturing the same
US7053477B2 (en) * 2002-10-08 2006-05-30 Chippac, Inc. Semiconductor multi-package module having inverted bump chip carrier second package

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