Classifications

• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01T—MEASUREMENT OF NUCLEAR OR X-RADIATION
  • G01T3/00—Measuring neutron radiation
  • G01T3/08—Measuring neutron radiation with semiconductor detectors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F30/00—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors
  • H10F30/20—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors
  • H10F30/29—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to radiation having very short wavelengths, e.g. X-rays, gamma-rays or corpuscular radiation

Definitions

• the present invention is directed in general to a neutron detection device and a method of manufacturing a neutron detection device.
• the present invention is specifically directed to a semiconductor device for the detection of neutrons that utilizes a neutron conversion layer in close proximity to a conventional memory cell structure.
• Scintillation devices include a light-transmissive neutron sensitive material (either a gas or a liquid) that generates light charged particles upon receipt of incident neutrons.
• the scintillation devices are typically coupled to a photomultiplier tube to generate an analog electrical signal based on the production of the light within the scintillation material.
• the analog signal is a representation of the incident neutron irradiation.
• Another class of conventional neutron detector is the gas filled counter, typically based on a gaseous helium-3 contained in high pressure tubes.
• the helium-3 filled tubes are delicate, require careful handling, and can indicate false positives when abruptly moved or struck.
• These types of conventional neutron detectors are effective in many types of field operations, but they are not suitable for operations requiring compact and highly sensitive devices capable of functioning for long periods of time with low power consumption.
• silicon-based semiconductor devices could be used to sense alpha particles emitted resulting from a neutron converter material in which an (n, alpha) reaction had taken place. The role of the converter material is to convert incident neutrons into emitted charged particles which are more readily sensed.
• SEUs single event upsets
• SEEs single event errors
• the error events which are detrimental when trying to maintain data integrity, can be used in a positive manner to detect radiation events by simply monitoring the radiation-induced charges in the states of the memory cells.
• Attempts have been made to utilize commercial memory circuits with a neutron converter in order to use the SEU associated with the memory circuits for neutron detection.
• boron has been used in the semiconductor industry as a dopant and in boron containing glass as a passivation layer that is used to cover the circuit-defining structures and to encapsulate a finished semiconductor chip.
• a neutron detection device that does not require the use of high pressure tubes or high voltages, is not sensitive to gamma radiations, is not sensitive to thermal noise, and operates with low power consumption, but yet is sensitive enough to permit the counting of single neutron events. It would further be desirable to provide a neutron detection device of inexpensive design and manufacture. Still further, it would be desirable to provide a method of manufacturing a neutron detection device that involved the modification on conventional memory devices, thereby permitting conventional memory devices to be converted to neutron detection devices.
• the invention provides a neutron detection device which does not require the use of high pressure tubes or high voltages for its operation, is not sensitive to gamma radiations, is not sensitive to thermal noise, and operates at low power consumption, but yet is sensitive enough to permit the counting of single neutron events.
• the invention further provides a neutron detection device of inexpensive design and manufacture.
• the device is based on a novel architecture for fabricating charge-sensitive semiconductor circuit elements in close proximity to a neutron conversion layer, thereby enabling the circuit elements to sense the charges produced in the semiconductor by transiting particles emitted from the reaction of a neutron with an atom of the conversion layer.
• One embodiment of the device maybe fabricated by modification of existing conventional semiconductor memory devices, thereby enabling existing devices to be modified for use as neutron detectors.
• the neutron detection device includes an active semiconductor device layer including a plurality of charge-sensitive elements such as conventional memory cells, and a neutron conversion layer located in close proximity to the charge-sensitive elements.
• the neutron conversion layer produces particles which are detectable by the charge-sensitive elements when neutrons enter the conversion layer.
• the location of the neutron conversion layer in close proximity to the memory cells increases the sensitivity of the neutron detection device.
• the neutron conversion layer may include boron or lithium. When an electrically conductive form of boron or boron containing composition is utilized, it is preferable to include an insulating layer located between the active semiconductor layer and the neutron conversion layer. Further, a barrier layer may be located between the neutron conversion layer and the insulating layer.
• the barrier layer preferably comprises silicon nitride.
• a preferred embodiment of the device employs a static random access (SRAM) memory circuit that is fabricated as a semiconductor-on-insulator (SOI) device.
• the SOI device includes a circuit structure layer comprising the structures by which the circuit is defined in an active semiconductor layer, the active semiconductor layer, and an insulating layer, the layers being arranged in the order just given.
• the insulating layer of SOI devices is typically approximately 200 nanometers thick.
• beneath the insulator of the SOI device is a neutron conversion layer in intimate contact with the insulating layer. The close proximity of the neutron conversion layer to the active semiconductor layer yields substantial improvements in device detection sensitivity.
• a barrier layer can also be incorporated by intimate contact between the neutron conversion layer and the active semiconductor layer to prevent diffusion of the neutron conversion material into the active semiconductor layer. Sensitivity can be further improved by adding a second neutron conversion layer in intimate contact with the first neutron conversion layer. It is also possible to provide an insulating neutron conversion layer in direct contact with the active semiconductor layer. It is further possible to provide a neutron conversion layer separated from the active semiconductor layer by a barrier layer provided between them, or by an insulating barrier layer in the case of a conducting conversion layer. Thin layers may be applied to surfaces to aid in maintaining the aforementioned intimate contacts.
• the neutron detection device is constructed from a conventional SRAM memory device that includes a SOI substrate.
• the SOI substrate includes an active semiconductor layer, a base substrate and an insulating layer between the active semiconductor layer and the base substrate.
• the base substrate layer is removed from the memory device by lapping, grinding and or etching to expose the insulating layer.
• a neutron conversion layer is then formed on the insulating layer. The close proximity of the neutron conversion layer to the active semiconductor layer yields substantial improvements in device sensitivity. Additional details and advantages of the invention will become apparent to those skilled in the art in view of the following detailed description of the preferred embodiments of the invention.
• Fig. 1 illustrates a conventional semiconductor memory device that includes a SOI substrate
• Fig. 1 A illustrates a preferred embodiment of the neutron device structure
• Fig. 2 illustrates the application of a bonding layer to the conventional memory device of Fig. 1 and the removal of the base substrate of the conventional memory device of Fig. 1
• Fig. 3 illustrates the formation of a neutron conversion layer on the exposed insulating layer of Fig. 2
• Fig. 4 illustrates the direct application of a neutron conversion layer to the active semiconductor layer of the conventional memory device
• Fig. 5 illustrates the addition of a second neutron conversion layer to the device illustrated in Fig. 3
• Fig. 6 illustrates the addition of a second neutron conversion layer to the device illustrated in Fig. 4;
• Fig. 7 is a graph illustrating the Qcrit for unhardened silicon memory cells based on feature size;
• Fig. 8 is a plot of the Linear Energy Transfer (LET) of an alpha particle from the isotope boron- 10 traversing silicon; and
• Fig. 9 is a graph including limiting values for liberating charge in the active semiconductor layer.
• LET Linear Energy Transfer
• the present invention is directed to a neutron detection device that utilizes a neutron conversion layer in close proximity to charge-sensitive elements such as conventional memory cells. Specifically, the device provides a neutron conversion layer in close proximity to the active semiconductor layer of a charge-sensitive electronic semiconductor device such as a semiconductor memory cell.
• the invention will be described with reference to an SRAM memory device formed on a SOI substrate.
• Fig. 1 illustrates a conventional SRAM memory device formed on a SOI substrate.
• the SOI substrate 10 includes an active semiconductor layer 12, an insulating layer 14 (referred to as a buried oxide "BOX") and a base substrate 16.
• BOX buried oxide
• active charge-sensitive circuit elements such as of individual memory cells 15 are formed in part by modifications made within the active semiconductor layer 14 of the SOI substrate 10. Additional structural layers are then formed over the active semiconductor layer 14 to form the working circuitry and circuit elements of the charge-sensitive device.
• the additional structural layers may include interconnect layers, insulating layers and/or additional circuit elements. In Fig. 1, these additional structural layers are not illustrated in detail for the sake of simplicity of illustration, but will simply be shown as a single circuit structure layer 18. It is noted, however, that the thickness of the additional structural layers that form the circuit structure layer 18 is generally much greater than the active semiconductor layer 12 or in the insulating layer 14. It is also common to include a passivation layer 20 on top of the circuit structure layer 18.
• a bonding layer 22 is first applied to a wafer containing at least one conventional semiconductor memory device of the type illustrated in Fig 1.
• the bonding layer 22 may be a thick epoxy (as just one example) that is used to provide a mechanical connection to the wafer for processing purposes.
• the back of the wafer is processed to remove the base substrate 16.
• Lapping or similar mechanical removal processes are suitable for removing an initial portion of the base substrate 16 while leaving a sufficient remaining thickness to protect the insulating layer 14 from mechanical damage.
• the remaining thickness of the base substrate 16 is then removed by a chemical removal process such as etching with etchants such as hydrazine, which that stops at the insulating layer 14, or by a timed etching removal process with etchants such as TMAH.
• a neutron conversion layer 24 is applied to the exposed insulating layer 14 as shown in Fig. 3.
• Sputter coating will produce lower thermal stresses in the circuit structure layer 18 during the deposition process, and, for fragile circuits, is therefore over, for example, high temperature processing preferred for fragile circuits.
• a barrier layer 26 for an example silicon nitride may be deposited to prevent diffusion of the neutron conversion material into the active semiconductor layer 12. This process insures that the neutron conversion layer 24 is located in close proximity to the active semiconductor layer 12.
• an additional stability layer such as epoxy may be applied to an outer layer if needed for additional mechanical stability.
• the composition of the neutron conversion layer 24 may be a boron metal or composition enriched with boron-10.
• a metal layer requires that an insulating layer 14 be present. For example, a neutron conversion layer 24 having a thickness of 1.8 microns and an insulating layer 14 having a thickness of 200 nm may be employed.
• borosilicate glass is compatible with application on silicon devices, is an insulator, and is commonly used for passivation layers.
• a BSPG with 5% boron to serve as the insulating layer 14 and also the neutron conversion layer 24 may also be applied directly to the active semiconductor layer 12 as shown in Fig. 4.
• Other Boron compounds or compositions may also be used.
• the neutron conversion layer may also incorporate lithium. Lithium metal is highly reactive and has been used to sensitize diodes, but has generally shortened sensor life.
• a stable material or composition such as 6 LiF may be employed as the neutron conversion layer 24 or alternatively as a second neutron conversion layer 28 formed over the first neutron conversion layer 24 as shown in Fig. 5 and 6.
• the alpha particles emitted by lithium have a longer range than those emitted by boron. For this reason, the use of two neutron conversion layers provides additional device sensitivity.
• the susceptibility of memory devices to SEU in general has been extensively studied for many years, and has revealed an important quantity called the critical charge (Qcrit).
• the Qcrit is the amount of charge a memory cell must accumulate in order to produce a bit error. It has long been known that finer lithographic line widths lead to smaller cells, to smaller cell charge holding capacity, and thus to smaller Qcrit for higher density memory devices.
• FIG. 7 A graph illustrating the Qcrit for unhardened silicon memory cells based on feature size is shown in Fig. 7.
• the typical 200 nm thickness of the active semiconductor layer 12 is much less than the range of the alpha particles generated in the neutron conversion layer 24. While the alpha will now reach the active semiconductor layer as required, only a fraction of the alpha energy will therefore be deposited in the active semiconductor layer 12 as it passes through that layer.
• the relevant quantity then becomes the amount of energy deposited along the track of the alpha particles, i.e., the Linear Energy Transfer (LET).
• the LET of an alpha particle from boron-10 traversing silicon is plotted in Fig. 8. (The initial energy of an alpha particle emitted by a boron-10 atom is approximately one and a half MeV.) It can be seen that the LET varies from about 1 to 1.5 Mev/(mg cm 2 ) over essentially the entire useful energy range of the alpha particle. Applying these limits to a 200 nm active semiconductor layer thickness gives a range of energy deposited in the active semiconductor layer 12 for normal incidence (the charge will increase for non-normal incidence with greater path lengths through the active silicon layer 12).
• the amount of alpha energy required (in MeV) per liberated charge (in pC) can be calculated. See “Calculation of Cosmic-Ray Induced Soft Upsets and Scaling in VLSI Devices", E.L. Peterson et al., IEEE Transactions on Nuclear Science, NS-29/6, Dec. 1982, 2055- 63.
• the energy is 22.5 MeV/pC giving a value of about 2 to 3 femtocouloubs deposited in the active layer at normal incidence.
• Fig. 7 can now be plotted as shown in Fig. 9 to include these limiting values for liberating charge in the active semiconductor layer. As shown in Fig.
• the alpha particle produced will - -at almost any point in its trajectory in silicon - - supply an amount of charge comparable to Qcrit for a 0.35 micron line width SOI RAM cell.
• the proximally placed neutron conversion layer 24 will produce alpha particles sufficient to cause SEU in conventional SOI RAM structures.
• the resulting structure will be referred to as a neutron sensitive random access memory (SNRAM).
• SNRAM neutron sensitive random access memory
• a neutron detector in accordance with the present invention can be utilized in a variety of applications. Just one notable application is in the area of monitoring the transportation of cargo.
• the low standby current draw of a device utilizing SRAM technology allows integrations of any desired duration to be performed without difficulty, as battery life can be on the order of years.
• the invention has been described with reference to certain preferred embodiments thereof.
• an additional SRAM circuit can be applied to a single-sided neutron sensitive SRAM to produce a "sandwich" sensor, wherein the center layer is the neutron converter and SRAM circuits are provided on either side of the converter.
• Other stacking geometries may also be used.
• the technology for multiple stacked layers of silicon microcircuits has already been demonstrated. See “Electrical Integrity of State-of-the-Art 0.13 ⁇ m SOI CMOS Devices and Circuits Transferred for Three- Dimensional (3D) Integrated Circuit (IC) Fabrication", K.W. Guarini et al., IEDM Technical Digest, IEEE, (2002).
• the invention has been described with reference to silicon memory SOI circuits, however, other semiconductor may be used to fabricate semiconductor-on-insulator RAM circuits and then can also be neutron-sensitized with one or more proximal neutron conversion materials in accordance with the invention to make neutron detectors. Still further, the invention is not limited to static RAM type memory devices, but can also be incorporated in other types of charge-sensitive memory devices.

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• 2003
  • 2003-10-20 US US10/693,847 patent/US7271389B2/en not_active Expired - Fee Related
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