WO2005074304A1 - Method and apparatus for measuring jitter - Google Patents
Method and apparatus for measuring jitter Download PDFInfo
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- WO2005074304A1 WO2005074304A1 PCT/US2005/001683 US2005001683W WO2005074304A1 WO 2005074304 A1 WO2005074304 A1 WO 2005074304A1 US 2005001683 W US2005001683 W US 2005001683W WO 2005074304 A1 WO2005074304 A1 WO 2005074304A1
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- jitter
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- edge position
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/20—Arrangements for detecting or preventing errors in the information received using signal quality detector
- H04L1/205—Arrangements for detecting or preventing errors in the information received using signal quality detector jitter monitoring
Definitions
- the present invention relates generally to data transmission, and more particularly to a method and apparatus for measuring jitter in data signals.
- a data signal is converted into a series of O's and I's called "bits".
- all the data signal bits that are sent down a transmission channel or transmission line have exactly the same length and spacing. This is important at the receiver end of the transmission channel so that the stream of I's and O's can be converted back into the original data signal.
- numerous factors in the transmission channel can alter or interfere with the desired precise timing of the data signal bits that are sent or transmitted. This applies to virtually all types of data communication, including telephone lines, computer networks, optical fibers, radio communication, and so forth.
- jitter measurement refers to analyzing the variations in the timing of the bits and determining the nature and the amount of the timing uncertainty - or jitter - that has been put onto the data bits by the time that the data signals get to the receiving end of the transmission line. The measurements reveal both the amplitude of the jitter and the frequency of the jitter. The amplitude of the jitter is the amount or size of the timing error in each of the bits.
- jitter amplitude is the difference between the time that the bit should have arrived and the time that the bit actually does arrive.
- the frequency of the jitter is a measurement that tells how quickly or how slowly the amount of jitter is changing.
- the frequency of the jitter is a measurement of how quickly the bits switch back-and-forth from being early at one moment, then late at another, then early again, and so forth.
- Jitter frequency is thus the frequency of the variations in the timing of the data bits.
- the jitter frequency is different from the frequency of the actual data bits in the transmission channel.
- the jitter frequency is normally from about 10Hz up to around several percent of the data bit frequency rate in the transmission channel.
- the required bandwidth for jitter measurement therefore, can be very large. For example, one specification for measuring jitter in a 155Mb per second signal would require the ability to measure jitter up to 1.3MHz. As indicated, there are many sources of jitter. One source is "data-related" jitter.
- the jitter is associated with the non-repetitive nature of the string of I's and O's in a data signal. For example, if a long string of O's is followed by a long string of I's, or vice versa, the result can be a slight, instantaneous transition point in the data signal timing. This can be caused by many factors, such as power supply noise on the transmitter, crosstalk from other signals, relays, reflections in the transmission line, and so forth. Other forms of jitter can appear within a multiplexed signal. One of these comes from combining separate source data signals into a single multiplexed signal.
- Tl generally refers to a high-speed data circuit line rate format that carries 24 user channels at a combined speed of 1.5 MHz.
- the timings of these different signal bits from the various different Tl signals may not be equally spaced within the multiplexed 155Mb/s channel.
- the different timing spacings then appear as jitter at the receiving end of the data channel.
- the present invention provides a method for measuring jitter.
- a signal under test is inputted to generate signal transition locations.
- a signal transition location is latched using a sampling clock signal, and the signal transition location is converted to a delay value.
- the delay value is converted to an edge position output, and a value of the edge position output is detected.
- FIG. 1 is an overview of a network in which a jitter measuring circuit is utilized;
- FIG. 2 is a block circuit diagram of the jitter measuring circuit of FIG. 1 according to the present invention;
- FIG. 3 is a block circuit diagram of the converter for converting the clock and delay to time values of FIG. 2; and
- FIG. 4 is a flow chart of a method for measuring jitter in accordance with the present invention.
- the present invention directed to measuring jitter in data signals, includes a sampled delay line consisting of cascaded delay elements.
- these delay elements are digital electrical buffers, and it will be understood that other appropriate devices that delay signals can also be used.
- the delay line is tapped along its length, between selected delay elements, so that the state of the line at each of the taps can be sampled.
- the sampling is controlled by a sampling clock that samples at a rate sufficiently fast to ensure that a signal state change does not pass from one end of the delay line to the other without being sampled at some point along the delay line.
- the line state is represented by either a 0 or a 1.
- the sampling can be performed by flip-flop circuits along the delay line that are clocked by the sampling clock. For example, if the signal changes state from 0 to 1, then the elements in the delay line will also change sequentially from 0 to 1 as the signal propagates through the delay line. In the embodiment shown and described, the elements change in order from the first to the last. If the delay line is sampled while the elements are changing, the earlier elements will have changed, while the later elements will not have changed.
- the number of elements that have changed is a measure of the timing of the state change.
- the samples can then be processed to determine which element the state change has reached at the time of the sampling clock. This is the "transition" element position, i.e., the point where the delay line samples have changed from one state to another. Since the delay of each delay element is known, the timing properties of the digital signal can be obtained. If, for example, the sampling clock is sampling at the signaling rate, then variations in the transition point correlate with, and thus characterize, jitter on the data signal under test. Furthermore, since jitter is usually defined as variations that have a frequency above about 10Hz, signal processing can be used, as taught herein, to remove the artifacts that are associated with a sampling clock that is different from the signaling rate.
- the present invention remembers the last transition point until a new transition occurs. If the timing variation between two consecutive samples becomes too large, an over- range function detects this condition. In that case, an indication is given that the incoming jitter is such that it is impractical to try to determine, without further information, which transition is from which data bit position. This is more likely to occur when jitter amplitudes are large.
- the amplitude of the jitter is the amount that the signal timing at the receiving end of the data transmission channel is varying. Jitter amplitude is normally measured as a percentage of a unit interval ("UI"), which is the length of one bit or data signal element.
- a jitter amplitude of 0.45 UI's would indicate that the timing at the receiving end of the data transmission channel is varying by approximately half a bit.
- amplitudes can range to 10's or lOO's of UI's.
- the frequency of the jitter is a measurement of how quickly or how slowly the amount of jitter is changing. There is a relationship between the jitter frequency and the difficulty of compensating for the jitter. Generally, the higher the jitter frequency, the smaller the number of UI's that can be managed.
- the analog circuitry includes a phase-lock loop that consists of an oscillator, a filter, and a phase comparator. This sets up a reference clock that is at the same frequency or a multiple of the frequency of the incoming data signal. Then, if the incoming data signal varies in timing, the reference signal generated by the phase-lock loop allows determination of the amount the incoming data signal timing has changed. The jitter measurement is then derived from this measured timing signal variation.
- Such analog circuitry unfortunately, has numerous shortcomings. For example, it is susceptible to signal noise, temperature variations, power supply noise, calibration problems, and so forth. Analog circuits also become ever increasingly difficult to design, fabricate, and maintain as their frequencies increase.
- Timing noise can actually be increased by the addition of timing noise to the signal under test. Because jitter measurement is usually carried out over a certain band of interest, typically from about 10Hz to about 1% or so of the signaling rate, timing noise introduced over a very wide band can increase resolution beyond the delay tap resolution. To accomplish this, the invention adds wideband noise to the data signal and then filters out noise above the band of interest, resulting in an increase in resolution. Noise can be added in several ways. For example, it can be added by using a delay device, by varying the threshold of sampling pins, by adding power supply noise to the delay line power supply, and so forth.
- All of these noise addition methods can be used, for example, in an FPGA implementation.
- filtering has been accomplished by using digital signal processing ("DSP") that is implemented in the FPGA alongside the delay line.
- DSP digital signal processing
- Such DSP filtering readily provides measurements that meet ITU-T specifications O.171/O/172 for Jitter Measuring Equipment.
- the delay line timing characteristics should be known.
- the timing of the delay line elements can be calibrated, or the timing can be known by design.
- the delay line was calibrated by generating two signals with known frequencies and a known frequency difference. The calibration signals were generated using a phase-locked loop.
- the jitter measuring circuit 102 measures the jitter on a signal 104 received by a receiver 106 from a transmission channel 108.
- the signal 104 originated in a transmitter 110 that inserted the signal 104 into the transmission channel 108 for reception by the receiver 106.
- a network 112 such as the Internet, may be present as part of the transmission channel 108.
- FIG. 2 therein is shown a block circuit diagram of the jitter measuring circuit 102 according to the present invention.
- the jitter measuring circuit 102 includes a block 202 that is a tapped delay line, a block 204 that is a sample register, a block 206 that is a priority encoder, a block 208 that is a converter for converting the clock and delay to time values, a block 210 that is an over-range detector, a block 212 that is DSP filters, a block 214 that is a peak-to-peak detector, a block 216 that performs root mean square ("RMS”) measurement calculations, and a block 218 that is a dither unit.
- the tapped delay line consists of cascaded delay elements 202A, 202B, ...202N.
- Each of the delay elements 202x provides a small amount of signal time delay ⁇ T.
- the delay elements 202x are connected sequentially, and thus the ⁇ T time delays in each delay element accumulate as a data signal moves through the block 202 tapped delay line. Accordingly, if there are n AT time delay elements, then n times ⁇ T is the total time delay from the beginning (at the delay element 202A) to the end (at the delay element 202N) of the block 202 tapped delay line.
- a data signal under test 220 which may be the signal 104 (FIG. 1), is supplied first to the block 218 dither unit and from there to the delay element 202 A at the beginning of the block 202 tapped delay line.
- the data signal under test 220 proceeds sequentially to the subsequent delay elements 202B...202N. Accordingly, inputting the data signal under test 220 into the block 202 tapped delay line will generate data signal transition locations in the block 202 tapped delay line as the data signal propagates therethrough.
- the several ⁇ T time delay intervals can each he different intervals.
- the jitter measuring circuit 102 includes circuitry that calibrates and accounts for the variations, if any, in the several ⁇ T time delays. By this means, the accuracy of the present invention is increased while the cost can be reduced by accepting greater ⁇ T tolerances in the block 202 tapped delay line.
- a sampling clock signal 222 is provided for the jitter measuring circuit 102 to synchronize the operation thereof.
- the frequency of the sampling clock signal 222 may be the same as that of the data signal under test 220, or as discussed above, may have a different frequency. Regardless of the frequency of the sampling clock signal 222, the total delay through the block 202 tapped delay line is configured to be greater than a cycle period of the sampling clock signal 222.
- Each of the ⁇ T time delays in the delay elements 202x is very small compared to the cycle period of the sampling clock signal 222. Thus, it is possible to accurately resolve the positions of the signal transitions (from 0 to 1 or vice versa) in the data signal under test 220 to within one ⁇ T time interval.
- the jitter measuring circuit 102 looks for the edge of the signal transition, either rising (going from 0 to 1) or falling (going from 1 to 0), since the circuit can measure jitter on rising edges, falling edges, and/or both edges. Accordingly, as a signal transition enters the block 202 tapped delay' line at the delay element 202A, it is delayed by the corresponding ⁇ T time delay and then similarly repeatedly delayed as it progresses up the delay chain to the delay element 202N. At the output of each delay element 202x, there is a tap 224x.
- taps each provide respective output signals reflecting the state of the data signal under test 220 at that corresponding position in the block 202 tapped delay line.
- the taps 224x are connected to the block 204 sample register to report the state of the data signal under test 220 at each of the delay elements 202x.
- Each of the taps 224x is accordingly connected from a respective delay element 202x to a respective flip-flop 204x in a series of flip-flops 204A, 204B, ...204N in the block 204 sample register.
- the flip-flops 204x thus correspond respectively to the delay elements 202x.
- the sampling clock signal 222 is also provided to the series of flip-flops 204x for the control thereof. Then, on each cycle of the sampling clock signal 222, the flip-flops 204x in the block 204 sample register sample the output from the block 202 tapped delay line on the taps 224x. That sampling captures the state of the tap 224x outputs from the block 202 tapped delay Une in the respective flip-flops 204x in the block 204 sample register. That output state is latched onto the block 204 sample register until the next cycle of the sampling clock signal 222.
- the state of the signal appearing on progressive taps 224x will change (for example, from 0 to 1 or vice versa).
- all of the delay elements toward the beginning of the block 202 tapped delay line and up to the position of the transition will have a value of 1.
- Those beyond the transition will not yet have changed and thus will continue to have a value of 0.
- the transition point will be captured by the block 204 flip- flops since they will latch with the respective I's and O's at that instant.
- the transition Since the total delay of the block 202 tapped delay line is greater than (longer than) the cycle period of the sampling clock signal 222, the transition will be somewhere within the block 202 tapped delay line and will be captured at its location therein as the transition location is then latched by the flip-flops 204x in the block 204 sample register. In a situation in which there is no jitter on the data signal under test 220, and in which the sampling clock signal 222 has the same frequency as the data signal, the transition points will always appear at the same places in the block 202 tapped delay line. If there is jitter on the data signal, such as from the transmission channel 108, then the jitter will appear as movement of the signal transition edges if the jitter has an amplitude greater than ⁇ T.
- the jitter measuring circuit 102 readily computes a corresponding offset and returns the correct jitter values and results. Since the total length of the block 202 tapped delay line, in terms of the time delay generated therein, is more than the cycle period of the sampling clock signal 222, each signal transition that passes through the block 202 tapped delay line will be captured by the block 204 sample register flip-flops.
- this is directly achieved by counting the number of the flip- flops 204x that have a value of 1 and reporting that number, since such a tally reflects just how far the signal edge has propagated. More specifically, if the flip-flop 204A has a value of 1, then a binary count can be made of all of the flip-flops from 204A up to the flip-flop having a value of 0. Conversely, if the flip-flop 204A has a value of 0, a count can be made up to the flip-flop 204x having a value of 1. The result is a single (binary) output number from the block 206 priority encoder that indicates at what tap 224x the transition was located when the sampling clock signal 222 triggered a sample cycle.
- the output from the block 206 priority encoder is supplied through a bus 226, which may be a parallel data bus, to the block 208 converter.
- the output from the block 206 priority encoder on the bus 226 is the delay value, and the block 208 converter combines this delay value with the sampling clock signal 222 to provide a time value output that indicates the time that the signal transition occurred.
- FIG. 3 therein is shown a more detailed block circuit diagram of the block 208 converter shown in FIG. 2.
- the block 208 converter includes a block 302 that is a calibrator, a block 304 that is a wrap-around detector, a block 306 that is a time/phase accumulator, and a block 308 that is a UI counter.
- the block 302 calibrator calibrates the ⁇ T time delay intervals for each of the delay elements 202x (FIG. 2), as described above, so that each of the taps 224x of the block 202 tapped delay line corresponds to an accurate time measurement.
- the block 304 wrap-around detector (FIG. 3) detects when the measured transition point from the block 202 tapped delay line (FIG. 2) has moved past the end (either beginning or ending, e.g., the bottom or top) of the block 202 tapped delay line.
- the block 304 wrap- around detector thus allows the length of the block 202 tapped delay line to be reasonable and not too expensive.
- the block 304 wrap-around detector accomplishes this by detecting and processing timing variations greater than the length of the block 202 tapped delay line by adding or subtracting one corresponding UI as appropriate, depending on the direction (up or down) of the wrap-around.
- the block 306 time/phase accumulator determines the phase (relative to one signal frequency cycle) of the incoming signal transition in relation to where the signal transition would be located in the absence of jitter. The phase determination is made by processing the several inputs and providing the measured phase of the edge position as an edge position output 310.
- One of the important functions of the block 208 converter is to accommodate consecutive O's or I's in the data signal under test 220.
- the block 308 UI counter counts the number of bits received from the sampling clock signal 222 and reports this count to the block 306 time/phase accumulator. With this information, the block 208 converter keeps count of the sampling clock cycles until another data signal transition actually comes along. The block 208 converter then predicts the expected edge position of the transition based on the number of corresponding data signal cycles that have passed. The block 208 converter then interpolates what the edge position shift is, if any, relative to the predicted edge position. Since the block 208 converter knows the sampling clock signal 222 frequency relative to the frequency of the data signal under test 220 (FIG.
- the block 302 calibrator (FIG. 3) can be recalibrated when desired, as may be appropriate, for example, in response to temperature and/or voltage variations.
- the data signal under test 220 (FIG. 2) is replaced by a known signal that causes the transition point on the block 202 tapped delay line to propagate through the block 202 tapped delay line at a known rate.
- the actual values that are then reported on the bus 226 are recorded in the block 302 calibrator so that the actual individual ⁇ T time delays of the corresponding delay elements 202x (FIG. 2) are accordingly correlated in the block 302 calibrator.
- the block 210 over-range detector (FIG. 2) analyzes and detects when the edge position output 310 that is reported by the block 208 converter has moved in excess of a set magnitude or fraction of a UI. For example, when an edge transition is detected, its edge position is reported by the block 208 converter as the edge position output 310. However, if a sequence of O's or I's occurs, the block 208 converter output will not change because there is no data edge in such an unchanging sequence. Therefore, the block 208 converter cannot update the edge position location.
- the block 210 over-range detector therefore contains a user definable threshold for warning when such an over-range event has occurred.
- the block 212 DSP filters enable the jitter amplitude to be measured in particular bandwidths.
- the block 212 DSP filters may be selected, for example, according to the need to meet particular specifications, thereby providing for proper measurements of amplitudes in respective bandwidths.
- the block 212 DSP filters are also configured to filter away high frequency noise and low frequency "wander".
- the outputs from the block 212 DSP filters are provided through an output 228 (for example, a data bus) to the block 214 peak-to-peak detector.
- the block 214 peak-to-peak detector measures the peak-to-peak values of the jitter, typically in terms of peak-to-peak UI's. For example, if a timing uncertainty moves back-and-forth by one UI, then this will constitute one UI peak-to-peak.
- the block 214 peak-to-peak detector thus measures how far the data transition edge jitters in one direction and how far it jitters in the other, subtracts the two, and outputs the result as a peak-to-peak UI height. This measurement may be repeated at set intervals, for example one second, and displayed to provide a dynamic output display of the peak-to-peak jitter behavior of the data signal under test 220.
- the outputs from the block 212 DSP filters are also provided through the output 228 to the block 216 RMS calculator.
- the block 216 RMS calculator analyzes the edge position output 310 to calculate and measure the RMS of the jitter signal by taking the position of the transition edge of the jitter signal, measuring the RMS value of that edge position during a set measurement interval (e.g., one second), and outputting the resultant RMS value thereof.
- This RMS measurement can be repeated over set measurement intervals (e.g., once per second) to provide a dynamic output display of the RMS jitter behavior of the data signal under test 220.
- the peak-to-peak and the RMS values are very useful for debugging telecommunications systems. For example, the peak-to-peak value represents the amplitude of the jitter, and the RMS value quantifies a value analogous to jitter "power".
- the block 218 dither unit adds accuracy and resolution to the jitter measurement by deliberately adding additional jitter (e.g., timing noise) onto the data signal under test 220 prior to injecting it into the measurement circuitry.
- additional jitter e.g., timing noise
- jitter values on the data signal under test 220 can be resolved to less than one ⁇ T value. This can be illustrated, for example, by considering a jitter present on the data signal under test 220 having a value less than one ⁇ T. In that case, many of the edge transition movements from one cycle of the sampling clock signal 222 to the next will occur within the anticipated or predicted delay element 202x for that sampling clock signal 222 cycle.
- This additional dither timing noise which is preferably at a high frequency relative to the jitter frequency, is now detected, combined with the data signal under test 220. Due to the increased signal excursion, the combined signal (dither plus data) is detected cyclically by several of the flip-flops 204x. The alternate detections are then averaged, resulting in a more accurate determination of the actual jitter.
- the high-frequency timing noise from the block 218 dither unit itself is then filtered out by the DSP filters in the block 212, so the dither signal never appears as part of the data output from the jitter measuring circuit 102.
- the block 218 dither unit can be implemented in a number of different ways. For example, a noisy power supply can be used for the jitter measuring circuit 102. Such a power supply will typically be less expensive, thereby reducing the cost of the jitter measuring circuit 102 while unexpectedly increasing the accuracy thereof.
- available integrated circuits can be put in series with the incoming data signal under test 220 to add programmable delay, and thus provide for affirmatively tuning the resolution of the jitter measuring circuit 102 as needed.
- the present invention can be implemented without analog circuitry. Therefore, significant savings can be realized in terms of cost, size, energy consumption, and so forth, because the entire jitter measuring circuit 102 can be implemented in a single FPGA. This is possible, in part, due to the discovery that the block 202 tapped delay line can be implemented in an FPGA by using the FPGA carry chain as a functional tapped delay line for the jitter measuring circuit 102.
- the FPGA carry chain is ordinarily used as an arithmetic logic accelerator.
- the carry chain cascaded multiplexers are configured in series to form the block 202 tapped delay line.
- the time delays that are then provided by the carry chain cascaded multiplexers are utilized to unexpectedly make possible the implementation of the entire jitter measuring circuit 102 in a single FPGA.
- FIG. 4 therein is shown a flow chart of a method 400 for measuring jitter in accordance with the present invention.
- the method 400 includes inputting a signal under test to generate signal transition locations in a block 402; latching a signal transition location using a sampling clock signal in a block 404; converting the signal transition location to a delay value in a block 406; converting the delay value to an edge position output in a block 408; and detecting a value of the edge position output in a block 410.
- the jitter measuring circuit 102 can also be utilized for measuring wander. This can be achieved by using a sampling clock signal 222 that has stability over long periods of time, such as might be available, for example, from an atomic clock source. Corresponding adjustments to the block 212 DSP filters would then be made to detect and pass signals in that bandwidth.
- the outputs from the block 214 peak-to-peak detector and/or the block 216 RMS calculator can be displayed, for example, on an oscilloscope, to provide a visual form of jitter display.
- the output signals from the block 212 DSP filters can be put through a fast Fourier transform ("FFT") to yield a spectrum signal for the jitter.
- FFT fast Fourier transform
- Such a signal can then be processed by a spectrum analyzer to reveal the frequencies at which the jitter is present.
- Such results can significantly assist in diagnosing jitter sources. For example, in one implementation, a 390kHz jitter was quickly isolated and then traced to an FPGA switching power supply that was switching at the same 390kHz frequency. The switching power supply was readily identified by the spectral fingerprint supplied by the FFT.
- the present invention can additionally be utilized with recording equipment to provide later playback and analysis of the jitter signals. This not only facilitates more careful evaluation of the jitter, but also enables comparisons and trend analyses over time of measurements made at different times on various systems. It could also be used for equipment failure analysis by recording during the failure and then replaying to analyze the causes of the failure.
- the present invention also enables automatic compensation by using the results of the jitter analysis to feed back into a signal compensator, thereby serving as a dynamic jitter attenuator.
- the present invention can also measure phase "hits", that is, sudden changes in the phase of the data signal.
- phase hit can occur in a multiplexing situation upon activation of an additional piece of equipment, such as adding several additional Tls into a multiplexed signal.
- the phase of the signal sometimes shifts suddenly when that happens.
- the present invention can also be used to measure how much noise there is in the power supply of an FPGA. With present FPGAs running at faster and faster rates, this is becoming a greater concern. Since the present invention can be implemented on a single FPGA, the invention can be loaded into the target FPGA and used as described above to measure the quality of the FPGA power supply. In still another embodiment, the present invention can be used to give very accurate time measurements in an environment where noisy measurements can be made at a high rate relative to the required output.
- the block 212 DSP filters are then calibrated to filter out the high-frequency noise, yielding an accurate time measurement, somewhat similarly to the processing and removal of the noise that was added by the block 218 dither unit.
Abstract
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CA2553570A CA2553570C (en) | 2004-01-23 | 2005-01-14 | Method and apparatus for measuring jitter |
JP2006551233A JP2007519005A (en) | 2004-01-23 | 2005-01-14 | Method and apparatus for measuring jitter |
EP05711649A EP1707017A4 (en) | 2004-01-23 | 2005-01-14 | Method and apparatus for measuring jitter |
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US53894504P | 2004-01-23 | 2004-01-23 | |
US60/538,945 | 2004-01-23 | ||
US10/826,198 | 2004-04-15 | ||
US10/826,198 US7236555B2 (en) | 2004-01-23 | 2004-04-15 | Method and apparatus for measuring jitter |
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US (1) | US7236555B2 (en) |
EP (1) | EP1707017A4 (en) |
JP (1) | JP2007519005A (en) |
KR (1) | KR20070004633A (en) |
CA (1) | CA2553570C (en) |
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- 2005-01-14 WO PCT/US2005/001683 patent/WO2005074304A1/en active Application Filing
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Also Published As
Publication number | Publication date |
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EP1707017A1 (en) | 2006-10-04 |
KR20070004633A (en) | 2007-01-09 |
TW200533101A (en) | 2005-10-01 |
TWI266493B (en) | 2006-11-11 |
EP1707017A4 (en) | 2008-03-19 |
US20050163204A1 (en) | 2005-07-28 |
US7236555B2 (en) | 2007-06-26 |
JP2007519005A (en) | 2007-07-12 |
CA2553570A1 (en) | 2005-08-11 |
CA2553570C (en) | 2011-09-20 |
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