WO2005074115A1

WO2005074115A1 - Position sensorless control method of permanent magnet synchronous motor with shunt in the inverter module

Info

Publication number: WO2005074115A1
Application number: PCT/JP2004/000958
Authority: WO
Inventors: Akira Matsuo; Subrata Saha; Kazushige Narazaki; Shunsuke Unehara; Toru Tazawa
Original assignee: Matsushita Electric Industrial Co., Ltd.
Priority date: 2004-01-30
Filing date: 2004-01-30
Publication date: 2005-08-11

Abstract

A closed loop position sensorless control of a three phase permanent magnet synchronous motor (1) driven by an inverter (11) with sinusoidal pulse width modulated drive is carried out by detecting phase currents with shunts (Rsh) placed in the emitter of the transistors (12L) in the lower legs of the inverter (11). The voltage drop across the three shunts (Rsh) are level shifted and amplified. Subsequently the amplified voltage is fed into the input port of an A/D converter (22) of a micro-controller (21). The sensing of the shunt voltages is started at the peak of the PWM carrier frequency when all the transistors (12L) in the lower leg are turned ON, and the values of the phase currents are retrieved from the sensed shunt voltages.

Description

DESCRIPTION

POSITION SENSORLESS CONTROL METHOD OF PERMANENT MAGNET SYNCHRONOUS MOTOR WITH SHUNT IN THE INVERTER MODULE

Technical field The present invention relates to a closed loop control of a permanent magnet synchronous motor with a sinusoidal pulse width modulated drive without using rotor position sensors or current transducers in the inverter circuit.

Background art Sinusoidal pulse width modulated drive system with closed loop position sensorless control for both the interior permanent magnet (IPM) and the surface permanent magnet (SPM) synchronous motors are now widely used as compressor drives for air-conditioners and refrigerators because of their superior drive efficiency and less vibration compared to a traditional 120° drive system.. A typical closed loop block diagram of the position sensorless control of a permanent magnet synchronous motor involving the vector control mode achieved by a micro-controller is shown in Fig. 23 (refer to Japanese Patent No. 3419725). The vector control drive for the permanent magnet synchronous motor 1 is normally used for the position sensorless control scheme because the d-q model of the permanent magnet synchronous motor 1 in the vector control mode helps to calculate the rotor position from the estimated back EMF. Different mathematical analysis and techniques had been proposed in the past about the calculation of the estimated back EMF and the method of retrieving the rotor position (θ) from it (refer to "An Extended Electromotive Force Model for Sensorless Control of Permanent-Magnet Synchronous Motors", Zhigian Chen, Mutuwo Tomita, Shinji Doki and Shigeru Okuma, IEEE Transactions on Industrial Electronics, Vol.50, No.2, April 2003, pp288-295.). However all the proposed techniques require the sensing of at least two current phases. The sensing of the current in the two phases is normally carried out with the help of a current transducer 91 as shown in Fig. 23.

Disclosure of Invention The present invention is directed to provide a position sensorless control method of the permanent magnet synchronous motor with simple and inexpensive hardware configuration. In the first aspect of the invention, a method is provided for the closed loop position sensorless control of a three phase permanent magnet synchronous motor driven by an inverter module with sinusoidal pulse width modulated drive. Each phase of the inverter module includes, transistors in lower and upper legs and a shunt placed in the emitter of the transistor in the lower leg. The inverter module is controlled by a micro-controller having an A/D converter connected with an input port. The method includes detecting the value of phase currents with the shunts placed in the emitter of the transistors in the lower legs in the following way: level shifting the voltage drop across the three shunts by +Vcc/2, where Vcc is the voltage of the mircor-controller power source; amplifying the level shifted voltage; and subsequently feeding the amplified voltage into the input port of the A D converter of a micro-controller. The sensing of the shunt voltages is started at the peak of the PVVM carrier frequency when all the transistors in the lower leg are turned ON, and the values of the phase currents are retrieved from the sensed shunt voltages. More specifically, the position sensorless control of the permanent magnet synchronous motor with sinusoidal pulse width modulated drive is achieved by sensing the phase currents with the help of three inexpensive shunts (R_S ) placed in the emitter of each lower leg of the inverter circuit (see Fig. 1). The voltage drop across the three shunts is fed into the input port of the A D converter of a micro-controller. The A/D converter is enabled when all the transistors in the lower leg are turned ON (i.e. during the null switching state '000' of the inverter). The ideal instant to start the sensing of shunt voltages is at the peak of the PWM carrier frequency for the micro-controller PWM output waveform (see Fig. 4). The voltage drop across the three shunts has both positive and negative values. Since the A/D converter within a micro-controller cannot sense negative voltage, the voltage across the three shunts is level-shifted and amplified with an operational amplifier circuit. An RC filter is also added at the output of the operational amplifier to avoid any voltage spikes in the shunt voltage. Below the 95% modulation of the sinusoidal PWM wave, any two out of the three shunt voltages sensed can be used to retrieve the two phase currents necessary for the position sensorless control of the permanent magnet synchronous motor. However, when the PWM carrier frequency lies between 2.75 to 10 kHz and the modulation of the sinusoidal PWM wave is above 95% i.e. near the rated speed and torque region and in the flux weakening region of the motor, for retrieving the two phase currents, the shunt voltage should be detected from the two phases whose instantaneous phase voltages is not maximum at that instant. In the second aspect of the invention, a method is provided for the closed loop position sensorless control of a three phase permanent magnet synchronous motor driven by an inverter module with sinusoidal pulse width modulated drive. Each phase of the inverter module includes, transistors in lower and upper legs and a shunt placed in a dc-link of the inverter module. The inverter module is controlled by a micro-controller having an A/D converter connected with an input port. The method includes detecting the value of phase currents with the shunt placed in the dc-link of the inverter module in the following way: amplifying the voltage drop across the dc-link shunt; and feeding the amplified voltage into the input port of the A/D converter of a micro-controller. In any PWM interval, the sensing of the dc-link voltage is started at the middle of the active inverter switching states, and the values of the phase currents is retrieved from the dc-link voltages sensed during the active inverter switching states. More specifically, the position sensorless control of the permanent magnet synchronous motor with sinusoidal pulse width modulated drive is achieved by sensing the voltage across an inexpensive shunt (Rdc) placed in the dc-link of the inverter circuit (see Fig. 8). It is seen that, during the active inverter switching states ('100' and '110'), there is a current flowing in the dc-link. Hence, the sensing of the dc-link voltage during these periods provides information of two phase currents (for example, U and W phases). The ideal instant to sense the dc-link voltage is at the middle of the active switching states (see Fig. 10C). However, during the two null inverter switching states ('000' and '111'), there is no current flowing in the dc-link, and hence there is no presence of dc-link voltage during this time. It should be noted that there are six active switching states of the inverter in one electrical cycle. During all these six active inverter switching states, a current flows through the dc-link shunt and the voltage drop across it are always positive. A double-sided PWM modulation strategy always provides information about two phase currents twice during every PWM interval. Hence, any position sensorless control algorithm involving 3 phase to 2 phase current transformation can be easily carried out by sensing the voltage across a dc-link shunt in the inverter circuit after suitable amplification and filtering. However, the proposed current sensing strategy by a dc-link shunt has severe limitations when the duty cycles of the two phases are almost equal. This type of situation will arise during low motor speed when the modulation index is low and during every 60° interval in an electrical cycle when the two phase voltages at a particular instant are nearly equal. When the motor speed is low (i.e. when the modulation index is low), very small amount of time is available to sense the dc-link voltage accurately during both the active switching states of the inverter. When the two phase voltages at a particular instant are nearly equal, the dc-link voltage can be always perfectly sensed in one of the active inverter switching states whereas during the other active inverter switching state the dc-link voltage cannot be sensed because of insufficient time. Hence, during low motor speed and at the instant of an electrical cycle when the two phase voltages are nearly equal the two phase currents cannot be correctly measured during one PWM interval by the dc-link shunt strategy and hence any position sensorless control algorithm will fail. Therefore, to measure the two phase currents at every PWM interval by the dc-link shunt strategy the sinusoidal PWM waveform at particular instants is modified so that a minimum time period T_m is always available for the sensing of the dc-link shunt voltage (see Figs. 11 C and 12C). The modification of the sinusoidal PWM waveform can be carried out in two ways such as the 'Time period modification' and the 'PWM compensation' schemes. In the 'Time period modification' scheme the effective sinusoidal phase voltage is changed, whereas in the 'PWM compensation' scheme the effective sinusoidal phase voltage is not altered.

Brief description of drawings Fig. 1 shows a configuration of the motor driving apparatus with three inexpensive shunts (R_Sh) placed in the emitter of each lower leg of the inverter circuit according to the first embodiment of the present invention. Fig. 2 shows a configuration of the level-shifting and amplification circuit for the shunt voltages before feeding into the input port of an A/D converter in the first embodiment. Fig. 3 shows six active switching states of the inverter. Fig. 4 shows the starting of sensing of shunt voltages at the peak of PWM carrier frequency. Fig. 5A shows U-phase current and Fig. 5B shows a typical U-phase shunt voltage during the null switching state O00'. Figs. 6A to 6C are views explaining the minimum turn-on duty (Ton)min of the lower transistors to accurately sense the shunt voltage. Figs. 7A to 7C show the phase voltage waveforms during the flux-weakening region of the motor when the modulation of the phase voltage waveforms is 100 % for a time period of 60° electrical. Fig. 8 shows a configuration of the motor driving apparatus with an inexpensive shunt R_dc placed in the dc-link of the inverter circuit according to the second embodiment of the present invention. Fig. 9 shows a configuration of the amplification and filtering circuit for the dc-link shunt voltage before feeding in to the input port of an A/D converter in the second embodiment. Figs. 10A to 10C show typical PWM base drive waveforms for the upper leg of the transistors with the corresponding dc-link voltage in one

PWM interval. Fig. 11 A shows a PWM carrier frequency waveform with three phase voltage reference, Fig. 11 B shows the PWM base drive waveforms for the upper leg of the transistors with the corresponding dc-link voltage in one PWM interval during low motor speed, Fig. 11 C shows that the sinusoidal PWM waveform at particular instants is modified so that a minimum time period T_m during active switching states is always available for the sensing of the dc-link shunt voltage when the motor speed is low. Fig. 12A shows a PWM carrier frequency waveform with three phase voltage reference, Fig. 12B shows the PWM base drive waveforms for the upper leg of the transistors with the corresponding dc-link voltage in one PWM interval when the two phase voltages at a particular instant are nearly equal, Fig.

12C shows that the sinusoidal PWM waveform at particular instants is modified so that a minimum time period T_m during active switching states is always available for the sensing of the dc-link shunt voltage when the two phase voltages at a particular instant are nearly equal. Fig. 13A shows a PWM carrier frequency waveform with three phase voltage reference, Fig. 13B shows the PWM base drive waveforms for the upper leg of transistors with the phase currents at the instant to for a double sided PWM modulation strategy. Figs.14A and 14B show the relation between minimum time period T_m and height H of the carrier frequency waveform. Fig. 15A shows a PWM carrier frequency waveform with three phase voltage reference, Fig. 15B shows the double sided time period modification scheme of the PWM waveform keeping Vi constant when the reference phase voltage magnitudes V_u ^*, V_v* and V_w* are estimated in every half cycle of the PWM, Fig. 15C shows the double sided time period modification scheme of the PWM waveform keeping V₂ constant when the reference phase voltage magnitudes V_u ^*, V_v* and V_w* are estimated in every half cycle of the PWM, Fig. 15D shows the double sided time period modification scheme of the PWM waveform keeping V₃ constant when the reference phase voltage magnitudes V_u ^*, V_v* and V_w* are estimated in every half cycle of the PWM. Fig. 16A shows a PWM carrier frequency waveform with three phase voltage reference, Fig. 16B shows the double sided time period modification scheme of the PWM waveform keeping Vι constant when the reference phase voltage magnitudes V_u ^*, V_v* and V_w* are estimated in every full cycle of the PWM, Fig. 16C shows the double sided time period modification scheme of the PWM waveform keeping V₂ constant when the reference phase voltage magnitudes V_u\ V_v* and V_w* are estimated in every full cycle of the PWM, Fig. 16D shows the double sided time period modification scheme of the PWM waveform keeping V₃ constant when the reference phase voltage magnitudes V_u ^*, V_v* and V_w* are estimated in every full cycle of the PWM. Figs. 17A to 17C explain that in every alternate PWM half cycle two phase currents can be detected for the single sided time period modification scheme. Fig. 18A shows a PWM carrier frequency waveform with three phase voltage reference, Fig. 18B shows the single sided time period modification scheme of the PWM waveform keeping Vi constant when the reference phase voltage magnitudes V_u ^*, V_v* and V_w* are estimated in every full cycle of the PWM, Fig. 18C shows the single sided time period modification scheme of the PWM waveform keeping V₂ constant when the reference phase voltage magnitudes V_u ^*, V_v ^* and V_w ^* are estimated in every full cycle of the PWM, Fig. 18D shows the single sided time period modification scheme of the PWM waveform keeping V₃ constant when the reference phase voltage magnitudes V_u ^*, Vv* and V_w* are estimated in every full cycle of the PWM. Figs. 19A to 19C explain the double sided PWM compensation scheme of the phase voltage waveforms keeping V₂ constant when the reference phase voltage magnitudes V_u\ V_v* and V_w* are estimated in every PWM cycle. Figs. 20A to 20C explain the double sided PWM compensation scheme of the phase voltage waveforms keeping V₂ constant when the reference phase voltage magnitudes V_u ^*, V_v* and V_w* are estimated in every alternate PWM cycle. Figs. 21 A and 21 B explain the single sided PWM compensation scheme of the phase voltage waveforms keeping V₂ constant when the reference phase voltage magnitudes V_u ^*, V_v* and V_w* are estimated in every PWM cycle. Fig. 22 shows an exemplary configuration of a compressor drive for driving a permanent magnet synchronous motor coupled to a compressor with a sinusoidal pulse width modulated drive. Fig. 23 shows a typical closed loop block diagram of the position sensorless control of a permanent magnet synchronous motor.

Best mode for carrying out the Invention The position sensorless control of the permanent magnet synchronous motor according to the present invention is described before with reference to the attached drawings.

First Embodiment Fig. 1 shows a configuration of motor driving apparatus of a permanent magnet motor according to the first embodiment of the invention. The apparatus includes an inverter circuit (module) 11 providing a driving power to a permanent magnet motor 1 , a base drive circuit 20 driving the inverter circuit 11, a micro-controller 21 controlling the base drive circuit 20, and amplifier and filter circuits 15. The inverter 11 has six transistors for three phases (U, V, W phases). Each phase of the inverter circuit 11 includes serially connected transistors 12U and 12L, as switching elements, on its lower and upper legs. The inverter circuitH has in each phase a shunt register R_Sh inserted between the emitter of the lower transistor 12L and a ground terminal. The inverter circuit 11 converts a DC power from the dc-link capacitor 13 into a driving power to drive the motor 1. The micro-controller 21 includes an A D converter 22 which converts an analog signal from the shunts registers R_sh via the amplifier and filter circuit 15 to a digital signal. The micro-controller executes the position sensorless control algorithm and generates PWM control signals to make the inverter circuit 11 supply the desired driving power to the motor 1. The base drive circuit 20 receives the control signal from the micro-controller 21 to generate base drive signals to drive the switching elements 12 in the inverter circuit 11. Fig. 2 shows a configuration of the amplifier and filter circuits 15. Since the A/D converter 22 within the micro-controller 21 cannot sense negative voltage, the voltage across the three shunts R_sh is level-shifted and amplified with an operational amplifier circuit as shown in Fig. 2. An RC filter 16 is also provided in each phase at the output of the operational amplifier 17 to avoid any voltage spikes in the shunt voltage. It should be noted that there are six active switching states of the inverter 11 in one electrical cycle, as shown in Fig. 3. In the drawing, the active switching state is expressed by using numerals in three digits such as '010' and '110'. The three digits represent the switching status of transistor on the upper leg for U-phase, V-phase, and W-phase, respectively, in this order. The value '1' means the status in that the switch 12U on the upper leg is turned ON while the switch 12L on the lower leg is turned OFF. The value '0' means the status in that the switch 12U on the upper leg is turned OFF while the switch 12L on the lower leg is turned ON. For example, '100' means that the upper leg switch 12U in U-phase is turned ON and the lower leg switches 12U in V- and W- phase are turned ON. According to the first embodiment, a position sensorless control of the permanent magnet synchronous motor with sinusoidal pulse width modulated drive is achieved by sensing the phase currents with the help of three inexpensive shunts (R_sn) placed in the emitter of the transistor 12 of each lower leg of the inverter circuit 11 as shown in Fig. 1. The voltage drop across the three shunt registers R_Sh is fed into the input port of the A D converter 22 of the micro-controller 21. The A/D converter 22 is enabled when all the transistors 12L in the lower leg are turned ON i.e. during the null switching state '000' of the inverter 11. Hence, the ideal instant to start the sensing of shunt voltages is at the peak of the PWM carrier frequency for the micro-controller PWM output waveform as shown in Fig. 4. The voltage drop across the three shunts Rs_h has both positive and negative values. A typical U-phase shunt voltage during the null switching state '000' is shown in Fig. 5B where it can be seen that the U-phase shunt voltage is positive for negative U-phase current (see Fig. 5A) whereas the U-phase shunt voltage is negative for positive U-phase current. Below the 95% modulation of the sinusoidal PWM wave, any two out of the three phase shunt voltages sensed can be used to retrieve the two phase currents necessary for the position sensorless control of the permanent magnet synchronous motor 1. However, when the PWM carrier frequency lies between 2.75 to 10 kHz and the modulation of the sinusoidal PWM wave is above 95% i.e. near the rated speed and torque region and in the flux weakening region of the motor 1 , for retrieving the two phase currents we should always detect the shunt voltage from the two phases whose instantaneous phase voltages is not maximum at that instant. The value of the shunts R_sh placed in the three transistors 12L on the lower leg should be chosen so that the total power dissipation across them is between 0.3 % and 0.5% of the input power at the rated load condition. The same is true for a dc-link shunt to be described in the second embodiment. If a low shunt value is chosen to keep the power dissipation much below 0.3 %, a high amplifier gain is needed which will limit the slew rate of the operational amplifier 17. The amplifier gain is kept normally less than or equal to 10. The voltage across the shunt Rs_h has to be filtered from any inductive voltage spikes before feeding it to the input port of a micro-controller 21. The A/D converter 22 within the micro-controller 21 should be of at least 10 bits for a high sensitivity of the current measured. This is very essential for any position sensorless control algorithm, which involves 3 to 2 phase current transformation. The micro-controller 21 used for implementing the position sensorless algorithm is preferably of at least 16 bits which can perform 32 bit multiplication. The micro-controller 21 as well as the operational amplifier 17 is operated with a 5 V power supply. The more detail action of the motor driving apparatus of this embodiment is described below. As described above, in this embodiment, the sensing of the two phase currents for any position sensorless control technique for the permanent magnet synchronous motor 1 with sinusoidal pulse width modulated drive can be achieved by inexpensive shunts (R_Sh) placed in the emitter of each lower leg transistor 12L of the inverter 11 as shown in Fig. 1. When all the transistors 12L in the lower leg of the inverter 11 are turned ON, that is, during the null switching state '000' in every PWM interval, the phase currents simultaneously flow through all the three shunts R_srι. During the null switching state '000', the current in the motor windings freewheels through the lower leg transistors 12L as well as the reverse diodes 14. In the null switching state when a phase current is negative, the transistors 12L for that corresponding phase in the lower leg of the inverter 11 conducts to provide a positive shunt voltage value. On the other hand, when a phase current is positive, the reverse diodes 14 for that corresponding phase in the lower leg of the inverter 11 conducts to provide a negative shunt voltage value. Since the A/D converter 22 within a micro-controller 21 cannot sense negative voltage, the voltage across the three shunts Rs_h is level-shifted and amplified with an operational amplifier 17 before feeding it into the input port of an A/D converter 22 of the micro-controller 21 as shown in Fig. 2. The A D converter 22 is enabled for sensing all the three shunt voltages during the null switching state '000' of a PWM interval. The diode 14 together with the RC filter circuit 16 at the output of the operational amplifier 17 do not allow the presence of any inductive voltage spikes at the input port of the A/D converter 22. The values of R and C depend on the inductance of the motor winding and normally a shunt voltage rise time between 5 and 10 μs is selected. The ideal instant to start the sensing of the three shunt voltages is at the peak of the PWM carrier frequency and hence only once in a PWM interval all the three phase currents can be detected simultaneously. Therefore, in the position sensorless control algorithm of a permanent magnet synchronous motor involving shunts R_Sh connected in the emitter of each transistor 12L in the lower leg of the inverter 11, the three phase to two phase current transformation, the estimation of the reference voltages V_u ^*, V_v ^* and V_w ^* and the calculation of the rotor position θ are carried out once in every PWM interval. When the modulation of the sinusoidal PWM wave is below 95 % any two out of the three shunt voltages sensed can be used to retrieve the two phase currents. However, when the PWM carrier frequency is between 2.75 and 10 kHz and the modulation of the sinusoidal PWM is above 95 % i.e. near the rated speed and torque region and in the flux-weakening region of the motor, it is not possible to sense all the three shunt voltages accurately. In such a case, at the instant when the instantaneous turn on duty of the upper transistors 12U for a particular phase is greater than 95 %, the detected shunt voltage for that phase do not correspond to correct value because a minimum turn-on duty of the lower transistor is needed to accurately sense the shunt voltage. The minimum turn-on duty (T_on)min of the lower transistors 12L as shown in Fig. 6 results taking into account the sampling time (t_s), the dead time between the upper and lower leg transistors (t_d) and the shunt voltage rise time (t_r). Typical values of the minimum turn-on duty (T_on)min of the lower transistors 12L lie between 10 to 20 μs. Hence, for retrieving the two phase currents when the modulation of the sinusoidal PWM waveform is above 95 %, we should always detect the shunt voltage from the two phases whose instantaneous phase voltages is not maximum at that instant. Figs. 7A to 7C show the phase voltage waveforms during the flux-weakening region of the motor 1 when the modulation of the phase voltage waveforms is 100 % for a time period of 60° electrical. For the periods I, II and III in an electric cycle as shown in Figs. 7Ato 7C, the two phase currents should be retrieved from the detected shunt voltages for the phase V and W, W and U and U and V in a sequence respectively. From Fig 2, the voltage sensed by the A D converter 22 can be mathematically expressed as,

V_AD ~ x^X^- (1) R₃ +R₄ R₂

In the circuit shown in Fig. 2, the resistances are so selected such that Ri = R₃ and R₂ = R₄. Therefore the A/D converter input voltage V_AD can be simplified as, V_AD = V_Cc/2 + V_sh ^* R₁ /R₂ (2) where, 'V_cc' is the power supply voltage (5V) and 'V_Sh' is the voltage across the shunt Rsh connected to the emitter of each lower leg transistor 12L in the inverter 11. Considering the ideal condition, for maximum instantaneous positive phase current (l_Sh = Imax), the A/D converter input voltage VAD = 0V and for maximum instantaneous negative phase current (l_Sh = -Imax), the A/D converter input voltage V_AD = 5V. The shunt voltages sensed by the A D converter 22 are finally reversed within the micro-controller 21 to retrieve the actual value of current. Now from equation (2), the value of the shunt R_Sh can be given as, R_sh= 2.5/(l_max)*A_F (3) where, AF is the amplification factor given by the ratio of the resistance Ri and R₂. The total power dissipation across the three shunts R_Sh can be approximated as, Pioss = 1.5*l_L ²*Rsh (4) The value of the shunt R_Sh is calculated from equations (3) and (4) such that the amplification factor (AF) is less than or equal to 10 and the total power dissipation P|_0SS across the three shunt R_Sh lies between 0.3 % and 0.5% of the input power when rated load current (lι_) of the motor 1 flows through the shunt Rs . In summary, for the current sensing strategy with shunts R_sh placed in each lower leg of the transistor 12L, the voltages across each of them are sensed by an A/D converter 22 when all the lower transistors 22 are turned ON i.e. during the null switching state '000' of the inverter 11. Hence, with this scheme all the phase currents can be detected only once during each PWM interval. The ideal instant to start the sensing of the shunt voltage by the A/D converter 22 is at the peak of the PWM carrier frequency. When the modulation of the sinusoidal PWM waveform is below 95 %, any two out of the three shunt voltages sensed can be used to retrieve the two phase currents. However, when the PWM carrier frequency is between 2.75 and 10 kHz and the modulation of the sinusoidal PWM waveform is above 95 %, it is not possible to sense all the three shunt voltages accurately. In such a case, at the instant when the instantaneous turn on duty of the upper transistors 12U for a particular phase is greater than 95 %, the sensed shunt voltage of that phase do not correspond to correct value because a minimum turn-on duty of the lower transistor 12L is needed to accurately sense the shunt voltage R_sh. Hence, for retrieving the two phase currents when the modulation of the sinusoidal PWM is above 95 %, the shunt voltage always should be detected from the two phases whose instantaneous phase voltage is not maximum at that instant.

Second Embodiment According to the second embodiment, a shunt is provided in the dc-link of the inverter circuit 11 as shown in Fig. 8. The position sensorless control of the permanent magnet synchronous motor with sinusoidal pulse width modulated drive in this embodiment is achieved by sensing the voltage across the shunt (Rdc) placed in the dc-link of the inverter circuit 11. Typical PWM base drive waveforms for the upper leg of the transistors 12U with the corresponding dc-link voltage in one PWM interval at a particular instant is shown in Fig. 10B. It is seen from Figs. 10A to 10C that during the active inverter switching states '100' and '110', there is a current flowing in the dc-link, and hence the sensing of the dc-link voltage during these periods provides information of two phase currents (U and W in the present case). The ideal instant to sense the dc-link voltage is at the middle of the active switching states as shown in Fig. 10C. However, during the two null inverter switching states '000' and '111', there is no current flowing in the dc-link and hence, there is no presence of dc-link voltage during this time. It should be noted again that there are six active switching states of the inverter in one electrical cycle and they are shown in Fig. 3. During all these six active inverter switching states current flows through the dc-link shunt and the voltage drop across it is always positive. A general relationship between the inverter switching states and the measured phase current from the sensed dc-link voltage is shown in Table 1. Table 1

Figs. 10A to 10C also describe a double-sided PWM modulation strategy which provides information about two phase currents twice during every PWM interval. Hence, any position sensorless control algorithm involving 3 phase to 2 phase current transformation can be easily carried out by sensing the voltage across a dc-link shunt in the inverter 11 after suitable amplification and filtering as shown in Fig. 9. However, the proposed current sensing strategy by a dc-link shunt has severe limitations when the duty cycles of the two phases are almost equal. This type of situation will arise during low motor speed when the modulation index is low and during every 60° interval in an electrical cycle when the two phase voltages at a particular instant are nearly equal. Fig. 11 B shows the PWM base drive waveforms for the upper leg of the transistors 12U with the corresponding dc-link voltage in one PWM interval during low motor speed (i.e. when the modulation index is low). In this case, very small amount of time is available to sense the dc-link voltage accurately during both the active switching states of the inverter 11. Fig. 12B shows the PWM base drive waveforms for the upper leg of the transistors 12U with the corresponding dc-link voltage in one PWM interval when the two phase voltages at a particular instant are nearly equal. In this case, the dc-link voltage can be always perfectly sensed in one of the active inverter switching states whereas during the other active inverter switching state the dc-link voltage cannot be sensed because of insufficient time. Hence, during low motor speed and at the instant of an electrical cycle when the two phase voltages are nearly equal the two phase currents cannot be correctly measured during one PWM interval by the dc-link shunt strategy and hence any position sensorless control algorithm will fail. Therefore, to measure the two phase currents at every PWM interval by the dc-link shunt strategy the sinusoidal PWM waveform at particular instants is modified so that a minimum time period T_m is always available for the sensing of the dc-link shunt voltage as shown in Figs. 11 C and 12C. The modification of the sinusoidal PWM waveform can be carried out in two ways such as the 'Time period modification' and the 'PWM compensation' schemes. In the 'Time period modification' scheme the effective sinusoidal phase voltage is changed whereas in the 'PWM compensation' scheme the effective sinusoidal phase voltage is not altered. The more detail action of the motor driving apparatus of this embodiment is described below. During all the active inverter switching states ('100', '110701070117001'and'IOI'), the dc-link current equals any of the phase current of the motor. On the other hand, during the null switching states ('000' and '111'), the dc-link current carries no information of the phase current. The double-sided PWM modulation strategy as shown in Figs. 10A to 10C always provides information about two phase currents during every half cycle interval of the PWM carrier frequency. The ideal instant to sense the dc-link voltage is at the middle of the active inverter switching states. It is seen from Figs. 13A and 13B that with this current sensing strategy, the phase currents are not detected simultaneously but a delay (D) exists between the detection of two phase currents in every PWM period. Such delays in the current sensing of two phases do not affect the position sensorless control of a permanent magnet synchronous motor. For the double sided PWM modulation strategy, referring to Figs. 13A and 13B, the phase currents at the instant t_c can now be given as, lι(to) = ldo(tι); (tc) = l_dc(t₂); l₃(tc) = -[lι(tc) + l₂(t_c)] where, lι=l_u, l₂=lw and l₃=l_v in the present case. Hence, in the position sensorless control algorithm of permanent magnet synchronous motors involving the phase current sensing with the aid of the dc-link shunt R_dc and the double sided PWM modulation strategy, the phase currents detected during the half cycle PWM interval T(n) is always used in the next half cycle PWM interval T(n+1 ) for the estimation of the rotor position. Since the current is not constant during the active switching state, the ideal value of phase current at the instant t_c can be expressed as the average of the two phase currents on either side of the PWM half cycle such as lι(to) = [Idc(ti) + l_dc(t₄)]/2; l₂(tc) = [l_dc(t₂) + ldc(t₃)]/2. However, the knowledge of the currents Idc(t3) and Idc(t4) is not available at t_c and hence the phase currents at t_p are defined with a half cycle delay such as, li(t_P) = [Idc(ti) + ldc(t₄)]/2; l₂(t_P) = [l_dc(t₂) + l_dc(t₃)]/2. Therefore, in an alternative scheme of phase current detection via the dc-link shunt R_dc and double sided PWM modulation strategy, the phase currents detected during the two consecutive half cycle PWM intervals T(n) and T(n+1) are averaged and used in the next half cycle PWM interval T(n+2) for the position sensorless control algorithm of a permanent magnet synchronous motor. The voltage drop across the dc-link shunt R_dc is always positive and is fed into the input port of the A/D converter 22 after suitable amplification and filtering as shown in Fig. 9. The amplification factor AF of the operational amplifier 17 is given by (1+Rι/R₂) and should be limited to 10 similar to the first embodiment. The power dissipation across the dc-link shunt R_dc should also lie between 0.3 % and 0.5% of the input power when rated load current (L) of the motor 1 flows through it. The proposed current sensing strategy by the dc-link shunt Rdc has severe limitations when the duty cycles of the two phases are almost equal. Therefore, to measure the two phase currents by the dc-link shunt strategy at every PWM interval, the sinusoidal PWM waveform at particular instants is modified so that a minimum time period T_m is always available for the sensing of the dc-link shunt voltage during the active switching state of the inverter 11. T_m is obtained by sum of the sampling time (t_s), the dead time (t_d) between the upper and lower leg transistors 12U and 12L and the shunt voltage rise time (t_r), as shown in Figs. 14A and 14B. Typical values for the minimum time period T_m lie between 10 to 20 μs. The minimum time period T_m required for accurate phase current detection is directly related to the height H of the carrier frequency waveform as shown in Figs. 14A and 14B. Hence, for every minimum time period T_m, there is a ΔH_mj_n which is expressed as follows: ΔHmin = 2^*fc*H^*T_m (5) The modification of the sinusoidal PWM waveform can be carried out in two ways such as the 'Time period modification' and the 'PWM compensation' schemes. The algorithms for the 'time period modification' and the 'PWM compensation' schemes are discussed below, respectively.

(A. Time Period Modification) In the time period modification scheme, a width or time period of the base drive signal (PWM waveform) is modified so that a minimum time period T_m is included for each of the two active switching states during a full cycle PWM interval of the carrier frequency at least once by modifying the PWM waveform. Hence, in this scheme the effective sinusoidal voltages for the three phases are changed. The time period modification scheme includes two strategies such as the double sided and the single sided time period modification, which are described below.

(A-1. Double Sided Time Period Modification) In the double sided time period modification strategy of the PWM waveform, a minimum time period T_m is included in each active switching states during every half cycle interval of the PWM carrier frequency. As shown in Figs. 13A and 13B, the current is sampled at the center of the active switching states, and in every PWM half cycle two phase currents can be detected. The position sensorless control of the permanent magnet synchronous motor involving the double-sided time period modification of the PWM waveform takes place in the following two ways. The first scheme include sensing the two phase current in every half cycle of the PWM. In this case, the three phase to two phase current transformation, rotor position θ calculation and finally the estimation of the magnitude of the reference phase voltages V_u*, V_v ^* and V_w* are also carried out in every half cycle of the PWM interval. Hence, in every half cycle PWM interval, the magnitude of the reference phase voltages V_u*, V_v ^* and V_w* are compared, and Vi is assigned to the maximum value, V₂ to the middle value, and V₃ to the minimum value. In this scheme, one of the phase voltages out of V_{1 :} V₂ or V₃ is kept fixed and the other two reference phase voltages are altered in every half cycle of the PWM if a minimum time period T_m is not available for the sensing of the dc-link voltage during the active switching states of the inverter. The following logical steps are followed in every half cycle of the

PWM sequentially when Vi is kept fixed. It should be noted that a suffix 'n' in Vjn (i=1 , 2, 3) means a newly set value. i) The difference between Vi and V₂ is calculated, ii) lf (V₁-V₂) < ΔHmin, then the new modified value of V| can be set as V_2n = Vi -ΔH_min. On the other hand, if (Vι-V₂) > ΔH_min, then V_2n = V₂. iii) The difference between V _n and V₃ is calculated, iv) If |(V_2n-V₃)| < ΔH_min, then the new modified value of V₃ can be set as V_3n = V_2n -ΔHmin. On the other hand, if |(V_2n-V₃)| > ΔHmin, then V_3n = V₃. v) Modified values of V_u ^*, V_v* and V ^* are calculated again from Vi ,

V_2n and V_3n. The double sided time period modification scheme of the PWM waveform keeping i constant when the reference phase voltage magnitudes V_u ^*, V_v* and V_w* are estimated in every half cycle of the PWM is shown in Fig. 15B. The following logical steps are followed in every half cycle of the PWM sequentially when V₂ is kept fixed. i) The difference between i and V₂ is calculated. ii) lf (V₁-V₂) < ΔHmm, then the new modified value of V₂ can be set as |_n = V₂ +ΔH_min- On the other hand if (Vι-V₂)>ΔHmin, then V_1n = VL iii) The difference between V₂ and V₃ is calculated, iv) If (V₂-V₃) < ΔHmin, then the new modified value of V₃ can be set as V_3n = V₂ -ΔH_min. On the other hand, if (V₂-V₃) > ΔHmin, then V_3n = V₃. v) Modified values of V_u ^*, V * and V_w* are retrieved from Vι_n, V₂ and

V_3n. The double sided time period modification scheme of the PWM waveform keeping V₂ constant when the reference phase voltage magnitudes V_u ^*, V_v* and V_w* are estimated in every half cycle of the PWM is shown in Fig. 15C. The following logical steps are followed in every half cycle of PWM sequentially when V₃ is kept fixed. i) The difference between V₂ and V₃ is calculated. ii) lf (V₂-V₃) < ΔHmin, then the new modified value of V₂ can be set as V_2n = V₃ +ΔH_min. On the other hand, if (V₂-V₃) > ΔH_min, then V_2n = V₂. iii) The difference between Vi and V_2n is calculated. iv) lf |(VrV_2n)| < ΔHmin, then the new modified value of Vi can be set as Vι_n = V_2n +ΔH in- On the other hand, if |(Vι-V_2n)| > ΔH_min, then Vm = Vi. v) Modified values of V_u ^*, V_v* and V_w* are retrieved from Vm, V_2n and V₃. The double sided time period modification scheme of the PWM waveform keeping V₃ constant when the reference phase voltage magnitudes V_u ^*, Vv* and V_w* are estimated in every half cycle of the PWM is shown in Fig. 15D. The second scheme for the position sensorless control of the permanent magnet synchronous motor involving the double sided time period modification of the PWM waveform includes sensing the two phase current only once in every full cycle of the PWM. Hence, in this case, the three phase to two phase current transformation, rotor position θ calculation and finally the estimation of the magnitude of the reference phase voltages V_u*, V_v ^* and V_w* are also carried out once in every full cycle of the PWM interval. Hence, in every full cycle PWM interval, the magnitude of the reference phase voltages V_u* V_v ^* and V_w* are compared, and Vi is assigned to the maximum value, V₂ to the middle one and V₃ to the minimum value. In this scheme, one of the phase voltages out of Vi, V or V₃ is kept fixed and the other two reference phase voltages are altered in every full cycle of the PWM if a minimum time period T_m is not available for the sensing of the dc-link voltage during the active switching states of the inverter. The logical steps followed in the doubled sided time period modification of the PWM waveform keeping either Vi, V₂ or V₃ fixed are same as the first scheme. However, instead of executing the logical steps in every PWM half cycle, they are now carried out once in every full cycle. The double sided time period modification scheme of the PWM waveform keeping either Vi , V₂ or V₃ constant when the reference phase voltage magnitudes V_u ^*, V_v* and V * are estimated in every full cycle of the PWM is shown in Fig. 16B, Fig. 16C and Fig. 16D, respectively.

(A-2. Single Sided Time Period Modification) In the single sided time period modification strategy of the PWM waveform, a minimum time period T_m is included in each active switching states during every alternate half cycle interval of the PWM carrier frequency. In the single sided time period modification of the PWM waveform, the output phase current ripple is comparatively lesser than the double sided time period modification of the PWM waveform. As shown in Figs. 17A to 17C, the current is sampled at the center of the active switching states and in every alternate PWM half cycle two phase currents can be detected. Hence, the position sensorless control of the permanent magnet synchronous motor involving the single sided time period modification of the PWM waveform includes sensing the two phase current only once in every full cycle of the PWM interval. Hence, in this case, the three phase to two phase current transformation, rotor position θ calculation and finally the estimation of the magnitude of the reference phase voltages V_u*, V_v ^* and V_w* are also carried out once in every full cycle of the PWM interval. Hence, in every full cycle PWM interval, the magnitude of the reference phase voltages V_u*, V_v ^* and V_w* are compared, and Vi is assigned to the maximum value, V₂ to the middle one and V₃ to the minimum value. In this scheme, one of the reference phase voltages out of Vi, V₂ or V₃ is kept fixed, and the other two reference phase voltages are altered in the first half cycle of the PWM interval if a minimum time period T_m is not available for the sensing of the dc-link voltage during the active switching states of the inverter. On the next half cycle of the PWM interval, the reference phase voltages remain unchanged. The logical steps followed in the single sided time period modification of the PWM waveform keeping either Vi , V₂ or V₃ fixed are same as the double sided modification explained earlier. However, instead of executing the logical steps in every PWM half cycle or in every PWM full cycle as in the double sided time period modification, they are executed in alternate PWM half cycle intervals. The single sided time period modification scheme of the PWM waveform keeping either Vi, V₂ or V₃ constant when the reference phase voltage magnitudes V_u ^*, V * and V_w ^* are estimated in every full cycle of the PWM is shown in Fig. 18B, Fig. 18C and Fig. 18D, respectively.

(B. PWM Compensation Scheme) According to the PWM compensation scheme, the base drive signal (PWM waveform) is modified so as to achieve the compensation of pulse width between two consecutive PWM intervals. In the PWM compensation scheme, the effective sinusoidal voltage reference waveforms of the three phases remain nearly constant and therefore, at low motor speed the output current distortion is minimum. The PWM compensation scheme also includes two strategies such as the double sided and the single side PWM compensation, which are described below.

(B-1. Double Sided PWM Compensation) The double sided PWM compensation scheme involves two full PWM cycles of the carrier frequency to adjust the reference PWM sinusoidal phase voltages. In this scheme, if a period of any active switching state is found to be less than the minimum time period T_m for perfect phase voltage detection, then in the first PWM interval, one of the reference phase voltages is increased and in the next PWM interval the same reference phase voltage is decreased for compensation. The position sensorless control of the permanent magnet synchronous motor involving the double-sided PWM compensation of the phase voltage waveform takes place in the following two ways. The first scheme contains sensing the two phase current in every half cycle of the PWM. The phase current from two consecutive PWM half cycles are averaged out to give the final phase current in every PWM interval as explained before. In this scheme, the three phase to two phase current transformation, rotor position θ calculation and finally the estimation of the magnitude of the reference phase voltages V_u* V_v ^* and V_w* are carried out once in every full cycle of the PWM interval. Hence, in every alternate PWM interval, the magnitude of the reference phase voltages V_u ^*, V_v ^* and V_w* are compared, and Vi is assigned to the maximum value, V₂ to the middle one and V₃ to the minimum value. In this scheme, the middle phase voltage V₂ is kept fixed, and the other two reference phase voltages Vi and V₃ are altered in two consecutive cycle of the PWM if a minimum time period T_m is not available for the sensing of the dc-link voltage during the active switching states of the inverter. The first scheme contains the following logical steps in two consecutive cycle of the PWM interval for the double sided PWM compensation strategy. i) The difference between Vι(n) and V₂(n) and the difference between V₂(n) and V₃(n) at the n-th PWM interval are calculated and defined such as, Vι(n)-V₂(n)=ΔH₁; V₂(n)-V₃(n)=ΔH₂. ii) If [ΔH-i] > ΔHmin and [ΔH₂] > ΔHmin, then there is no modification of the phase voltage waveform. Therefore the phase voltages in the n-th and the (n+1 )th interval are given as, Vm(n)=Vι(n); V_2n(n)=V₂(n); V_3n(n)=V₃(n), V,_n(n+1)=Vι(n+1); V_2n(n+1)=V₂(n+1); V_3n(n+1 )=V₃(n+1 ). iii) If both [ΔHi] < ΔHmin and [ΔH₂] < ΔHmin, the new modified phase voltages in the n-th and the (n+1)th interval are given as, Vin(n)=V₂(n)+ΔHmin; V_2n(n)=V₂(n); V_3n(n)=V₂(n)-ΔH_min, Vm(n+1 )=V₂(n+1 )-ΔH_min; V_2n(n+1 )=V₂(n+1 ); V_3n(n+1)=V₂(n+1)+ΔH_min. iv) If [ΔHi] > ΔHmin but [ΔH₂] < ΔHmin, the new modified phase voltages in the n-th and the (n+1 )th interval are given as, Vm(n)=Vι(n); V_2n(n)=V₂(n); V_3n(n)=V₂(n)-ΔH_min Vm(n+1 )=Vι(n+1 ); V_2n(n+1)=V₂(n+1); V_3n(n+1)=V₂(n+1)+ΔH_min, Now, if |V_1n(n+1 )-V_3n(n+1 )|<ΔH_min, then V_1n(n+1)=V_3n(n+1 ) +ΔH_min. v) If [ΔHi] < ΔHmm but [ΔH₂] > ΔH_min the new modified phase voltages in the n-th and the (n+1)th interval are given as, Vin(n)=V₂(n)+ΔH_min; V_2n(n)=V₂(n); V_3n(n)=V₃(n), V_1n(n+1)=V₂(n+1)-ΔHmi_n; V_2n(n+1 )=V₂(n+1 ); V_3n(n+1)=V₃(n+1), Now, if |Vin(n+1)-V_3n(n+1)|<ΔHmin, then V_3n(n+1)=V_1n(n+1 ) -ΔH_min. vi) Modified values of V_u ^*, V_v* and V_w* in two consecutive PWM intervals are retrieved from Vι_n, V₂ and V_3n. The double sided PWM compensation scheme of the phase voltage waveforms keeping V₂ constant when the reference phase voltage magnitudes V_u ^*, V_v* and V_w* are estimated in every PWM cycle are shown in Figs. 19A to 19C. It can be seen from Figs. 19A to 19C that while altering a phase voltage, the increase of phase voltage in one PWM interval T(n) is not equal to the decrease of the same phase voltage in the next PWM interval T(n+1). Therefore perfect PWM compensation is not carried out in this scheme. The second scheme for the position sensorless control of the permanent magnet synchronous motor involving the double sided PWM compensation of the phase voltage waveforms contains sensing the two phase current in every alternate interval of the PWM carrier frequency. In this scheme, the three phase to two phase current transformation, rotor position θ calculation and finally the estimation of the magnitude of the reference phase voltages V_u*,

V_v ^* and V * are carried out in every alternate PWM interval. Hence, in every alternate PWM interval, the magnitude of the reference phase voltages V_u*, V_v ^* and V_w* are compared, and Vi is assigned to the maximum value, V₂ to the middle one and V₃ to the minimum value. In this scheme, the middle phase voltage V₂ is also kept fixed and the other two reference phase voltages are altered in two consecutive cycle of the PWM. The second scheme contains the following logical steps in two s. consecutive cycle of the PWM interval for the double sided PWM compensation strategy. i) The difference between V^n) and V₂(n) and the difference between V₂(n) and V₃(n) at the n-th PWM interval are calculated and defined such as V₁(n)-V₂(n)=ΔHι; V₂(n)-V₃(n)=ΔH₂. ii) If both ΔHi > ΔH_mi_n and ΔH₂ > ΔH_min, then there is no modification of the phase voltage waveform. Therefore the phase voltages in the n-th and the (n+1)th intervals are given as Vm(n)=Vι(n); V_2n(n)=V₂(n); V_3n(n)=V₃(n) Vm(n+1 )=Vι(n+1 ); V_2n(n+1 )=V₂(n+1 ); V_3n(n+1 )=V₃(n+1 ). iii) If both ΔHι<ΔH_mj_n and ΔH₂<ΔH_min, the new modified phase voltages in the n-th and the (n+1 )th interval are given as V_1n(n)=V₁(n)+(ΔH_min-ΔHι); V_2n(n)=V₂(n); and V_3n(n)=V₃(n)-(ΔHmin-ΔH₂) V_1n(n+1)=V₁(n)-(ΔH_min-ΔHι); V_2n(n+1 )=V₂(n); and V_3n(n+1)=V₃(n)+(ΔHmin-ΔH₂). iv) If ΔHi > ΔH_m,n but ΔH₂ < ΔH_min, the new modified phase voltages in the n-th and the (n+1)th intervals are given as Vm(n)=V₁(n); V_2n(n)=V₂(n); V_3n(n)=V₃(n)-(ΔHmin~ΔH₂), Vm(n+1)=Vι(n); V_2n(n+1 )=V₂(n); V_3n(n+1)=V₃(n)+(ΔH_min-ΔH₂). v) If ΔHi < ΔHmin but ΔH₂> ΔHmin, the new modified phase voltages in the n-th and the (n+1)th interval are given as Vin(n)=V₁(n)+(ΔHmin-ΔHι); V_2n(n)=V₂(n); V_3n(n)=V₃(n), V_2n(n+1)=V₂(n); V_3n(n+1)=V₃(n). vi) Modified values of V_u ^*, V_v* and V_w* in two consecutive PWM intervals are retrieved from Vm, V₂ and V_3n. The double sided PWM compensation scheme of the phase voltage waveforms keeping V₂ constant when the reference phase voltage magnitudes V_u ^*, V_v* and V_w* are estimated in every alternate PWM cycle are shown in Figs. 20A to 20C. It can be seen from Figs. 20A to 20C, that while altering a phase voltage, the increase of phase voltage in one PWM interval T(n) is exactly equal to the decrease of the same phase voltage in the next PWM interval T(n+1). Therefore perfect PWM compensation is carried out in this scheme.

(B-2. Single Sided PWM Compensation) The single sided PWM compensation scheme involves two consecutive PWM half cycles of the carrier frequency to adjust the reference PWM sinusoidal phase voltages. In this scheme, in a PWM interval if a period of any active switching state of the inverter is found to be less than the minimum time period T_m for perfect phase voltage detection, then in the first half cycle PWM interval, one of the reference phase voltages is increased, and in the next half cycle PWM interval, the same reference phase voltage is decreased for compensation. Hence, in the single sided PWM compensation strategy of the phase voltage waveforms, a minimum time period T_m is included in every active switching state during every alternate half cycle interval of the PWM carrier frequency. Hence, in every alternate PWM half cycle, two phase currents can be detected. Hence, the position sensorless control of the permanent magnet synchronous motor involving the single sided PWM compensation scheme contains sensing the two phase current only once in every full cycle of the PWM. Therefore, in this case, the three phase to two phase current transformation, rotor position θ calculation and finally the estimation of the magnitude of the reference phase voltages V_u*, V_v ^* and V_w* are also carried out once in every full cycle of the PWM interval. Hence, in every full cycle PWM interval, the magnitude of the reference phase voltages V_u* V_v ^* and V_w* are compared, and Vi is assigned to the maximum value, V₂ to the middle one and V₃ to the minimum value. In this scheme, one of the reference phase voltages out of Vi , V₂ or V₃ is kept fixed and the other two reference phase voltages are altered in every half cycle of the PWM interval if a minimum time period T_m is not available for the sensing of the dc-link voltage during the active switching states of the inverter. Therefore, in this method the logical steps followed for the phase voltage modification in two consecutive PWM half cycle intervals should be identical to the second scheme of the double sided PWM compensation strategy. The single sided PWM compensation scheme of the phase voltage waveforms keeping V₂ constant when the reference phase voltage magnitudes V_u\ V_v* and V_w ^* are estimated in every PWM cycle are shown in Figs. 21 A and 21 B. It can be seen from Figs. 21 A and 21 B, that while altering a phase voltage, the increase of phase voltage in one half cycle PWM interval is exactly equal to the decrease of the same phase voltage in the next half cycle PWM interval. Therefore perfect PWM compensation is carried out in this scheme. In summary, for the current sensing strategy with the dc-link shunt R_dc, the voltage across the shunt Rdc is sensed by an A/D converter during the two active inverter switching states of a PWM interval. With this scheme, a double sided PWM modulation strategy always provides information about two phase currents twice during every PWM interval. The ideal instant to sense the dc-link voltage is at the middle of the active inverter switching states. However, the proposed current sensing strategy by a dc-link shunt has severe limitations when the duty cycles of the two phases are almost equal. Hence, to measure the two phase currents at every PWM interval, the sinusoidal PWM phase voltage waveforms are modified at particular instants so that a minimum time period T_m is always available for the sensing of the dc-link voltage during the active inverter switching states.

Industrial Applicability The proposed closed loop position sensorless of a permanent magnet synchronous drive with a sinusoidal pulse width modulated waveform carried out by detecting the phase currents with the aid of inexpensive shunts placed either in the emitter of each lower leg transistors or the dc-link of the inverter module is ideal for the compressor drive of refrigerators, domestic air-conditioners and electric driven car air-conditioners. Fig. 22 shows an exemplary configuration of a compressor drive for driving a permanent magnet synchronous motor coupled to a compressor with a sinusoidal pulse width modulated drive. The drive 100 includes the motor driving apparatus as described in the first and second embodiments. The drive 100 drives the permanent magnet synchronous motor to drive the compressor 70 coupled to a refrigeration cycle 71.

Although the present invention has been described in connection with specified embodiments thereof, many other modifications, corrections and applications are apparent to those skilled in the art. Therefore, the present invention is not limited by the disclosure provided herein but limited only to the scope of the appended claims.

Claims

1 A method of a closed loop position sensorless control of a three phase permanent magnet synchronous motor driven by an inverter module with sinusoidal pulse width modulated drive, the inverter module comprising, in each phase, transistors in lower and upper legs and a shunt placed in the emitter of the transistor in the lower leg, the inverter module being controlled by a micro-controller having an A/D converter connected with an input port, the method comprising: detecting phase currents with the shunts placed in the emitter of the transistors in the lower legs; level shifting the voltage drop across the three shunts; amplifying the shifted voltage; and subsequently feeding the amplified voltage into the input port of the A/D converter of a micro-controller, wherein the sensing of the shunt voltages is started at the peak of the PWM carrier frequency when all the transistors in the lower leg are turned ON, and the values of the phase currents are retrieved from the sensed shunt voltages.

2. The method according to claim 1 , wherein the simultaneous detection of the three phase currents, the three phase to two phase current transformation, the estimation of the reference voltages V_u ^*, V_v ^* and V_w ^* and the calculation of the rotor position θ are carried out once in every PWM interval for the position sensorless control of the permanent magnet synchronous motor.

3. The method according to claim 1 , wherein, below the 95% modulation of the sinusoidal PWM wave, any two out of the three shunt voltages sensed is used to retrieve the two phase currents and execute the three phase to two phase current transformation, and when the PWM carrier frequency is between 2.75 and 10 kHz and the modulation of the sinusoidal PWM wave is above 95%, for retrieving the two phase currents the shunt voltage is detected from the two phases whose instantaneous phase voltages is not maximum at that instant, and subsequently the three phase to two phase current transformation is executed.

4. A method of a closed loop position sensorless control of a three phase permanent magnet synchronous motor driven by an inverter module with sinusoidal pulse width modulated drive, the inverter module comprising, in each phase, transistors in lower and upper legs and a shunt placed in a dc-link of the inverter module, the inverter module being controlled by a micro-controller having an A D converter connected with an input port, the method comprising: detecting the phase currents with the shunts placed in the dc-link of the inverter module; amplifying the voltage drop across the dc-link shunt; and feeding the amplified voltage into the input port of the A/D converter of a micro-controller; wherein, in any PWM interval, the sensing of the dc-link voltage is started at the middle of the active inverter switching states, and the values of the phase currents is retrieved from the dc-link voltages sensed during the active inverter switching states.

5. The method according to claim 4, wherein every PWM interval requires a minimum time period T_m during the active switching state of the inverter module so that the dc-link shunt voltage is accurately sensed, and the period T_m is given by sum of the sampling time (t_s), the dead time between the upper and lower leg transistors (td) and the shunt voltage rise time (t_r).

6. The method according to claim 5, wherein when the period for the active switching states of the inverter in a PWM interval is less than the minimum period T_m, the PWM sinusoidal phase voltage waveform is modified so that a minimum time period is always available for the sensing of the dc-link voltage accurately during the active inverter switching states.

7. The method according to claim 6, wherein the modification of the sinusoidal PWM phase voltage waveforms is carried out by the "Time period modification scheme" where the effective sinusoidal phase voltages are changed.

8. The method according to claim 6, wherein the modification of the sinusoidal PWM phase voltage waveforms is carried out by the "PWM compensation scheme" where the effective sinusoidal phase voltages are not altered.

9. The method according to claim 7, wherein a double sided time period modification strategy of the PWM waveform is performed such that a minimum time period T_m is always included in each active switching states during every half cycle interval of the PWM carrier frequency.

10. The method according to claim 7, wherein a single sided time period modification strategy of the PWM waveform is performed such that a minimum time period T_m is included in each active switching states during every alternate half cycle interval of the PWM carrier frequency.

11. The method according to claim 8, wherein a double sided PWM compensation scheme is conducted such that in two consecutive full PWM cycles of the carrier frequency the reference PWM sinusoidal phase voltages are adjusted, and in the compensation scheme, in a PWM interval when an active switching state of the inverter is found to be less than that of the minimum time period T_m for perfect phase voltage detection, in the first PWM interval one of the reference phase voltage is increased and in the next PWM interval the same reference phase voltage is decreased.

12. The method according to claim 8, wherein a single sided PWM compensation scheme is conducted such that in two consecutive PWM half cycles of the carrier frequency the reference PWM sinusoidal phase voltages are adjusted, and in the compensation scheme, in a PWM interval when an active switching state of the inverter is found to be less than that of the minimum time period T_m for perfect phase voltage detection, in the first half cycle PWM interval one of the reference phase voltage is increased and in the next half cycle PWM interval the same reference phase voltage is decreased.

13 The method according to claim 9, further comprising sensing the two phase currents in every half cycle of the PWM, carrying out a three phase to two phase current transformation, rotor position calculation and finally the estimation of the magnitude of the reference phase voltages V_u*, V_v ^* and V_w* in every half cycle of the PWM interval, comparing, in every half cycle PWM interval, the magnitude of the reference phase voltages V_u* V_v ^* and V_w*, and assigning Vi to the maximum value, V₂ to the middle value and V₃ to the minimum value. wherein one of the phase voltages out of Vi, V₂ or V₃ is kept fixed, and the other two reference phase voltages are altered in every half cycle of the PWM if a minimum time period T_m is not available for the sensing of the dc-link voltage during the active switching states of the inverter.

14. The method according to claim 9, further comprising sensing the two phase currents only once in every full cycle of the PWM interval carrying out the three phase to two phase current transformation, rotor position calculation and finally the estimation of the magnitude of the reference phase voltages V_u* V_v ^* and V_w* once in every full cycle of the PWM interval. comparing, in every full cycle PWM interval, the magnitude of the reference phase voltages V_u*, V_v ^* and V_w* and assigning Vi to the maximum value, V₂ to the middle value and V₃ to the minimum value. wherein one of the phase voltages out of Vi, V₂ and V₃ is kept fixed, and the other two reference phase voltages are altered in every full cycle of the PWM if a minimum time period T_m is not available for the sensing of the dc-link voltage during the active switching states of the inverter.

15. The method according to claim 10, further comprisng sensing the two phase currents only once in every full cycle of the PWM, carrying out the three phase to two phase current transformation, rotor position calculation and finally the estimation of the magnitude of the reference phase voltages V_u* V_v ^* and V_w* once in every full cycle of the PWM interval, comparing, in every full cycle PWM interval, the magnitude of the reference phase voltages V_u* V_v ^* and V *, and assigning Vi to the maximum value, V₂ to the middle value and V₃ to the minimum value. In this scheme, wherein one of the reference phase voltages out of Vi, V₂ or V₃ is kept fixed, and the other two reference phase voltages are altered in the first half cycle of the PWM interval if a minimum time period T_m is not available for the sensing of the dc-link voltage during the active switching states of the inverter while on the next half cycle of the PWM interval the reference phase voltages remain unchanged.

16. The method according to claim 11 , further comprising sensing the two phase currents in every half cycle of the PWM, averaging the phase current from two consecutive PWM half cycles to give the final phase current in every PWM interval, carrying out the three phase to two phase current transformation, rotor position calculation and finally the estimation of the magnitude of the reference phase voltages V_u* V_v ^* and V_w* once in every full cycle of the PWM interval, comparing, in every alternate PWM interval, the magnitude of the reference phase voltages V_u*, V_v ^* and V_w* assigning Vi to the maximum value, V₂ to the middle value and V₃ to the minimum value wherein the middle phase voltage V₂ is kept fixed, the other two reference phase voltages are altered in two consecutive cycles of the PWM if a minimum time period T_m is not available for the sensing of the dc-link voltage during the active switching states of the inverter, and during changing of the phase voltage the increase of one phase voltage in the first PWM interval is not equal to the decrease of the same phase voltage in the next PWM interval.

17. The method according to claim 11 , further comprising sensing the two phase currents in every alternate interval of the PWM carrier frequency, carrying out the three phase to two phase current transformation, rotor position calculation and finally the estimation of the magnitude of the reference phase voltages V_u*, V_v ^* and V_w* in every alternate PWM interval, comparing, in every alternate PWM interval, the magnitude of the reference phase voltages V_u ^*, V_v ^* and V_w ^* assigning V| to the maximum value, V₂ to the middle value and V₃ to the minimum value, wherein the middle phase voltage V₂ is kept fixed and the other two reference phase voltages are altered in two consecutive cycles of the PWM if a minimum time period T_m is not available for the sensing of the dc-link voltage during the active switching states of the inverter, during changing of the phase voltage, the increase of one phase voltage in the first PWM interval is exactly equal to the decrease of the same phase voltage in the next PWM interval.

18. The method according to claim 12, further comprising sensing the two phase currents only once in every full cycle of the PWM, carrying out the three phase to two phase current transformation, rotor position calculation and finally the estimation of the magnitude of the reference phase voltages V_u*, V_v ^* and V_w* once in every full cycle of the PWM interval, comparing, in every full cycle PWM interval, the magnitude of the reference phase voltages V_u*, V_v ^* and V_w* assigning Vi to the maximum value, V₂ to the middle value and V₃ to the minimum value. wherein one of the reference phase voltages out of Vi, V₂ or V₃ is kept fixed and the other two reference phase voltages are altered in every half cycle of the PWM interval if a minimum time period T_m is not available for the sensing of the dc-link voltage during the active switching states of the inverter, during changing of the phase voltage, the increase of one phase voltage in the first half cycle PWM interval is exactly equal to the decrease of phase voltage in the next half cycle PWM interval.

19. A compressor drive for driving a motor with the method according to claim 1 or 4.