WO2005071850A3 - A dynamically reconfigurable signal processing apparatus and method for use in a high speed digital communication system - Google Patents

A dynamically reconfigurable signal processing apparatus and method for use in a high speed digital communication system Download PDF

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Publication number
WO2005071850A3
WO2005071850A3 PCT/IB2005/050258 IB2005050258W WO2005071850A3 WO 2005071850 A3 WO2005071850 A3 WO 2005071850A3 IB 2005050258 W IB2005050258 W IB 2005050258W WO 2005071850 A3 WO2005071850 A3 WO 2005071850A3
Authority
WO
WIPO (PCT)
Prior art keywords
signal processing
processing apparatus
high speed
communication system
digital communication
Prior art date
Application number
PCT/IB2005/050258
Other languages
French (fr)
Other versions
WO2005071850A2 (en
Inventor
Krishnamurthy Vaidyanathan
Karl R Wittig
Geoffrey F Burns
Original Assignee
Koninkl Philips Electronics Nv
Philips Corp
Krishnamurthy Vaidyanathan
Karl R Wittig
Geoffrey F Burns
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv, Philips Corp, Krishnamurthy Vaidyanathan, Karl R Wittig, Geoffrey F Burns filed Critical Koninkl Philips Electronics Nv
Priority to EP05702752A priority Critical patent/EP1709549A2/en
Priority to JP2006550435A priority patent/JP2007520952A/en
Publication of WO2005071850A2 publication Critical patent/WO2005071850A2/en
Publication of WO2005071850A3 publication Critical patent/WO2005071850A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W88/00—Devices specially adapted for wireless communication networks, e.g. terminals, base stations or access point devices
    • H04W88/08—Access point devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Transceivers (AREA)
  • Stored Programmes (AREA)
  • Logic Circuits (AREA)

Abstract

A dynamically reconfigurable signal processing apparatus (158c) is disclosed. The signal processing apparatus (158c) includes at least one system controller (170) for detecting a change of state in a high speed digital communication system (10). Responsive to the change of state, in one embodiment, signal processing function code is downloaded, in real-time or in near real-time, from an external memory (130) to be processed in an array-type processor (120). In another embodiment, signal processing function code for a plurality of signal processing functions are pre-stored in the array­type processor (120) and are switch selectable in response to a change of system state thereby obviating the need to download signal processing function code.
PCT/IB2005/050258 2004-01-22 2005-01-21 A dynamically reconfigurable signal processing apparatus and method for use in a high speed digital communication system WO2005071850A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP05702752A EP1709549A2 (en) 2004-01-22 2005-01-21 A dynamically reconfigurable signal processing apparatus and method for use in a high speed digital communication system
JP2006550435A JP2007520952A (en) 2004-01-22 2005-01-21 Dynamically reconfigurable signal processing apparatus and method for use in high-speed digital communication systems

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US53827504P 2004-01-22 2004-01-22
US60/538,275 2004-01-22

Publications (2)

Publication Number Publication Date
WO2005071850A2 WO2005071850A2 (en) 2005-08-04
WO2005071850A3 true WO2005071850A3 (en) 2005-10-13

Family

ID=34807171

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2005/050258 WO2005071850A2 (en) 2004-01-22 2005-01-21 A dynamically reconfigurable signal processing apparatus and method for use in a high speed digital communication system

Country Status (4)

Country Link
EP (1) EP1709549A2 (en)
JP (1) JP2007520952A (en)
CN (1) CN1910570A (en)
WO (1) WO2005071850A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7856246B2 (en) * 2007-03-21 2010-12-21 Nokia Corporation Multi-cell data processor
JP5572527B2 (en) 2010-11-09 2014-08-13 パナソニック株式会社 Communication processing apparatus and communication processing method
CN114661656B (en) * 2022-05-25 2022-08-30 广州万协通信息技术有限公司 Reconfigurable array configuration method, device, equipment and storage medium

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6047115A (en) * 1997-05-29 2000-04-04 Xilinx, Inc. Method for configuring FPGA memory planes for virtual hardware computation
US6282627B1 (en) * 1998-06-29 2001-08-28 Chameleon Systems, Inc. Integrated processor and programmable data path chip for reconfigurable computing
WO2002050700A2 (en) * 2000-12-19 2002-06-27 Picochip Designs Limited Processor architecture
US20030105949A1 (en) * 2001-11-30 2003-06-05 Quicksilver Technology, Inc. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6047115A (en) * 1997-05-29 2000-04-04 Xilinx, Inc. Method for configuring FPGA memory planes for virtual hardware computation
US6282627B1 (en) * 1998-06-29 2001-08-28 Chameleon Systems, Inc. Integrated processor and programmable data path chip for reconfigurable computing
WO2002050700A2 (en) * 2000-12-19 2002-06-27 Picochip Designs Limited Processor architecture
US20030105949A1 (en) * 2001-11-30 2003-06-05 Quicksilver Technology, Inc. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
ARNDT M ET AL: "SOFTWARE RADIO: THE CHALLENGES FOR RECONFIGURABLE TERMINALS LA RADIO LOGICIELLE: LES ENJEUX POUR DES TERMINAUX RECONFIGURABLES", ANNALES DES TELECOMMUNICATIONS - ANNALS OF TELECOMMUNICATIONS, PRESSES POLYTECHNIQUES ET UNIVERSITAIRES ROMANDES, LAUSANNE, CH, vol. 57, no. 7/8, July 2002 (2002-07-01), pages 570 - 612, XP001124779, ISSN: 0003-4347 *
GAY-BELLILE, O. MARCHAL, X. BURNS, G. VAIDYANATHAN, K: "A reconfigureable superimposed 2D-mesh array for channel equalization", IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, 2002. ISCAS 2002, August 2002 (2002-08-01), pages 893 - 896, XP002335646, ISBN: 0-7803-7448-7 *
KOREN I ET AL: "A DATA-DRIVEN VLSI ARRAY FOR ARBITRARY ALGORITHMS", COMPUTER, IEEE COMPUTER SOCIETY, LONG BEACH., CA, US, US, vol. 21, no. 10, 1 October 1988 (1988-10-01), pages 30 - 43, XP000118929, ISSN: 0018-9162 *
SOFTWARE DEFINED RADIO FORUM: "Requirements for Radio Software Download for RF Reconfiguration", NN, 13 November 2002 (2002-11-13), XP002335657, Retrieved from the Internet <URL:http://www.sdrforum.org/public/approved/02_a_0007_v0_00_dl_req_01_22_03.pdf> [retrieved on 20050712] *
YEUNG A K W ET AL: "A reconfigurable data-driven multiprocessor architecture for rapid prototyping of high throughput DSP algorithms", SYSTEM SCIENCES, 1993, PROCEEDING OF THE TWENTY-SIXTH HAWAII INTERNATIONAL CONFERENCE ON WAILEA, HI, USA 5-8 JAN. 1993, LOS ALAMITOS, CA, USA,IEEE, US, vol. i, 5 January 1993 (1993-01-05), pages 169 - 178, XP010640447, ISBN: 0-8186-3230-5 *

Also Published As

Publication number Publication date
CN1910570A (en) 2007-02-07
WO2005071850A2 (en) 2005-08-04
EP1709549A2 (en) 2006-10-11
JP2007520952A (en) 2007-07-26

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