CN1910570A - A dynamically reconfigurable signal processing apparatus and method for use in a high speed digital communication system - Google Patents
A dynamically reconfigurable signal processing apparatus and method for use in a high speed digital communication system Download PDFInfo
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- CN1910570A CN1910570A CNA2005800029297A CN200580002929A CN1910570A CN 1910570 A CN1910570 A CN 1910570A CN A2005800029297 A CNA2005800029297 A CN A2005800029297A CN 200580002929 A CN200580002929 A CN 200580002929A CN 1910570 A CN1910570 A CN 1910570A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W88/00—Devices specially adapted for wireless communication networks, e.g. terminals, base stations or access point devices
- H04W88/08—Access point devices
Abstract
A dynamically reconfigurable signal processing apparatus (158c) is disclosed. The signal processing apparatus (158c) includes at least one system controller (170) for detecting a change of state in a high speed digital communication system (10). Responsive to the change of state, in one embodiment, signal processing function code is downloaded, in real-time or in near real-time, from an external memory (130) to be processed in an array-type processor (120). In another embodiment, signal processing function code for a plurality of signal processing functions are pre-stored in the arraytype processor (120) and are switch selectable in response to a change of system state thereby obviating the need to download signal processing function code.
Description
Present invention relates in general to signal Processing, be specifically related to a kind of being used in real time or the approaching signal processor that dynamically reconfigures of carrying out the unlike signal processing capacity in real time.
The communicating wireless signals system requirements is carried out a large amount of Channel Modulation and is conciliate modulation function, to transmit and receive numerical data via this network.Typically, modulation and demodulation function is included in the signal processing function that utilizes known digital signal processing (DSP) method and technology to carry out in the digital field.In high-bandwidth radio-frequency systems, the desired sampling rate sampling rate of DSP is very high, to such an extent as to all be to utilize digital logic hardware customization, special use to carry out these functions (promptly Chang Gui DSP computer processor can not move to support the desired high data rate of this kind high-speed sampling rate sampling rate) traditionally.
Recently, developed and to have carried out some Computer Architecture of DSP function with desired sampling rate sampling rate, and be known in the industry as " software radio ".These so-called software radios typically are made up of parallel processing array, described parallel processing array has in fact very little in a large number but the consistent very fast computer processor of operation, so that each processor is carried out a part of desired signal Processing, thereby allow this array to carry out necessary DSP function with desired sampling rate.Described these architectures can be readily configured to operate in any in the multiple communication strategy, described communication strategy can utilize various modulation and demodulation methods simply, by utilizing essential software that processor is programmed, carry out appropriate functional.
The term software radio is used for describing to the waveform requirement of multiple modulation technique, broadband or arrowband operation, communication security function (for example jump) and electric current and the wireless communication that the evolution standard in wide frequency range provides software control.
The United States Patent (USP) 6,181,734 that Palermo proposes discloses according to the software radio that operates in the software program operation on the common radio platform.Interoperable waveform pattern adds application program to the mode of personal computer and is used as software application and adds to be similar to.
Another example of such equipment is described as the hybrid radio transceiver in the United States Patent (USP) 6,091,715 that Vucetic proposes.Vucetic has hinted that such radio transceiver provides the parameter of software definition to obtain dirigibility aspect modulation and the protocol type.
Above-mentioned patent or prior art all do not have to propose the needs to following software radio, and promptly this kind software wireless electric energy responds the variation of detected system state, in real time or near in real time by reprogramming dynamically to carry out different signal processing functions.
The invention provides a kind of digital signal equipment that dynamically reconfigures, be used for the variation of responding system state, in real time or near carrying out different digital signal processing functions in real time.The present invention also indicates on the silicon surface area that reduces and implements digital signal processing appts.
According to an aspect of the present invention, system of the present invention comprises the processor of system controller, array control unit and array type at least.The processor of array type comprises a plurality of data handling components, each data handling component further comprises the specific program storer that is used to store a part of signal processing function code, and described signal processing function code is used for the variation combine digital signal processing function of responding system state.Different signal processing functions can comprise, for example, and FFT processing, correction, digital filtering or the like.
According to one embodiment of present invention, by downloading signal processing function code the specific program storer separately will be stored in data handling component from external memory storage carrying out therein, can be in real time or the approaching signal handling equipment that dynamically reconfigures in real time.
According to another embodiment of the invention, the private memory of each data handling component can be configured to a plurality of memory blocks.A plurality of memory blocks can be by the pre-loaded signal processing function code that is associated in desired with different digital signal processing function of each stage of high-speed digital communication system.The variation of responding system state, the processor of array type are configured in real time or approaching memory block of selecting to store desired signal processing function in real time convertiblely.In this kind mode, can obtain the signal processing function code data of carrying out by the processor of array type immediately.
According to another aspect of the present invention, in digital signal processing appts, a kind ofly be used in real time or, comprise behavior: (i) receive input digit information at described network node near reconfiguring this equipment to carry out the method for different signal processing functions when needed in real time; (ii) in the variation of described network node detected state; (iii) respond the variation of detected state described in the described network node, discern at least one the signal processing function that is performed; And the variation that (iv) responds described detected state, in real time or near dynamically reconfiguring signal handling equipment to carry out described at least one signal processing function in real time.
Valuably, signal handling equipment of the present invention uses less resources and the function of comparing equivalence with a plurality of specialized hardwares of the prior art and/or software signal treatment facility is provided.And, should be appreciated that with respect to prior art circuits, to signal handling equipment of the present invention dynamically reprogramming cause the silicon surface area that reduces to carry out the ability of different signal processing functions.The result has improved design productivity.
In conjunction with the accompanying drawings, by the exemplary embodiment of the present invention that reference is described in detail below, above-mentioned feature of the present invention is with apparent more and easy to understand, wherein
The prior art systems illustrated example of Fig. 1 a kind of cellular system, can implement the present invention therein;
The block scheme of Fig. 2 generally example the structure of the wireless network node of constructing according to prior art;
Fig. 3 is the more detailed exemplary plot of the signal processing unit 158c among the Fig. 2 that constructs according to prior art;
Fig. 4 is the more detailed exemplary plot of the signal processing unit 158c among the Fig. 2 that constructs according to embodiments of the invention;
The more detailed exemplary plot of signal processing unit 158c among Fig. 2 that Fig. 5 is according to another embodiment of the invention to be constructed.
The present invention provides generally and has been used for dynamically reconfiguring signal processing apparatus to carry out the technology of different signal processing functions in the different standard (including but not limited to the system data of the network node of detected variation and/or combined signal treating apparatus in the channel) of high-speed digital communication system response.
In conjunction with being used for the typical architecture of deal with data to transmit by network, the present invention will be described.Canonical system comprises and is configured to two-dimensional array as (MxN, network processing unit array NxN).But, should be appreciated that the present invention is applicable to more that generally the performance of wherein expecting dynamically to reconfigure by use is to provide any processor structure of signal processing function.
According to embodiments of the invention, signal processing apparatus of the present invention can be in real time or near in real time by reprogramming dynamically, to respond the variation of detected system state, carry out needed signal processing function.This and prior art differ widely, and wherein construct the resource that is in specialized hardware or software signal processor form in such a way, to resemble special-purpose (being hardwired) for each digital signal processing function that will be performed.
The present invention has specific but not exclusive application in the various aspects of radio data network.But, should be appreciated that to the invention is not restricted to this or any specific data network application.
In the radio data network field, network node must be carried out multiple different digital communication functions according to the particular network standard.In many cases, having only a kind of digital communication functions in the moment of any specific is that the function of current active is in use.Correspondingly, signal processing apparatus of the present invention only needs to be configured to the combine digital processing capacity at the moment.For example, well-known, IEEE 802.11a network standard is supported four kinds of different modulator approaches, i.e. BPSK, QPSK, 16 and 64 grades of QAM.Utilize signal handling equipment of the present invention to avoid providing the method for dedicated hardware/software according to various standards in the prior art with deal with data.Especially, reconfigurable signal handling equipment of the present invention can be in real time or near dynamically being disposed and reconfigure when the operation in real time, with according to above-mentioned various modulator approaches operations.Can utilize the detected needed modulator approach of the rate information that transmits in packet header, header packet information typically transmits after preamble.In this kind mode, reconfigurable device of the present invention has avoided in four kinds of modulator approaches each all to need dedicated hardware/software.
The system diagram example of Fig. 1 typical cellular system 10, can implement the present invention therein.Cellular system comprises a plurality of base stations 102,104,106,108,110 and 112, and they provide service for radio communication in separately launch site or zone.Cellular system provides radio communication service for a plurality of wireless subscriber units.These wireless subscriber units comprise wireless phone 114,118,120 and 126, mobile computer 124 and 128, and desktop computer 116 and 122.At normal operation period, each in these subscriber units all communicates with one or more base stations of base station 102 to 112 between transfer period.As below will being described, the signal processing apparatus that each subscriber unit 114 to 128 and base station 102 to 112 all comprise according to the present invention being constructed.
The block diagram of Fig. 2 generally example according to the structure of the wireless network node 100 of prior art structure.The general structure of wireless device 100 will appear in any one subscriber unit 114 to 128 and base station 102 to 112 of example among Fig. 1.Wireless device 100 comprises antenna 160, RF front end 152, comprises the signal Processing front end 154 of normal signal processing element 158A, 158B, 158C.Wireless device 100 also comprises a plurality of host device components 160, the demand of all wireless devices 100 of its service except that RF demand 152 and front end 154 signal Processing demands.
Fig. 3 is the more detailed description to the signal processing unit 158C of the Fig. 2 that constructs according to prior art.Signal processing apparatus 158C comprises input data-interface 110, is used to receive digital input data 9.Input data-interface 110 buffer memory digital input data 9 in data buffer 23, and the numerical data to be supplied 11 of output buffers is to processor array 120.Processor array 120 is embodied as the set of the treatment element 122 of matrix structure.Treatment element 122 preferably is configured to original configurable processor array, and this kind processor is designed to high-throughput, reconfigurable signal Processing.Each processor keeps presumptive instruction collection, minimum local storage (program storage 124), and utilizes nearest neighbor communication and adjacent processor swap data.Be described about other details of ARRAY PROCESSING " ARRAY PROCESSING (Array Processing For ChannelEqualization) that is used for channel equalization " of G.Burns and K.Vaidyanathan in U.S. Philip research (Philips Research USA) for example, this article is herein incorporated with for referencial use.The array of treatment element 122 is configured to, and by loading suitable digital processing functional software to each memory component 124 separately at reasonable time, carries out different signal processing functions.Under the control of array control unit 140, can be from memory cell 130 being used for the software loading of signal specific processing capacity to processor array 120.
With reference now to Fig. 4 and Fig. 5,, example and described the preferred embodiments of the present invention wherein.
Fig. 4 is the detailed view of the signal processing unit 158C of Fig. 3 according to an embodiment of the invention.As shown in Figure 4, signal processing unit 158C comprises the element of describing among top Fig. 3, and comprises system controller 170.
The system controller 170 that shows comprises first input 173 that is denoted as " input data ", is coupled to the output of input data-interface 110, be denoted as " channel/system " data, be coupled to the channel/system data the source second the input 171, be denoted as " output data ", be coupled to the 3rd input 175 of the output of output data interface 160, and be denoted as " reconfiguring request ", be coupled to the independent output 177 of the input of array control unit 140.Should be appreciated that different embodiment of the present invention can utilize the different combination of above-described input and output.
The array control unit 140 that shows is coupled to external memory storage 130 via data line 180, with response " reconfiguring request " order 177 from system controller 170 outputs, obtains the signal processing function code again from storer 130.The output of the array control unit 140 that shows is coupled to the input of processor array 120 via data line 181, so that the signal processing function code from external memory storage 130 is exported to processor array 120.
During operation, when system controller 170 detected the variation of the system state in the network node 100 according to one or more in above-named four aforementioned condition, it sent " reconfiguring request " order 177 to array control unit 140.Array control unit is by downloading the appropriate signals processing capacity software that is stored in advance in the external memory storage 130, response " reconfiguring request " order 177.External memory storage 130 is preferably each will be by the digital signal processing function storage signal processing capacity software of network node 100 execution.For example, the signal processing function of being stored can comprise, handles the function that is associated, relevant, digital filtering or the like with FFT.Should be noted that external memory storage 130 preferably nonvolatile memory or other suitable storer.
Response " reconfiguring request " orders 177, from external memory storage 130 download signal processing capacity softwares to processor array 120, to carry out desired signal processing function of this moment.In some cases, can require to carry out an above signal processing function at any time.The simultaneity that should be appreciated that a plurality of signal processing functions requires partial memory array 120 to be exclusively used in the specific signal processing capacity.But also should be appreciated that in other cases the signal processing function that is performed can be required to be lower than the capacity of the overall process capacity of processor array 120, and in this case, it is idle that some treatment element 122 in the array 120 can keep.
In the present embodiment, load different treatment elements 122, can be embodied as the independent multiplexed data bus of employing in the program storage 124 of treatment element 122 via special line 180,181.Knowing those skilled in the art is to be understood that, must carry out with enough high speeds via independent multiplex bus 180,181 load softwares to the processing of program storage 124, to meet network node 100 in its sequential requirement of the main network standard of operation down.Because in some cases, the time of defined may be very short, so software loading mechanism must be very fast.In order to ensure proper synchronously, in certain embodiments, for example among the embodiment shown in Fig. 3-5, demonstration will be in Input Data Buffer 23 and output data buffer 25 buffer memory input and output data.
In case the signal processing function of current requirement intrinsic software be loaded in separately the program storage 124, processor 120 is just carried out signal processing function, and produces the treated output data 15 that will be provided to output data interface 160.
According to another embodiment of the invention, can be by each treatment element 122 in related a plurality of (being two or more) program storage 125a-125n (referring to Fig. 5) and the memory array 120, come to be a plurality of signal processing functions storage signal processing capacity code data in advance, reconfigure the required time of processor array 120 with improvement.So, just avoided from the needs of external memory storage (for example external memory storage 130) download signal processing capacity code data.
Fig. 5 is the more detailed view to the signal processing unit 158C of Fig. 3 according to current embodiment.As shown in Figure 5, signal processing unit 158C comprises those elements of describing among top Fig. 4.In addition, Fig. 5 also comprises the program storage element 125a-125n that is associated with each treatment element 122.But array control unit 140 subregion option program memory component 125a-125n.That is, at any time, in this district, array control unit 140 can be transformed into another program storage element from a program storage element.
Preferably, shift to an earlier date the pre-loaded a plurality of memory block 125a-125n that are associated with each treatment element 122, wherein each storage area stores is used for the signal processing function code of signal specific processing capacity.For example, the first program storage area 125a can be by the pre-loaded signal processing function code data that is associated with the correction signal processing capacity, and the second program storage area 125b can be by the pre-loaded signal processing function code data that is associated with the FFT signal processing function.
The key feature of embodiment is, for immediate access in fact when needed, the signal processing function code of definition corresponding signal processing capacity is stored among separately the program storage 125a-n in advance, and need not from external memory storage 130 to obtain the signal processing function code again, like this, aspect execution time and speed, provide important performance advantage.
When operation, in case detect the variation of state, system controller 170 just indicates array control unit 140 to select a pre-loaded memory block of program convertiblely, memory block 125j for example, stored the signal processing function code that is associated with the signal processing function that will carry out therein, to respond the variation of detected state.
The ability of conversion selection memory block 125a-n provides the immediate access to desired signal processing function code in fact.Avoided and the time delay that is associated from external memory storage 130 download function codes.Therefore, can in time enough, reconfigure processor elements 122 separately, to satisfy the requirement of all known network standards.
Should be appreciated that having known in advance and distribute under sufficiently long those situations of the time that reconfigures processor array 120, can utilize first embodiment.That is to say, known at those to have sufficient time to dynamically to download under the situation of required function code that the method for first embodiment is just enough from external memory storage 130.
Should be appreciated that in each embodiment described herein, processor array 120 can be individually, with the processor group or as a whole array be addressed.In other words, if in processor array 120, carry out two processing capacities simultaneously, first signal processing function (for example function A) can be in first subclass of treatment element 122, carried out so, and second function (for example function B) can be in second subclass of treatment element 122, carried out simultaneously.
The typical case uses
On behalf of an important typical case of the present invention, IEEE 802.11 WLAN standard use.But, should be noted that the present invention is not limited only to this standard, but can in multiple different communication standard, implement.
According to 802.11 standards, before " useful load (payload) " (real data) is transmitted, transmission " preamble (preamble) " earlier.The synchronously desired signal processing requirement to " preamble " part of receiver is different fully with the desired payload portions of digital received.These the two kinds moment (that is, at any given time, or receive preamble, or receive useful load, the two can not be received simultaneously) that operate in mutual exclusion take place.And at given time, node or reception data are perhaps launched data, but will never be received and launch data simultaneously.Signal handling equipment of the present invention can be configured to be carried out preamble at reasonable time and handles, and thereafter,, is handled to carry out useful load (data transmission) at reasonable time in real time or near reconfiguring in real time by dynamically.For example, when needs were handled the preamble part, signal processing apparatus initially can be configured to correlator, and when needs processing payload data, can be reprogrammed subsequently to be FFT.Should be appreciated that owing to,, optimized available radio resource to carry out desired signal specific processing capacity of any time dynamically in real time or near reconfiguring signal processing apparatus of the present invention in real time.
It should be apparent to those skilled in the art that disclosed apparatus and method have various application in the radio data network field.
Although the present invention is described with reference to specific embodiment,, should be appreciated that and can take multiple variation and do not break away from the illustrated spirit and scope of the appended claim of the present invention.Therefore, instructions and accompanying drawing are taken as the mode of example rather than the scope of intention restriction claims.
In order to explain appended claim, be to be understood that:
Word " comprises (comprising) " and is not precluded within listed other element or the behavior that occurs outside those in the claim of being given;
Word before an element " one (a) " or " one (an) " do not get rid of and a plurality of this kind elements occur;
Any reference marker in the claim is not made restriction to their scope;
Structure or function that on behalf of identical project or hardware or software, several " devices (means) " can realize; And
Disclosed various element can comprise hardware components (for example, Li San electronic circuit), software section (for example, computer programming) or combination in any wherein.
Claims (12)
1, be used for the signal processing apparatus (158c) of high-speed digital communication system (10), described signal processing apparatus (158c) is carried out predetermined signal processing function, comprising:
Input receives input digit information;
Array type processor (120) is configured to respond current system state, utilizes described input digit information and executing signal processing function code, and described function code is corresponding at least one described predetermined signal processing function;
At least one system controller (170) is configured to: detect the variation of the described system state in the described high-speed digital communication system (10); And the variation that responds described detected system state, dynamically reconfigure described array type processor (10), with the real-time or approaching signal processing function code of carrying out in real time corresponding at least one described signal processing function.
2, the described signal processing apparatus of claim 1 (158c), wherein said array type processor (120) comprises a plurality of data processors (122), the described data processor of in the processor of wherein said array type each (122) comprises the specific program storer (124) that is configured to store described signal processing function code, and wherein said a plurality of data processor (122) is operationally carried out the described signal processing function code in the specific program storer (124) that is stored in separately.
3, the described signal processing apparatus of claim 2 (158c), the behavior that wherein dynamically reconfigures the processor (120) of described array type comprises following behavior:
Respond the variation of described detected system state, from the described signal processing function code of external memory storage (130) download corresponding to described at least one described signal processing function;
Be stored to the specific program storer (124) of the signal processing function code of the described download of small part to one or more described a plurality of data processors (120); And
In described one or more described a plurality of data processors (120), carry out the signal processing function code of described download.
4, the described signal processing apparatus of claim 1 (158c), further comprise the input data-interface (110) that is configured to the described input digit input information of buffer memory, described input data-interface (110) has an output, and this output is coupled to the input of described array type processor (120).
5, the described signal processing apparatus of claim 1 (158c), further comprise output data interface (160), be configured to the digital output signal of buffer memory from the processor output of described array type, input of described output data interface tool, this input is coupled to the output of the processor of described array type.
6, the described signal processing apparatus of claim 2 (158c), wherein private memory (124) is configured to the memory block (125a-n) of a plurality of convertible selections.
7, the described signal processing apparatus of claim 2 (158c), wherein at least one system controller is configured to the variation of the described detected system state of response, selects in a plurality of memory blocks (125a-n) convertiblely.
8, the described signal processing apparatus of claim 6 (158c), each in wherein said a plurality of memory blocks (125a-n) all are configured to the signal processing function code that storage is associated with certain described predetermined signal processing function.
9, a kind ofly be used to reconfigure signal handling equipment (158c) with in real time or near the method for carrying out signal processing function in real time, described method is used for the network node of high-speed digital communication system, comprises behavior:
Receive input digit information at described network node;
Detect the variation of the state in the described network node;
Respond the variation of detected state described in the described network node, discern at least one the signal processing function that is performed; And
Dynamically reconfigure signal handling equipment (158c), responding the variation of described detected system state, in real time or near carrying out described at least one signal processing function in real time.
10, the described method of claim 9, wherein the behavior according to one or more standard detection state variation comprises in described network node: (i) channel and system data, (ii) by the main network standard defined agreement of network node in its following operation, the (iii) described input digit information that receives, and the output data that (iv) is associated with signal handling equipment.
11, the described method of claim 10, the behavior that wherein reconfigures signal handling equipment further comprises following behavior:
Respond the variation of described detected system state, obtain predetermined signal processing function code data again from external memory storage (130); And
The described signal processing function code data of obtaining again of storage in the array type processor (120) of described signal handling equipment (158c).
12, the described method of claim 11, wherein said array type processor comprises data processor (122) array (120), and each data processor (122) in described array (120) comprises the private memory (124) that is configured to storage signal processing capacity code data.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US53827504P | 2004-01-22 | 2004-01-22 | |
| US60/538,275 | 2004-01-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1910570A true CN1910570A (en) | 2007-02-07 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNA2005800029297A Pending CN1910570A (en) | 2004-01-22 | 2005-01-21 | A dynamically reconfigurable signal processing apparatus and method for use in a high speed digital communication system |
Country Status (4)
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| EP (1) | EP1709549A2 (en) |
| JP (1) | JP2007520952A (en) |
| CN (1) | CN1910570A (en) |
| WO (1) | WO2005071850A2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114661656A (en) * | 2022-05-25 | 2022-06-24 | 广州万协通信息技术有限公司 | Reconfigurable array configuration method, device, equipment and storage medium |
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| US7856246B2 (en) * | 2007-03-21 | 2010-12-21 | Nokia Corporation | Multi-cell data processor |
| JP5572527B2 (en) | 2010-11-09 | 2014-08-13 | パナソニック株式会社 | Communication processing apparatus and communication processing method |
Family Cites Families (4)
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|---|---|---|---|---|
| US6047115A (en) * | 1997-05-29 | 2000-04-04 | Xilinx, Inc. | Method for configuring FPGA memory planes for virtual hardware computation |
| US6282627B1 (en) * | 1998-06-29 | 2001-08-28 | Chameleon Systems, Inc. | Integrated processor and programmable data path chip for reconfigurable computing |
| GB2370381B (en) * | 2000-12-19 | 2003-12-24 | Picochip Designs Ltd | Processor architecture |
| US6986021B2 (en) * | 2001-11-30 | 2006-01-10 | Quick Silver Technology, Inc. | Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements |
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2005
- 2005-01-21 CN CNA2005800029297A patent/CN1910570A/en active Pending
- 2005-01-21 EP EP05702752A patent/EP1709549A2/en not_active Withdrawn
- 2005-01-21 JP JP2006550435A patent/JP2007520952A/en active Pending
- 2005-01-21 WO PCT/IB2005/050258 patent/WO2005071850A2/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114661656A (en) * | 2022-05-25 | 2022-06-24 | 广州万协通信息技术有限公司 | Reconfigurable array configuration method, device, equipment and storage medium |
Also Published As
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| WO2005071850A2 (en) | 2005-08-04 |
| EP1709549A2 (en) | 2006-10-11 |
| WO2005071850A3 (en) | 2005-10-13 |
| JP2007520952A (en) | 2007-07-26 |
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