WO2005065144B1 - Planarization method of manufacturing a superjunction device - Google Patents
Planarization method of manufacturing a superjunction deviceInfo
- Publication number
- WO2005065144B1 WO2005065144B1 PCT/US2004/041375 US2004041375W WO2005065144B1 WO 2005065144 B1 WO2005065144 B1 WO 2005065144B1 US 2004041375 W US2004041375 W US 2004041375W WO 2005065144 B1 WO2005065144 B1 WO 2005065144B1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- doped region
- conductivity type
- mesa
- trenches
- main surface
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract 6
- 239000002019 doping agent Substances 0.000 claims abstract 16
- 239000004065 semiconductor Substances 0.000 claims abstract 15
- 239000000758 substrate Substances 0.000 claims abstract 12
- 238000000151 deposition Methods 0.000 claims abstract 3
- 238000005530 etching Methods 0.000 claims abstract 3
- 230000001590 oxidative Effects 0.000 claims abstract 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims 6
- 239000007943 implant Substances 0.000 claims 4
- 239000011521 glass Substances 0.000 claims 3
- 238000000034 method Methods 0.000 claims 3
- 238000009792 diffusion process Methods 0.000 claims 2
- 238000009413 insulation Methods 0.000 claims 2
Abstract
A method of manufacturing a semiconductor device includes providing a substrate having first and second main surfaces. The substrate has a heavily doped region of a first conductivity at the second main surface and has a lightly doped region of the first conductivity at the first main surface. The method includes providing trenches and mesas in the substrate, implanting, at an angle, a dopant of the first conductivity into a sidewall of a mesa and implanting, at an angle, a dopant of a second conductivity into the mesa at another sidewall. The method includes oxidizing the sidewalls and bottoms of each trench and tops of the mesas to create a top oxide layer, etching back the top oxide layer to expose a portion of the mesa, depositing an oxide layer to cover the etched back top layer and mesa and planarizing the top surface of the device.
Claims
1. A method of manufacturing a semiconductor device comprising;
providing a semiconductor substrate having first and second main surfaces opposite to each other, the semiconductor substrate having a heavily doped region of a first conductivity type at the second main surface and having a lightly doped region of the first conductivity type at the first main surface;
forming in the semiconductor substrate a plurality of trenches and a plurality of mesas, each of the plurality of trenches having a first extending portion extending from the first main surface toward the heavily doped region to a first depth position, each of the plurality of trenches being disposed between adjacent mesas, each of the plurality of mesas having sidewall surfaces;
implanting a dopant of the first conductivity type into a preselected mesa region of the semiconductor substrate at a sidewall surface of one mesa so as to form at the sidewall surface of the at least one mesa a first doped region of the first conductivity type having a doping concentration lower than that of the heavily doped region;
implanting a dopant of the second conductivity type into the preselected mesa region at a sidewall surface opposite to the sidewall implanted with the dopant of the first conductivity type, to provide a second doped region of the second conductivity type at the sidewall surface opposite to the sidewall implanted with the dopant of the first conductivity type;
oxidizing the sidewalls and bottoms of at least the trenches adjacent to the preselected mesa region and the top of the preselected mesa region to create a top oxide layer;
etching back the top oxide layer to expose a preselected portion of the preselected mesa; depositing an oxide layer using a process selected from a group that includes tetraethylorthosilicate (TEOS) and spun-on-glass (SOG) oxide deposition to cover the etched back top layer and preselected mesa; and
planarizing the top surface of the device.
2. The method according to claim 1 , further comprising:
providing a third doped region of the second conductivity type at the first main surface of the first and second doped regions to be electrically connected to the second doped region;
providing a fourth doped region of the first conductivity type at at least one of the first main surface and a sidewall surface of the one tronch such that the fourth doped region is opposite to the first doped region with the third doped region posed therebetween; and
providing a gate electrode layer opposite to the third doped τegion between the first and fourth doped regions, with a gate insulation layer interposed therebetween.
3. The method according to claim 2, wherein the gate electrode layer is formed on the first main surface.
4. The method according to claim 1 , further comprising:
providing a third doped region of the second conductivity type at the first main surface of the first and second doped regions to be electrically connected to the second doped region.
5. The method according to claim 1 , wherein a diffusion length of each of the dopants of the fast and second conductivity types in manufacturing the semiconductor device is longer than a distance from the sidewall surfaces of the adjacent pair of trenches to the P-N junction of the first and second doped regions.
6. A method of manufacturing a semiconductor device comprising:
providing a semiconductor substrate having first and second main surfaces opposite to each other, the semiconductor substrate having Λ heavily doped region of a first conductivity type at the second main surface and having a lightly doped region of the first conductivity type at the first main surface;
forming in the semiconductor substrate a plurality of trenches and a plurality of mesa regions, each of the plurality of mesa regions having a first extending portion extending from the first main surface toward the heavily doped region to a first depth position and having a sidewall surface, each of the plurality of mesa regions being surrounded by one of the plurality of trenches;
implanting a dopant of the first conductivity type into a preselected group of mesa regions of the plurality of mesa regions at a sidewall surface in one of the plurality of trenches to form at the sidewall surface of each of the preselected group of mesa regions a first doped region of the first conductivity type having a doping concentration lower than that of the heavily doped region;
implanting a dopant of a second conductivity type into the preselected group of mesa regions at a sidewall surface opposite to the sidewall implanted with the dopant of the first conductivity type to provide a second doped region of the second conductivity type at the sidewall surtace opposite to the sidewall implanted with the dopant of the first conductivity type; oxidizing at least the bottom of each of the trenches adjacent to the preselected group of mesa regions and sidewalls and the tops of the preselected group of mesa regions to create a top oxide layer,
etching back the top oxide layer to expose a preselected portion of the preselected group of mesa regions;
depositing an oxide layer using a process selected from a group that includes tetraethylorthosilicate (TEOS) and spun-on-glass (SOG) o>ide deposition to cover the etched back top layer and preselected mesa; and
planarizmg the top surface of the device.
7. The method according to claim 6, further comprising:
providing a third doped region of the second conductivity type at the first main surface of the first and second doped regions to be electrically connected to the second doped region;
providing a fourth doped region of the first conductivity type at one of the first main surface and a sidewall surface of the one trench such that the fourth doped region is opposite to the first doped region with the third doped region posed therebetween; and
providing a gate electrode layer opposite to the third doped region between the first and fourth doped regions, with a gate insulation layer interposed therebetween.
8. The method according to claim 6, wherein the gate electrode layer is armed on the first main surface.
9. The method according to claim 6, further comprising: providing a third doped region of the second conductivity type at the first main surface of the first and second doped τegions to be electrically connected to the second doped region.
10. The method according to claim 6, further comprising:
providing an electrode layer in ohmic contact with the first doped region.
11. The method according to claim 6, wherein a diffusion length of each of the dopants of the fast and second conductivity types in manufacturing the semiconductor device is longer than a distance from the sidewall surfaces of the adjacent pair of trenches to a P-N junction of the first and second doped regions.
12. The method according to claim 1 , wherein each of the plurality of trenches has an approximate equal width relative to the other trenches.
13. The method according to claim 1 , wherein each of the sidewall surfaces has a predetermined inclination angle maintained relative to the first main surface.
14. The method according to claim 1, wherein the implanting of the dopant of the first conductivity type is performed at a first predetermined angle of implant.
15. The method according to claim 1 , wherein the implanting of the dopant of the second conductivity type is performed at a second predetermined angle of implant.
16. The method according to claim 6, wherein each of the plurality of trenches has an approximate equal width relative to the other trenches.
17. The method according to claim 6, wherein each of the sidewall surfaces has a predetermined inclination angle maintained relative to the first main surface.
18. The method according to claim 6, wherein the implanting of the dopant of the first conductivity type is performed at a first predetermined angle of implant.
19. The method according to claim 6, wherein the implanting of the dopant of the second conductivity type is performed at a second predetermined angle of implant.
20. A semiconductor device comprising:
a semiconductor substrate having first and second main surfaces opposite to each other, the semiconductor substrate having a heavily doped region of a first conductivity type at the second main surface and having a lightly doped region of the first conductivity type at the first main surface,
the first main surface including a plurality of trenches and a plurality of mesas, each of the plurality of trenches having a first extending portion extending from the first main surface toward the heavily doped region to a first depth position, each of the plurality of trenches being disposed between adjacent mesas, each of the plurality of mesas having sidewall surfaces;
a first doped region of the first conductivity type having a doping concentration lower than that of the heavily doped region formed at a sidewall surface of at least one mesa; a second doped region of the second conductivity type formed at a sidewall surface opposite to the sidewaU surface having the first doped region;
a top oxide layer formed on the sidewalls and bottoms of at least the trenches adjacent to the preselected mesa region and the top of the preselected mesa region; and
a second oxide layer formed using a process selected from a group that includes tetraethylorthosilicate (TEOS) and spun-on-glass (SOQ) oxide deposition that covers at least an etched back portion of the top layer and the preselected mesa region.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006545758A JP4417962B2 (en) | 2003-12-19 | 2004-12-10 | Planarization method in the manufacture of superjunction devices |
| EP04813671A EP1706899A4 (en) | 2003-12-19 | 2004-12-10 | Planarization method of manufacturing a superjunction device |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US53146703P | 2003-12-19 | 2003-12-19 | |
| US60/531,467 | 2003-12-19 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| WO2005065144A2 WO2005065144A2 (en) | 2005-07-21 |
| WO2005065144A3 WO2005065144A3 (en) | 2006-03-02 |
| WO2005065144B1 true WO2005065144B1 (en) | 2006-04-20 |
Family
ID=34748767
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US2004/041375 WO2005065144A2 (en) | 2003-12-19 | 2004-12-10 | Planarization method of manufacturing a superjunction device |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US7199006B2 (en) |
| EP (1) | EP1706899A4 (en) |
| JP (1) | JP4417962B2 (en) |
| KR (1) | KR100879588B1 (en) |
| TW (1) | TWI353621B (en) |
| WO (1) | WO2005065144A2 (en) |
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2004
- 2004-12-10 JP JP2006545758A patent/JP4417962B2/en not_active Expired - Fee Related
- 2004-12-10 EP EP04813671A patent/EP1706899A4/en not_active Withdrawn
- 2004-12-10 WO PCT/US2004/041375 patent/WO2005065144A2/en active Application Filing
- 2004-12-10 US US11/009,616 patent/US7199006B2/en not_active Expired - Fee Related
- 2004-12-10 KR KR1020067014533A patent/KR100879588B1/en not_active IP Right Cessation
- 2004-12-15 TW TW093138901A patent/TWI353621B/en not_active IP Right Cessation
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