WO2005057660A1 - Small-surfaced active semiconductor component - Google Patents

Small-surfaced active semiconductor component Download PDF

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Publication number
WO2005057660A1
WO2005057660A1 PCT/FR2004/050642 FR2004050642W WO2005057660A1 WO 2005057660 A1 WO2005057660 A1 WO 2005057660A1 FR 2004050642 W FR2004050642 W FR 2004050642W WO 2005057660 A1 WO2005057660 A1 WO 2005057660A1
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WIPO (PCT)
Prior art keywords
region
type
fingers
conductivity
conductive
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PCT/FR2004/050642
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French (fr)
Inventor
Jean-Luc Morand
Jean-Baptiste Quoirin
Frédéric Lanois
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Stmicroelectronics Sa
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Application filed by Stmicroelectronics Sa filed Critical Stmicroelectronics Sa
Priority to CN2004800361610A priority Critical patent/CN1918710B/en
Priority to EP04805873A priority patent/EP1702366A1/en
Publication of WO2005057660A1 publication Critical patent/WO2005057660A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
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    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular

Definitions

  • FIGS. 1A and 1B show by way of example a perspective view and a sectional view of a conventional vertical power diode structure. This diode is formed from a substrate comprising a heavily doped N-type region 1 (N + ) and a lightly doped N-type layer 2 coated with a P-type layer 3.
  • FIG. 2 is a sectional view of a vertical power thyristor.
  • This thyristor comprises a lightly doped N-type substrate 10.
  • a box 11 of type P containing a cathode region 12 of type N.
  • a layer 13 of anode of type P On the side of the lower surface is formed a metallization of anode MA, a metallization of cathode MK and a MG trigger metallization.
  • a P type peripheral isolation wall 15 is generally provided.
  • the term "LED” refers to a PN or Schottky diode for use as a power diode, protective or ava ⁇ lanche.
  • a diode is a dipole component having two terminals intended to be connected to elements of an electric or electronic circuit, discrete or integrated, to, as the case may be, allow a direct current to flow and block a reverse current (rectifier diode ), or on the contrary let reverse current pass when the voltage across its terminals exceeds a certain threshold (protection diode).
  • the separation surface between the isolation wall 15 of type P and the substrate 1 of type N is never intended to be passable, but only or else to allow the periphery of the component to be isopotential, to the potential of the rear face, or else to isolate the box 1 from an adjacent box containing another component.
  • This separation surface is not associated with terminals intended to be connected to elements of an electrical or electronic circuit.
  • Such a separation surface does not constitute a diode (sometimes passable sometimes blocked) linked to terminals for connection to a circuit.
  • a disadvantage of vertical components lies in their resistance in the on state. In fact, the thicknesses of the various layers and regions are optimized as a function of the desired characteristics of the diode.
  • the thickness of the N 2 (diode) or 10 (thyristor) type layer must be high enough for the component to have a desired breakdown voltage but must be as low as possible to limit the resistance to the on state of the component ⁇ health.
  • the N + 1 layer has no active role in the operation of the diode. It simply serves to ensure ohmic contact with the metallization and is used to reduce the resistance of the diode in the on state linked to the fact that a silicon wafer has in current technologies a thickness of 300 to 500 ⁇ m, in the in most cases much greater than the desired thickness of the N 2 layer (for example 60 ⁇ m to support 600 V).
  • the thickness of the layer 10 is also imposed by the thick ⁇ sor of the silicon wafer and various means, often complex, are implemented to reduce it.
  • Another disadvantage of vertical components is that the surface of the active junction is bonded to the surface of the semiconductor chip occupied by the component, these junctions being horizontal (in planes parallel to the faces princi ⁇ blades of the diode).
  • such components intended to withstand high voltages pose numerous problems for ensuring the voltage withstand at the periphery of the semiconductor or Schottky junction, as well as for isolating the component as a whole and ensuring its protection (wall of isolation).
  • FIGS. 3A and 3B are a sectional view and a partial top view of an example of a conventional multicell vertical power MOS transistor structure.
  • This transistor is formed from a lightly doped N type layer or substrate 21 comprising on the side of its rear face a heavily doped N type layer (N +). Contrary to what is represented, the N + layer can be much thicker than the substrate N.
  • boxes P are formed comprising a more heavily doped central part 23 and a less lightly doped peripheral part 24. Substantially at the center of these boxes P, is formed a ring 25 highly doped of type N.
  • the part 26 of the box P external to the ring N 25 is surmounted by a conductive grid 27 insulated by a thin insulating layer 28.
  • the upper surface and the lateral surface of the grid 27 are insulated by an insulating layer 29 and the assembly is coated with an MS source metallization.
  • the underside of the compo ⁇ sant is coated with a drain metallization MD. All the gates 27 are connected to a common gate terminal, not shown.
  • FIG. 3B is a top view of the structure without the grid and the metallization of source MS.
  • the same elements are designated therein by the same references as in FIG. 3A.
  • each cell has been represented in a square pattern. Other forms are possible and commonly used.
  • the source is negative with respect to the drain and the grid is suitably polarized, the current flows from the drain to the source passing through the channel region according to the arrows I illustrated in FIGS. 3A and 3B in a portion of the structure . Similar currents flow from each of the cells. These currents flow essentially vertically, hence the name of vertical MOS transistor.
  • a drawback of MOS transistors. of vertical power lies in their resistance in the passing state.
  • the thickness of the N-type layer 21 must be high enough for the component to have a desired breakdown voltage but must be as small as possible to limit the resistance in the on state of the component.
  • the N + 22 layer is used to make an ohmic drain contact on the rear face. Its thickness could be reduced to a few micrometers, but this would lead to too thin silicon wafer thicknesses ( ⁇ 100 ⁇ m), incompatible with current production tools. So we use very thick N + 22 layers (a few hundred micrometers). This layer then introduces an additional series resistance which reduces the performance in the on state of the transistor.
  • MOS transistor Another disadvantage of vertical components of the MOS type is that the channel width (perimeter of the P 24 wells) depends in particular on the surface of the semiconductor chip occupied by the transistor and cannot be increased beyond certain limits.
  • MOS power components or high vertical voltage for example chilled ⁇ twisted insulated gate bipolar (IGBT) and other components to control voltage, MOS or Schottky-MOS, to enrichment or depletion.
  • IGBT chilled ⁇ twisted insulated gate bipolar
  • the present invention aims to provide new types of diodes and more generally new types of power or high voltage semiconductor components making it possible to avoid at least some of the aforementioned drawbacks of vertical components, in particular to increase the active junction surface relative to the surface of the chip in which the component is formed, to reduce the voltage drop in the on state, to simplify the peripheral structure of the individual components ...
  • the present invention provides a semiconductor component in which the active junctions extend perpendicular to the surface of a semiconductor chip substantially over the entire thickness thereof.
  • the contacts with the regions to be connected are taken by conductive fingers crossing substantially the entire region with which it is desired to establish contact.
  • the conductive fingers are metallic fingers.
  • the semiconductor component is of the multicellular type and the junctions consist of several cylinders perpendicular to the main faces of the substrate.
  • the active junctions extend according to at least one cylinder perpendicular to the main faces of a semiconductor chip substantially over the entire thickness thereof, the said cylinder or said cylinders having, in section, a section in the form of a wavy closed curve.
  • the wavy curve is a Sierpinski curve type curve.
  • the contacts with the regions to be connected are taken by conductive fingers perpendicular to the main faces of the semiconductor chip and passing through substantially the entire region with which it is desired to establish contact.
  • said at least one conductive finger integral with the outermost semiconductor layer constitutes a cylinder or cylinder portions surrounding said outermost semiconductor layer.
  • the semiconductor component is a diode, a bipolar transistor, a thyristor, a power MOS transistor, an IGBT transistor, and assemblies of such components.
  • FIG. 1A and 1B described above, are a perspective view and a schematic sectional view of a vertical diode structure classic;
  • Figure 2, described above, is a schematic sectional view of a conventional vertical thyristor structure;
  • Figures 3A and 3B, described above, are schematic sectional views from above of a conventional vertical MOS transistor structure;
  • Figure 4 is a schematic perspective view of an embodiment of a diode according to the invention;
  • Figure 5 is a schematic perspective view of an embodiment of a diode according to the invention;
  • Figure 6A is a schematic perspective view of another embodiment of a diode according to the present invention;
  • Figure 6B is a schematic top view of a diode cell according to the present invention;
  • FIGS. 6C is a schematic top view of an alternative diode according to the present invention
  • Figure 7 is a schematic top view of a sea of diode cells according to the present invention
  • Figures 8A and 8B are respectively a schematic sectional view and a circuit diagram of a diode according to the present invention
  • FIGS. 9A and 9B are respectively a schematic sectional view and a circuit diagram of an assembly of diodes according to the present invention
  • FIGS. 10A and 10B are respectively a schematic sectional view and a circuit diagram of another assembly of diodes according to the present invention
  • FIGS. 11A and 11B are respectively a schematic sectional view and a circuit diagram of another assembly of diodes according to the present invention
  • FIGS. 12A and 12B are respectively a schematic sectional view and a circuit diagram of another assembly of diodes according to the present invention
  • Figures 13A and 13B are a schematic perspective view and a sectional view of a bipolar transistor according to the present invention
  • Figures 14A and 14B are a schematic perspective view and a sectional view of a thyristor according to the present invention
  • FIG. 15A is a schematic sectional view of an embodiment of MOS transistor according to the invention
  • FIG. 15B is a schematic top view of an embodiment of MOS transistor according to the invention
  • FIG. 15C is a schematic top view of another embodiment of MOS transistor according to the invention
  • FIGS. 16A and 16B are respectively a circuit diagram and a schematic sectional view of a parallel and opposite assembly of two IGBT transistors according to the invention; and FIGS. 17A and 17B are respectively a circuit diagram and a schematic sectional view of an assembly of a MOS transistor according to the invention and of a fast diode.
  • FIGS. 17A and 17B are respectively a circuit diagram and a schematic sectional view of an assembly of a MOS transistor according to the invention and of a fast diode.
  • FIG. 4 is a schematic perspective view of a portion of semiconductor component in which is made a set of diode cells according to the present invention.
  • the main faces of the component correspond to the upper and lower faces of a semiconductor wafer and the vertical face, the thickness of which is designated by e, corresponds to the thickness of the semiconductor wafer.
  • the junction of each diode cell is carried out vertically in the thickness of the semiconductor wafer.
  • the structure is produced from a lightly doped silicon wafer 31 of type N.
  • a plate-shaped metallization 32 formed vertically in a trench extends over the entire height or over most of the height of the semiconductor wafer.
  • a P-type region 33 is adjacent to part of the wafer
  • the junction of the diode is a vertical junction between regions N and P 31 and 33. It is only useful to plan between region N and metallization
  • FIG. 5 represents a variant topology of a multicellular diode according to the present invention, it being understood that in certain cases it will be possible to use a single diode cell.
  • the structure is again formed in an N-type substrate 31, the thickness of which is designated by e.
  • the metallizations instead of corresponding to plates formed in parallel trenches, consist of cylindrical fingers.
  • One way to achieve such a structure is to form from a surface of the edge of the first openings 32 preferably extending over the entire height e of the substrate.
  • Second openings 34 staggered relative to the openings 32, also preferably extend over the entire height of the substrate.
  • a short N + diffusion (not shown) is formed from these second openings which are filled with metal to constitute vias 34.
  • All vias 32 are connected together and all vias 34 are connected together by metallizations of anode and cathode, not shown, insulating layers, not shown, providing the necessary insulation. Is obtained between these metallizations, eg respectively formed on the upper and lower faces of the structure, a vertical diode junctions low resis tance ⁇ in the on state and much higher density which could be achieved with a conventional diode with horizontal junction.
  • FIG. 6A is a schematic perspective view of an embodiment of the present invention which constitutes a currently preferred variant of the embodiment described in relation to FIG. 5.
  • the contour of the section of each cylinder corresponds to a fractal curve and more particularly to a Sierpinski type curve which will be called hereinafter for simplicity and embarrassed- “wavy curve” realization.
  • Figure 6B is an enlarged top view of a pattern of Figure 6A.
  • FIG. 6C represents fractal curves of
  • FIG. 7 is a top view of a silicon wafer in which a large number of vertical cylinders with a section in the form of an undulating curve has been formed, such as those of FIG. 6B constituting a sea of diode cells.
  • block A3 elementary patterns
  • FIG. 8A represents a more detailed sectional view of a structure such as that of Figures 4 to 6. Similarly elements that in Figures 4 to 6 are designated by the same references.
  • References 36 and 37 designate insulating layers.
  • the insulating layer 36 on the upper face of the substrate covers all the regions N and the insulating layer 37 on the lower face of the substrate covers all the regions P.
  • a metallization Ml on the upper face is in contact with all the vias 32 in contact with the P type regions 33 and a metallization of lower face M2 is in contact with all the vias 34 in contact with the N + 35 regions, themselves in contact with portions of the substrate N 31.
  • FIG. 8A shows the vias of the upper layer as substantially through vias and the vias of the lower layer as non-traversing vias.
  • FIG. 8B represents the equivalent diagram of the structure of FIG. 8A between the metallizations Ml and M2.
  • the junction surface of all the diode cells in parallel can be much greater than the surface of the chip containing these diode cells, and this all the more that one can use semiconductor wafers thicker than usual.
  • Another advantage of this type of manufacture is that it is possible to produce several components according to the invention on the same wafer, each of these components can easily be surrounded, if this is useful, with insulating walls formed in any chosen way.
  • FIGS. 9A and 9B represent a schematic sectional view and an equivalent diagram of two diodes or diode cells Dl and D2 in series (tandem assembly) formed in a semiconductor substrate 40 of type N.
  • the diode on the left comprises two almost through conductive fingers 41 and 42, both starting from the upper face.
  • the finger 41 is surrounded by a region P 43 and the finger 42 is surrounded by a region N + 44.
  • the right diode comprises a conductive finger 45 starting from the upper face surrounded by a region P 46 and a conductive finger 47 starting from the lower face surrounded by a region N + 48.
  • Insulating layers are produced so that an upper metallization Ml is in contact with the finger 41, an insulated metallization M3 connects the conductive fingers 42 and 45 and a metallization of the lower face M2 is in contact with the conductive finger 47.
  • a rectifier bridge can be produced.
  • the left diode is identical to the left diode in FIG. 9A and its elements are designated by the same references.
  • the right diode is also identical to the right diode in FIG.
  • FIGS. 9A and 10A are also designated by the same references.
  • the essential difference between FIGS. 9A and 10A resides in the positioning of the metallizations.
  • the metallization of the upper face M1 contacts the finger 41 and the metallization of the lower face M2 contacts the finger 47.
  • the metallization M3 short-circuiting the conducting fingers 42 and 45 is not enclosed in an insulating layer but is accessible from the upper surface.
  • the entire structure is surrounded by a wall 49 made of an insulating material.
  • FIG. 11A and FIG. 11B represent a combination of diodes constituting a bi-directional avalanche diode. This diode is formed in an N-type semiconductor substrate 50. A conductive finger 51 extending from the upper surface is surrounded by a P-type region 52 and a conductive finger. tor 53 starting from the lower surface is surrounded by a P type region 54. A metallization Ml on the upper face is in contact with the finger 51 and a metallization M2 on the lower face is in contact with the finger 53.
  • FIG. 11A and FIG. 11B represent a combination of diodes constituting a bi-directional avalanche diode. This diode is formed in an N-type semiconductor substrate 50. A conductive finger 51 extending from the upper surface is surrounded by a P-type region 52 and a conductive finger. tor 53 starting from the lower surface is surrounded by a P type region 54. A metallization Ml on the upper face is in contact with the finger 51 and a metallization M2
  • FIG. 12A is a sectional view and FIG. 12B is a circuit diagram of an assembly of two antiparallel diodes.
  • the two diodes are formed in an N-type substrate 60.
  • the diode on the left comprises a conductive finger 61 surrounded by a region P 62, integral with an upper metallization Ml.
  • a conductive finger 63 surrounded by an N + 64 region is integral with a lower metallization M2.
  • the right diode comprises a conductive finger 65 surrounded by an N + 66 type region integral with the upper metallization M1 and a conductive finger 67 surrounded by an N + region 68 integral with the lower metallization M2.
  • the two diodes are separated by an insulating wall 69.
  • FIG. 13A and 13B show a partial perspective view and a sectional view of an embodiment according to the invention of a bipolar transistor.
  • This bipolar transistor is formed in an N-type substrate 70 and comprises a heavily N-doped emitter region 71 around a central conductive finger 72 extending over all or substantially the entire thickness of the substrate.
  • a base region 73 of type P is disposed around the emitter, between the emitter and a collector region corresponding to the substrate 70. As best shown in FIG.
  • FIGS. 14A and 14B illustrate a thyristor structure in perspective and in section respectively. The structure is produced in a semiconductor substrate 80, of type N.
  • a conductive finger 81 is surrounded by a heavily doped region of type N 82 corresponding to the thyristor cathode and a P layer 83. These regions can be produced by successively diffusing, from a through or substantially through opening, a P dopant and then an N dopant or else by simultaneously diffusing dopants whose diffusion rates are suitably different.
  • the finger 81 is connected to a metallization of cathode MK.
  • Conductive fingers 84 penetrate the P-type region 83 and constitute trigger contact points secured to a trigger metallization MG.
  • conductive fingers 85 On the side of the lower face, at the periphery of the component, are made conductive fingers 85 surrounded by a P-type region 86 which constitutes the anode of the thyristor and which is connected by the fingers 85 to an anode metallization MA . It will be noted that it is possible, as is conventional in a thyristor, to trigger-cathode short-circuits located by means of conductive fingers 87 partially penetrating only in the substrate between the region N 82 and the region P 84. Layers insulating materials not referenced are intended to separate the various metallizations and to isolate the appropriate zones. The entire structure may be surrounded by an insulating wall.
  • FIG. 15A is a schematic sectional view of a portion of semiconductor wafer in which a set of cells of MOS transistors according to the present invention.
  • the main faces of the component correspond to the upper and lower faces of a semiconductor wafer, and the vertical dimension, the height of which is designated by e, corresponds to the thickness of the semiconductor wafer.
  • Figures 15B and 15C are two simplified examples of top views of the structure formed in the semiconductor substrate, both corresponding to the sectional view of Figure 15A.
  • An elementary cell according to the present invention comprises a conductive finger 111 extending over the entire thickness of the wafer or over a major part of this thickness.
  • the conductive finger 111 is bordered by a heavily doped N-type region (N +), itself bordered by an intermediate P-type region 113 then by a lightly doped N-type region 114 and a heavily doped N-type region 115 used for resumption of ohmic contact with a conductive finger 116.
  • N + heavily doped N-type region
  • the regions 112, 113, 114 and 115 and the conductive finger 116 extend substantially over the entire thickness of the substrate, and the junctions or limits between these elements are substantially vertical.
  • the conductive finger 111 corresponds to a source metallization, the region 112 to a source zone, the intermediate region 113 to the zone in which a channel can form, the region 114 to a drain zone, the region 115 to a drain contact recovery layer, and the conductive finger 116 to a drain metallization.
  • FIG. 15B is a top view of the present invention in an embodiment in which the conductive fingers are produced in the form of vertical conductive plates extending in trenches formed in a semiconductor substrate. We can see better in FIG. 15B, the embodiment of the gate of the MOS transistor according to the present invention. This grid is produced by means of spaced apart conductive fingers 121 surrounded by an insulating layer 122 extending vertically in the intermediate region 113.
  • FIG. 15B also shows conductive fingers 123 penetrating over all or part of the thickness of the substrate and making it possible to establish a short circuit between the intermediate box 113 and the source region 112, which constitutes the equivalent of the short circuit established by the source metallization MS of FIG. 3A between the ring N + 25 and the central part of the box P 23.
  • FIG. 15C illustrates in top view another embodiment of a component according to the present invention in which each MOS transistor cell has a closed contour.
  • the central source finger 111 is surrounded by an annular region 112 of the type N +, which is itself surrounded by an annular region inter ⁇ noteire 113 P-type with an annular region 114 of N type, and a annular region 115 heavily doped with N (N + ) type.
  • FIG. 15C the structure is shown as completely surrounded by a conductive ring 116.
  • this ring may be made up of a succession of conductive fingers close to each other.
  • the conductive fingers 123 have not been shown in FIG. 15C.
  • the drain, gate and source metallizations have not been shown in FIGS. 15A, 15B and 15C.
  • all the gate fingers 121 are connected to the same metallization, all the source fingers 111 to the same metallization and all the drain fingers 116 to the same metallization.
  • the drain and source metallizations are produced on two opposite faces of the semiconductor chip.
  • the grid metallization can, as desired and also simply, be carried out on the drain side or source side, which simplifies monolithic assemblies of components according to the invention.
  • the production of a component according to the present invention will appear to a person skilled in the art who may use conventional techniques for piercing openings in the form of vias or trenches, for doping from the openings thus formed, then for filling. of these openings by a conductor, for example a metal, for example copper, this filling being preceded or not by the formation of an insulating layer.
  • a conductor for example a metal, for example copper
  • the present invention applies not only to an MOS transistor but also in general to any MOS component of power or high voltage, for example bipolar insulated gate transistors (IGBT) and other components to voltage control, MOS or Schottky-MOS type, enrichment or depletion.
  • IGBT bipolar insulated gate transistors
  • the channel width per unit of area is much greater than that obtained in a diffused vertical MOS transistor (VDMOS) such as that of FIG. 3, as is the total area of the drain of the the set of cells can be larger than the area of the chip containing these cells.
  • VDMOS diffused vertical MOS transistor
  • Another advantage of the present invention is that it is possible to produce several components according to the invention in the same semiconductor wafer, each of these components can easily be surrounded by insulating walls formed in any chosen way. Examples of such assemblies will be given in FIGS. 16 and 17.
  • FIG. 16A represents the diagram of an anti-parallel assembly of two IGBT transistors according to the present invention comprising two main terminals T1 and T2 and two control terminals Gl and G2.
  • FIG. 16B represents a schematic embodiment of such an assembly in which the same elements as in FIG. 15A are designated by the same references.
  • the left part of the figure represents an IGBT transistor comprising a source finger 111-1, surrounded by an N + region 112-1, an intermediate region 113-1 crossed by gate fingers not visible in the figure.
  • An N type region 114-1 extends between region 113-1 and a P + type region 132-1 which surrounds a drain finger 116-1.
  • This assembly is separated by an isolation wall 131 from a structure arranged symmetrically with respect to this wall and comprising a drain finger 116-2 surrounded by a P + 132-2 region and separated by a weakly doped region of the type N 114-2 of an intermediate region 113-2 in which is likely to form a channel and in which penetrate gate fingers not shown. Intermediate region 113-2 is in contact with a heavily doped N-type region 112-2 in contact with a source finger 111-2.
  • each of the structures is made up of a set of cells, as described above.
  • the source fingers of the cells situated to the left of the isolation wall are integral with an upper metallization T1, as are the drain fingers 116-2 of the cells arranged to the right of the isolation wall.
  • the drain fingers 115-1 of the cells located to the left of the isolation wall are connected to a lower metallization T2 as are the source fingers 111-2 of the cells located to the right of the isolation wall.
  • the connections Gl and G2 are only shown symbolically, which it will be noted that they can, without difficulty, be made on the same face of the component.
  • This structure has, compared to the monolithic structures assembling conventional vertical IGBT transistors, the advantage that the two IGBT transistors are perfectly symmetrical and that the characteristics of these transistors are also perfectly symmetrical.
  • the structures according to the present invention also make it possible to associate MOS components as described above and bipolar components also produced with vertical junctions (orthogonal to the main faces of the substrate). FIG.
  • FIG. 17A shows an example of such an association, comprising a MOS transistor, TMOS, and a diode, D, the anode of the diode being connected to the drain of the MOS transistor.
  • This circuit constitutes an element commonly used in practice and difficult to integrate by conventional technologies.
  • FIG. 17B shows an embodiment of such a structure. In FIG. 17B, the left part is strictly identical to the left part in FIG. 16B except that the P type region surrounding the drain region is replaced by an N + type region to constitute a MOS transistor.
  • This MOS transistor comprises a source finger 111, a source region 112, an intermediate region 113, a drain region 114, and a drain finger 116 surrounded by a heavily doped N-type region 115.
  • This assembly is separated by an isolation wall 132 from a diode structure comprising a cathode finger 140 surrounded by a strongly 141 region N-type doped and separated, by a lightly N-type doped region 142, from an anode finger 143 surrounded by a P-type region 144.
  • the source finger of the MOS transistor is connected to a first main metallization Ml .
  • the gate fingers (not shown) are connected to a control metallization Gl.
  • the cathode finger 140 of the diode is connected to a metallization M2.
  • the drain fingers of the MOS transistor cells as well as the anode fingers 143 of the diode cells are connected to a metallization M3.
  • the metallization M3 is on the side of the rear face and the metallizations Ml, M2 and Gl on the side of the front face.
  • the various illustrated structures are likely many variations and modifications, and skilled in the art will appreciate that variations described for certain modes of Réali ⁇ tion apply to other embodiments.
  • assemblies of diode cells in parallel it will be possible, by repeating a pattern, to produce thyristors or multicellular transistors.
  • Each of the cells may be produced from parallel trenches as in FIG. 4 or be of cylindrical geometry, as in FIGS. 5 and 6. It will of course be possible to choose cylinders with a non-circular section, for example polygonal.
  • metal fingers have a thermal conductivity 2 to 3.5 times higher than the equivalent volume of silicon. These fingers can occupy a large surface and in particular the peripheral "fingers" can occupy the entire free surface between the elementary cells of a component. It will also be noted that, in the present description and the claims below, the term junction is used to denote both a contact between semiconductors of different conductivity types and a Schottky contact between a semiconductor and a material of metal or alloy type metallic.

Abstract

The invention relates to a semiconductor component whose active connections extend in a perpendicular direction with respect to the surface of a semiconductor chip substentially to the entire thickness thereof. Said connections together with connectable areas are held by conductive fingers (32, 34) which substentially pass over the entire contactable area.

Description

COMPOSANT SEMICONDUCTEUR ACTIF A SURFACE REDUITE ACTIVE SEMICONDUCTOR COMPONENT WITH REDUCED SURFACE
Domaine de l' invention La présente invention concerne un nouveau type de composant semiconducteur. La présente invention s'applique plus particulièrement aux composants de puissance et aux composants de protection destinés à supporter de hautes tensions, ces composants étant généralement qualifiés de composants discrets bien que plusieurs tels composants puissent être prévus sur une même puce, et/ou qu'ils puissent être associés à des circuits logiques prévus sur la même puce. Exposé de l' art antérieur Les figures 1A et 1B représentent à titre d'exemple une vue en perspective et une vue en coupe d'une structure de diode de puissance verticale classique. Cette diode est formée à partir d'un substrat comprenant une région 1 fortement dopée de type N (N+) et une couche 2 faiblement dopée de type N revêtue d'une couche 3 de type P. La face supérieure est revêtue d'une metallisation d'anode 4 et la face inférieure est revêtue d'une metallisation de cathode 5. La référence 6 désigne une couche isolante. La figure 2 est une vue en coupe d'un thyristor de puissance vertical. Ce thyristor comprend un substrat 10 faiblement dopé de type N. Du côté de la surface supérieure est formé un caisson 11 de type P contenant une région de cathode 12 de type N. Du côté de la surface inférieure est formée une couche 13 d'anode de type P. Il est également prévu une metallisation d'anode MA, une metallisation de cathode MK et une metallisation de gâchette MG. Pour éviter que la metallisation d'anode vienne court-circuiter le substrat 10, ou pour séparer ce thyristor d'un composant voisin, il est généralement prévu un mur d'isolement périphérique de type P 15. Incidemment, on notera que dans la présente descrip- tion, le terme "diode" désigne une diode PN ou Schottky destinée à servir en tant que diode de puissance, de protection ou à ava¬ lanche. Une diode est un composant dipolaire ayant deux bornes destinées à être connectées à des éléments d'un circuit électrique ou électronique, discret ou intégré, pour, selon le cas, laisser passer un courant en direct et bloquer un courant en inverse (diode de redressement) , ou au contraire laisser passer un courant inverse quand la tension à ses bornes dépasse un certain seuil (diode de protection) . Dans le thyristor de la figure 2, la surface de séparation entre le mur d'isolement 15 de type P et le substrat 1 de type N n'est jamais destinée à être passante, mais seulement ou bien à permettre que la périphérie du composant soit isopotentielle, au potentiel de la face arrière, ou bien à isoler le caisson 1 d'un caisson adjacent contenant un autre composant. Cette surface de séparation n'est pas associée à des bornes destinées à être connectées à des éléments d'un circuit électrique ou électronique. Une telle surface de séparation ne constitue pas une diode (tantôt passante tantôt bloquée) liée à des bornes de connexion à un circuit. Un inconvénient des composants verticaux réside dans leur résistance à l'état passant. En effet, les épaisseurs des diverses couches et régions, sont optimisées en fonction des caractéristiques souhaitées de la diode. En particulier, l'épaisseur de la couche de type N 2 (diode) ou 10 (thyristor) doit être suffisamment élevée pour que le composant ait une tension de claquage désirée mais doit être aussi faible que possible pour limiter la résistance à l'état passant du compo¬ sant. Dans le cas d'une diode, la couche N+ 1 n'a aucun rôle actif dans le fonctionnement de la diode. Elle sert simplement à assurer un contact ohmique avec la metallisation et est utilisée pour réduire la résistance de la diode à l'état passant liée au fait qu'une plaquette de silicium a dans les technologies courantes une épaisseur de 300 à 500 um, dans la plupart des cas bien supérieure à l'épaisseur souhaitée de la couche N 2 (par exemple 60 μm pour supporter 600 V) . Dans le cas du thyristor, l'épaisseur de la couche 10 est également imposée par l'épais¬ seur de la plaquette de silicium et divers moyens, souvent complexes, sont mis en oeuvre pour la réduire. Un autre inconvénient des composants verticaux est que la surface des jonctions actives, est liée à la surface de la puce semiconductrice occupée par le composant, ces jonctions étant horizontales (dans des plans parallèles aux faces princi¬ pales de la diode) . De plus, de tels composants destinés à supporter de hautes tensions, posent de nombreux problèmes pour assurer la tenue en tension à la périphérie de la jonction semiconductrice ou Schottky, ainsi que pour isoler le composant dans son ensemble et assurer sa protection (mur d'isolement) . On a décrit uniquement à titre d'exemple de composants verticaux une diode PNN+ et un thyristor, les problèmes indiqués ci-dessus concernent de façon générale les composants de puissance ou haute tension verticaux, par exemple des diodes Schottky, des commutateurs bidirectionnels, ou des composants à commande en tension, de type MOS . Les figures 3A et 3B sont une vue en coupe et une vue de dessus partielles d'un exemple de structure de transistor MOS de puissance vertical multicellulaire classique. Ce transistor est constitué à partir d'une couche ou substrat 21 faiblement dopé de type N comportant du côté de sa face arrière une couche 22 fortement dopée de type N (N+) . Contrairement à ce qui est représenté, la couche N+ peut être beaucoup plus épaisse que le substrat N. Du côté de la surface supérieure du substrat 21, sont formés des caissons P comprenant une partie centrale plus fortement dopée 23 et une partie périphérique plus faiblement dopée 24. Sensiblement au centre de ces caissons P, est formé un anneau 25 fortement dopé de type N. La partie 26 du caisson P externe à l'anneau N 25 est surmontée d'une grille conductrice 27 isolée par une mince couche isolante 28. La surface supérieure et la surface latérale de la grille 27 sont isolées par une couche isolante 29 et l'ensemble est revêtu d'une metallisation de source MS. La face inférieure du compo¬ sant est revêtue d'une metallisation de drain MD. Toutes les grilles 27 sont reliées à une borne de grille commune non représentée . La figure 3B est une vue de dessus de la structure sans la grille et la metallisation de source MS. De mêmes éléments y sont désignés par les mêmes références qu'en figure 3A. Pour la simplicité de la figure, on a représenté chaque cellule selon un motif carré. D'autres formes sont possibles et couramment utilisées. Quand la source est négative par rapport au drain et que la grille est convenablement polarisée, le courant s'écoule du drain à la source en passant par la région de canal selon les flèches I illustrées en figures 3A et 3B dans une portion de la structure. Des courants similaires circulent à partir de chacune des cellules. Ces courants s'écoulent essentiel- lement verticalement, d'où l'appellation de transistor MOS vertical. Un inconvénient des transistors MOS. de puissance verticaux réside dans leur résistance à l'état passant. En effet, des considérations pratiques rendent difficile d'opti- miser les épaisseurs des diverses couches et régions en fonction des caractéristiques souhaitées du transistor. En particulier, l'épaisseur de la couche 21 de type N doit être suffisamment élevée pour que le composant ait une tension de claquage désirée mais doit être aussi faible que possible pour limiter la résis- tance à l'état passant du composant. La couche N+ 22 sert à prendre un contact ohmique de drain sur la face arrière. Son épaisseur pourrait être réduite à quelques micromètres, mais cela conduirait à des épaisseurs de plaquette de silicium trop fines (<100 μm) , incompatibles avec les outils de production actuels. Aussi utilise-t-on des couches N+ 22 très épaisses (quelques centaines de micromètres) . Cette couche introduit alors une résistance série additionnelle qui réduit les performances à l'état passant du transistor. Un autre inconvénient des composants verticaux de type MOS est que la largeur de canal (périmètre des caissons P 24) dépend en particulier de la surface de la puce semiconductrice occupée par le transistor et ne peut être augmentée au-delà de certaines limites. On a décrit, uniquement à titre d'exemple de composant vertical de type MOS, un transistor MOS. Les problèmes indiqués ci-dessus concernent de façon générale les composants MOS de puissance ou haute tension verticaux, par exemple des transis¬ tors bipolaires à grille isolée (IGBT) et autres composants à commande en tension, de type MOS ou Schottky-MOS, à enrichisse- ment ou à déplétion. Résumé de l'invention La présente invention vise à prévoir de nouveaux types de diodes et plus généralement de nouveaux types de composants semiconducteurs de puissance ou haute tension permettant d'éviter au moins certains des inconvénients susmentionnés des composants verticaux, en particulier d'augmenter la surface de jonction active par rapport à la surface de la puce dans laquelle le composant est formé, de réduire la chute de tension à l'état passant, de simplifier la structure périphérique des composants individuels... Pour atteindre ces objets, la présente invention prévoit un composant semiconducteur dans lequel les jonctions actives s'étendent perpendiculairement à la surface d'une puce semiconductrice sensiblement sur toute l'épaisseur de celle-ci. Selon un mode de réalisation de la présente invention, les contacts avec les régions devant être connectées sont pris par des doigts conducteurs traversant sensiblement toute la région avec laquelle on souhaite établir un contact. Selon un mode de réalisation de la présente invention, les doigts conducteurs sont des doigts métalliques. Selon un mode de réalisation de la présente invention, le composant semiconducteur est de type multicellulaire et les jonctions sont constituées de plusieurs cylindres perpendicu- laires aux faces principales du substrat. Selon un mode de réalisation de la présente invention, les jonctions actives s'étendent selon au moins un cylindre perpendiculaire aux faces principales d'une puce semiconductrice sensiblement sur toute l'épaisseur de celle-ci, le ou lesdits cylindres ayant, en coupe, une section en forme de courbe fermée ondulée . Selon un mode de réalisation de la présente invention, la courbe ondulée est une courbe de type courbe de Sierpinski. Selon un mode de réalisation de la présente invention, les contacts avec les régions devant être connectées sont pris par des doigts conducteurs perpendiculaires aux faces principales de la puce semiconductrice et traversant sensiblement toute la région avec laquelle on souhaite établir un contact. Selon un mode de réalisation de la présente invention, ledit au moins un doigt conducteur solidaire de la couche semiconductrice la plus externe constitue un cylindre ou des portions de cylindre entourant ladite couche semiconductrice la plus externe . Des modes de réalisation particuliers de la présente invention sont décrits dans lesquels le composant semiconducteur est une diode, un transistor bipolaire, un thyristor, un transistor MOS de puissance, un transistor IGBT, et des assemblages de tels composants. Brève description des dessins Ces objets, caractéristiques et avantages, ainsi que d'autres de la présente invention seront exposés en détail dans la description suivante de modes de réalisation particuliers faite à titre non-limitatif en relation avec les figures jointes parmi lesquelles : les figures 1A et 1B, décrites précédemment, sont une vue en perspective et une vue en coupe schématique d' une structure de diode verticale classique ; la figure 2, décrite précédemment, est une vue en coupe schématique d'une structure de thyristor vertical classique ; les figures 3A et 3B, décrites précédemment, sont des vues schématiques en coupe et de dessus d'une structure de transistor MOS vertical classique ; la figure 4 est une vue en perspective schématique d'un mode de réalisation d'une diode selon l'invention ; la figure 5 est une vue en perspective schématique d'un mode de réalisation d'une diode selon l'invention ; la figure 6A est une vue en perspective schématique d'un autre mode de réalisation d'une diode selon la présente invention ; la figure 6B est une vue de dessus schématique d'une cellule de diode selon la présente invention ; la figure 6C est une vue de dessus schématique d'une variante de diode selon la présente invention ; la figure 7 est une vue de dessus schématique d'une mer de cellules de diode selon la présente invention ; les figures 8A et 8B sont respectivement une vue en coupe schématique et un schéma de circuit d'une diode selon la présente invention ; les figures 9A et 9B sont respectivement une vue en coupe schématique et un schéma de circuit d'un assemblage de diodes selon la présente invention ; les figures 10A et 10B sont respectivement une vue en coupe schématique et un schéma de circuit d'un autre assemblage de diodes selon la présente invention ; les figures 11A et 11B sont respectivement une vue en coupe schématique et un schéma de circuit d'un autre assemblage de diodes selon la présente invention ; les figures 12A et 12B sont respectivement une vue en coupe schématique et un schéma de circuit d'un autre assemblage de diodes selon la présente invention ; les figures 13A et 13B sont une vue en perspective schématique et une vue en coupe d'un transistor bipolaire selon la présente invention ; les figures 14A et 14B sont une vue en perspective schématique et une vue en coupe d'un thyristor selon la présente invention ; la figure 15A est une vue en coupe schématique d'un mode de réalisation de transistor MOS selon l'invention ; la figure 15B est une vue de dessus schématique d'un mode de réalisation de transistor MOS selon l'invention ; la figure 15C est une vue de dessus schématique d'un autre mode de réalisation de transistor MOS selon l'invention ; les figures 16A et 16B sont respectivement un schéma de circuit et une vue en coupe schématique d'un montage en parallèle et en opposition de deux transistors IGBT selon 1 ' invention ; et les figures 17A et 17B sont respectivement un schéma de circuit et une vue en coupe schématique d'un assemblage d'un transistor MOS selon l'invention et d'une diode rapide. Description détaillée Comme cela est classique dans le domaine de la représentation des semiconducteurs, les diverses figures ne sont pas tracées à l'échelle. Notamment, dans ces diverses figures, les dimensions latérales ont été beaucoup exagérées par rapport aux directions verticales. En effet, une plaquette de silicium a couramment une épaisseur de 300 à 500 um - et des épaisseurs plus élevées pourront être choisies pour une mise en oeuvre de l'invention - tandis que des motifs et des vias peuvent être définis selon des dimensions de l'ordre de 1 à 10 μm, ou plus, par exemple de 5 à 50 um dans certaines technologies. La figure 4 est une vue en perspective schématique d'une portion de composant semiconducteur dans laquelle est réalisé un ensemble de cellules de diodes selon la présente invention. Les faces principales du composant correspondent aux faces supérieure et inférieure d'une tranche semiconductrice et la face verticale, dont l'épaisseur est désignée par e, correspond à l'épaisseur de la tranche semiconductrice. La jonction de chaque cellule de diode est réalisée de façon verticale dans l'épaisseur de la tranche semiconductrice. En figure 4, la structure est réalisée à partir d'une tranche de silicium 31 faiblement dopée de type N. Pour chaque cellule, une metallisation 32 en forme de plaque formée vertica- lement dans une tranchée s'étend sur toute la hauteur ou sur la plus grande partie de la hauteur de la tranche semiconductrice. Une région 33 de type P est adjacente à une partie de la trancheField of the Invention The present invention relates to a new type of semiconductor component. The present invention applies more particularly to power components and to protection components intended to withstand high voltages, these components generally being qualified as discrete components although several such components may be provided on the same chip, and / or that they can be associated with logic circuits provided on the same chip. DESCRIPTION OF THE PRIOR ART FIGS. 1A and 1B show by way of example a perspective view and a sectional view of a conventional vertical power diode structure. This diode is formed from a substrate comprising a heavily doped N-type region 1 (N + ) and a lightly doped N-type layer 2 coated with a P-type layer 3. The upper face is coated with a anode metallization 4 and the lower face is coated with a cathode metallization 5. The reference 6 designates an insulating layer. Figure 2 is a sectional view of a vertical power thyristor. This thyristor comprises a lightly doped N-type substrate 10. On the side of the upper surface is formed a box 11 of type P containing a cathode region 12 of type N. On the side of the lower surface is formed a layer 13 of anode of type P. There is also provided a metallization of anode MA, a metallization of cathode MK and a MG trigger metallization. To prevent the anode metallization from short-circuiting the substrate 10, or to separate this thyristor from a neighboring component, a P type peripheral isolation wall 15 is generally provided. Incidentally, it will be noted that in the present tion descriptions, the term "LED" refers to a PN or Schottky diode for use as a power diode, protective or ava ¬ lanche. A diode is a dipole component having two terminals intended to be connected to elements of an electric or electronic circuit, discrete or integrated, to, as the case may be, allow a direct current to flow and block a reverse current (rectifier diode ), or on the contrary let reverse current pass when the voltage across its terminals exceeds a certain threshold (protection diode). In the thyristor of FIG. 2, the separation surface between the isolation wall 15 of type P and the substrate 1 of type N is never intended to be passable, but only or else to allow the periphery of the component to be isopotential, to the potential of the rear face, or else to isolate the box 1 from an adjacent box containing another component. This separation surface is not associated with terminals intended to be connected to elements of an electrical or electronic circuit. Such a separation surface does not constitute a diode (sometimes passable sometimes blocked) linked to terminals for connection to a circuit. A disadvantage of vertical components lies in their resistance in the on state. In fact, the thicknesses of the various layers and regions are optimized as a function of the desired characteristics of the diode. In particular, the thickness of the N 2 (diode) or 10 (thyristor) type layer must be high enough for the component to have a desired breakdown voltage but must be as low as possible to limit the resistance to the on state of the component ¬ health. In the case of a diode, the N + 1 layer has no active role in the operation of the diode. It simply serves to ensure ohmic contact with the metallization and is used to reduce the resistance of the diode in the on state linked to the fact that a silicon wafer has in current technologies a thickness of 300 to 500 μm, in the in most cases much greater than the desired thickness of the N 2 layer (for example 60 μm to support 600 V). In the case of the thyristor, the thickness of the layer 10 is also imposed by the thick ¬ sor of the silicon wafer and various means, often complex, are implemented to reduce it. Another disadvantage of vertical components is that the surface of the active junction is bonded to the surface of the semiconductor chip occupied by the component, these junctions being horizontal (in planes parallel to the faces princi ¬ blades of the diode). In addition, such components intended to withstand high voltages, pose numerous problems for ensuring the voltage withstand at the periphery of the semiconductor or Schottky junction, as well as for isolating the component as a whole and ensuring its protection (wall of isolation). A PNN + diode and a thyristor have only been described as an example of vertical components, the problems indicated above generally relate to vertical power or high voltage components, for example Schottky diodes, bidirectional switches, or voltage-controlled components, MOS type. FIGS. 3A and 3B are a sectional view and a partial top view of an example of a conventional multicell vertical power MOS transistor structure. This transistor is formed from a lightly doped N type layer or substrate 21 comprising on the side of its rear face a heavily doped N type layer (N +). Contrary to what is represented, the N + layer can be much thicker than the substrate N. On the side of the upper surface of the substrate 21, boxes P are formed comprising a more heavily doped central part 23 and a less lightly doped peripheral part 24. Substantially at the center of these boxes P, is formed a ring 25 highly doped of type N. The part 26 of the box P external to the ring N 25 is surmounted by a conductive grid 27 insulated by a thin insulating layer 28. The upper surface and the lateral surface of the grid 27 are insulated by an insulating layer 29 and the assembly is coated with an MS source metallization. The underside of the compo ¬ sant is coated with a drain metallization MD. All the gates 27 are connected to a common gate terminal, not shown. FIG. 3B is a top view of the structure without the grid and the metallization of source MS. The same elements are designated therein by the same references as in FIG. 3A. For the simplicity of the figure, each cell has been represented in a square pattern. Other forms are possible and commonly used. When the source is negative with respect to the drain and the grid is suitably polarized, the current flows from the drain to the source passing through the channel region according to the arrows I illustrated in FIGS. 3A and 3B in a portion of the structure . Similar currents flow from each of the cells. These currents flow essentially vertically, hence the name of vertical MOS transistor. A drawback of MOS transistors. of vertical power lies in their resistance in the passing state. Indeed, practical considerations make it difficult to optimize the thicknesses of the various layers and regions as a function of the desired characteristics of the transistor. In particular, the thickness of the N-type layer 21 must be high enough for the component to have a desired breakdown voltage but must be as small as possible to limit the resistance in the on state of the component. The N + 22 layer is used to make an ohmic drain contact on the rear face. Its thickness could be reduced to a few micrometers, but this would lead to too thin silicon wafer thicknesses (<100 μm), incompatible with current production tools. So we use very thick N + 22 layers (a few hundred micrometers). This layer then introduces an additional series resistance which reduces the performance in the on state of the transistor. Another disadvantage of vertical components of the MOS type is that the channel width (perimeter of the P 24 wells) depends in particular on the surface of the semiconductor chip occupied by the transistor and cannot be increased beyond certain limits. There has been described, solely by way of example of a vertical component of MOS type, a MOS transistor. The problems indicated above relate generally to the MOS power components or high vertical voltage, for example chilled ¬ twisted insulated gate bipolar (IGBT) and other components to control voltage, MOS or Schottky-MOS, to enrichment or depletion. SUMMARY OF THE INVENTION The present invention aims to provide new types of diodes and more generally new types of power or high voltage semiconductor components making it possible to avoid at least some of the aforementioned drawbacks of vertical components, in particular to increase the active junction surface relative to the surface of the chip in which the component is formed, to reduce the voltage drop in the on state, to simplify the peripheral structure of the individual components ... To achieve these objects, the present invention provides a semiconductor component in which the active junctions extend perpendicular to the surface of a semiconductor chip substantially over the entire thickness thereof. According to an embodiment of the present invention, the contacts with the regions to be connected are taken by conductive fingers crossing substantially the entire region with which it is desired to establish contact. According to an embodiment of the present invention, the conductive fingers are metallic fingers. According to an embodiment of the present invention, the semiconductor component is of the multicellular type and the junctions consist of several cylinders perpendicular to the main faces of the substrate. According to an embodiment of the present invention, the active junctions extend according to at least one cylinder perpendicular to the main faces of a semiconductor chip substantially over the entire thickness thereof, the said cylinder or said cylinders having, in section, a section in the form of a wavy closed curve. According to an embodiment of the present invention, the wavy curve is a Sierpinski curve type curve. According to an embodiment of the present invention, the contacts with the regions to be connected are taken by conductive fingers perpendicular to the main faces of the semiconductor chip and passing through substantially the entire region with which it is desired to establish contact. According to an embodiment of the present invention, said at least one conductive finger integral with the outermost semiconductor layer constitutes a cylinder or cylinder portions surrounding said outermost semiconductor layer. Particular embodiments of the present invention are described in which the semiconductor component is a diode, a bipolar transistor, a thyristor, a power MOS transistor, an IGBT transistor, and assemblies of such components. Brief Description of the Drawings These objects, features and advantages, as well as others of the present invention will be explained in detail in the following description of particular embodiments given without limitation in relation to the appended figures in which: FIGS. 1A and 1B, described above, are a perspective view and a schematic sectional view of a vertical diode structure classic; Figure 2, described above, is a schematic sectional view of a conventional vertical thyristor structure; Figures 3A and 3B, described above, are schematic sectional views from above of a conventional vertical MOS transistor structure; Figure 4 is a schematic perspective view of an embodiment of a diode according to the invention; Figure 5 is a schematic perspective view of an embodiment of a diode according to the invention; Figure 6A is a schematic perspective view of another embodiment of a diode according to the present invention; Figure 6B is a schematic top view of a diode cell according to the present invention; FIG. 6C is a schematic top view of an alternative diode according to the present invention; Figure 7 is a schematic top view of a sea of diode cells according to the present invention; Figures 8A and 8B are respectively a schematic sectional view and a circuit diagram of a diode according to the present invention; FIGS. 9A and 9B are respectively a schematic sectional view and a circuit diagram of an assembly of diodes according to the present invention; FIGS. 10A and 10B are respectively a schematic sectional view and a circuit diagram of another assembly of diodes according to the present invention; FIGS. 11A and 11B are respectively a schematic sectional view and a circuit diagram of another assembly of diodes according to the present invention; FIGS. 12A and 12B are respectively a schematic sectional view and a circuit diagram of another assembly of diodes according to the present invention; Figures 13A and 13B are a schematic perspective view and a sectional view of a bipolar transistor according to the present invention; Figures 14A and 14B are a schematic perspective view and a sectional view of a thyristor according to the present invention; FIG. 15A is a schematic sectional view of an embodiment of MOS transistor according to the invention; FIG. 15B is a schematic top view of an embodiment of MOS transistor according to the invention; FIG. 15C is a schematic top view of another embodiment of MOS transistor according to the invention; FIGS. 16A and 16B are respectively a circuit diagram and a schematic sectional view of a parallel and opposite assembly of two IGBT transistors according to the invention; and FIGS. 17A and 17B are respectively a circuit diagram and a schematic sectional view of an assembly of a MOS transistor according to the invention and of a fast diode. Detailed description As is conventional in the field of the representation of semiconductors, the various figures are not drawn to scale. In particular, in these various figures, the lateral dimensions have been greatly exaggerated with respect to the vertical directions. Indeed, a silicon wafer commonly has a thickness of 300 to 500 μm - and greater thicknesses can be chosen for an implementation of the invention - while patterns and vias can be defined according to dimensions of the order of 1 to 10 μm, or more, for example from 5 to 50 μm in certain technologies. Figure 4 is a schematic perspective view of a portion of semiconductor component in which is made a set of diode cells according to the present invention. The main faces of the component correspond to the upper and lower faces of a semiconductor wafer and the vertical face, the thickness of which is designated by e, corresponds to the thickness of the semiconductor wafer. The junction of each diode cell is carried out vertically in the thickness of the semiconductor wafer. In FIG. 4, the structure is produced from a lightly doped silicon wafer 31 of type N. For each cell, a plate-shaped metallization 32 formed vertically in a trench extends over the entire height or over most of the height of the semiconductor wafer. A P-type region 33 is adjacent to part of the wafer
31 de type N et une metallisation 34 en forme de plaque s'étend verticalement dans une tranchée adjacente à ladite partie de la tranche 31 de type N. Ainsi, la jonction de la diode est une jonction verticale entre les régions N et P 31 et 33. Il est seulement utile de prévoir entre la région N et la metallisation31 of type N and a metallization 34 in the form of a plate extends vertically in a trench adjacent to said part of the wafer 31 of type N. Thus, the junction of the diode is a vertical junction between regions N and P 31 and 33. It is only useful to plan between region N and metallization
32 une très fine couche de type N+ (non représentée) pour assurer le contact ohmique sans qu'il soit nécessaire comme dans le cas des diodes classiques de prévoir une région N+ épaisse. Ainsi, la chute de tension à l'état passant dans la diode est réduite . La figure 5 représente une variante de topologie d'une diode multicellulaire selon la présente invention, étant entendu que dans certains cas on pourra utiliser une seule cellule de diode. La structure est à nouveau formée dans un substrat 31 de type N dont l'épaisseur est désignée par e. Les métallisations, au lieu de correspondre à des plaques formées dans des tranchées parallèles sont constituées de doigts cylindriques. Une façon de réaliser une telle structure est de former à partir d'une surface de la tranche des premières ouvertures 32 s 'étendant de préférence sur toute la hauteur e du substrat. A partir de ces ouvertures est formée une diffusion 33 de type P, puis ces ouvertures sont remplies de métal pour constituer des vias 32. Des deuxièmes ouvertures 34, en quinconce par rapport aux ouvertures 32, s'étendent également de préférence sur toute la hauteur du substrat. Une courte diffusion N+ (non représentée) est formée à partir de ces deuxièmes ouvertures qui sont remplies de métal pour constituer des vias 34. Tous les vias 32 sont reliés entre eux et tous les vias 34 sont reliés entre eux par des métallisations d'anode et de cathode, non représentées, des couches isolantes, non représentées, assurant les isolations nécessaires. On obtient entre ces métallisations, par exemple respectivement formées sur les faces supérieure et inférieure de la structure, une diode à jonctions verticales à faible résis¬ tance à l'état passant et de densité bien supérieure à ce qui pourrait être obtenu avec une diode classique à jonction horizontale. Ce type de structure présente en outre l'avantage d'éviter les problèmes de tenue en tension en périphérie de diode que posent les structures classiques. On notera que, au lieu de prévoir de simples doigts conducteurs 34, du métal pourrait être présent tout autour des zones 31 de type N utiles. La structure peut alors se voir comme une plaque conductrice (métallique) comportant des ouvertures contenant des éléments cylindriques concentriques comprenant un via central 32, entouré d'un cylindre semiconducteur 33 de type P, entouré d'un cylindre semiconducteur 31 de type N, éventuellement entouré d'un cylindre semiconducteur N+. La figure 6A est une vue en perspective schématique d'un mode de réalisation de la présente invention qui constitue une variante actuellement préférée du mode de réalisation décrit en relation avec la figure 5. Dans cette variante préférée, le contour de la section de chaque cylindre correspond à une courbe fractale et plus particulièrement à une courbe de type Sierpinski qu'on appellera ci-après par simplification et gêné- ralisation "courbe ondulée". Ceci permet d'augmenter la surface de jonction pour une surface de puce donnée. La figure 6B est une vue de dessus agrandie d'un motif de la figure 6A. La figure 6C représente des courbes fractales de32 a very thin layer of N + type (not shown) to ensure ohmic contact without the need, as in the case of conventional diodes, to provide a thick N + region. Thus, the voltage drop in the state passing through the diode is reduced. FIG. 5 represents a variant topology of a multicellular diode according to the present invention, it being understood that in certain cases it will be possible to use a single diode cell. The structure is again formed in an N-type substrate 31, the thickness of which is designated by e. The metallizations, instead of corresponding to plates formed in parallel trenches, consist of cylindrical fingers. One way to achieve such a structure is to form from a surface of the edge of the first openings 32 preferably extending over the entire height e of the substrate. From these openings is formed a diffusion type P, then these openings are filled with metal to form vias 32. Second openings 34, staggered relative to the openings 32, also preferably extend over the entire height of the substrate. A short N + diffusion (not shown) is formed from these second openings which are filled with metal to constitute vias 34. All vias 32 are connected together and all vias 34 are connected together by metallizations of anode and cathode, not shown, insulating layers, not shown, providing the necessary insulation. Is obtained between these metallizations, eg respectively formed on the upper and lower faces of the structure, a vertical diode junctions low resis tance ¬ in the on state and much higher density which could be achieved with a conventional diode with horizontal junction. This type of structure also has the advantage of avoiding the problems of voltage withstand at the periphery of the diode posed by conventional structures. It will be noted that, instead of providing simple conductive fingers 34, metal could be present all around the useful N type areas 31. The structure can then be seen as a conductive (metallic) plate comprising openings containing concentric cylindrical elements comprising a central via 32, surrounded by a semiconductor cylinder 33 of type P, surrounded by a semiconductor cylinder 31 of type N, possibly surrounded by an N + semiconductor cylinder. FIG. 6A is a schematic perspective view of an embodiment of the present invention which constitutes a currently preferred variant of the embodiment described in relation to FIG. 5. In this preferred variant, the contour of the section of each cylinder corresponds to a fractal curve and more particularly to a Sierpinski type curve which will be called hereinafter for simplicity and embarrassed- "wavy curve" realization. This makes it possible to increase the junction surface for a given chip surface. Figure 6B is an enlarged top view of a pattern of Figure 6A. FIG. 6C represents fractal curves of
Sierpinski légèrement modifiées, qui augmentent encore la surface de jonction. La figure 7 est une vue de dessus d'une plaquette de silicium dans laquelle on a formé un grand nombre de cylindres verticaux à section en forme de courbe ondulée tels que ceux de la figure 6B constituant une mer de cellules de diodes. On peut former des diodes de puissances différentes (pouvant laisser passer des courants plus ou moins importants) en choisissant de découper la plaquette selon 4 motifs élémentaires (bloc Al) , selon 9 motifs élémentaires (bloc A2), ou selon 16 motifs élé¬ mentaires ou plus (bloc A3) . On pourra aussi choisir des découpes selon des contours rectangulaires. Ceci présente l'avantage que, en prévoyant des plaquettes de silicium de même structure, on peut obtenir des diodes de puissance différentes en fonction de la découpe, d'où il résulte une diminution des stocks et des lignes de fabrication. On notera également que les courbes fractales perme¬ ttent un bon équilibre des surfaces anode-cathode. En outre, leur coefficient de forme permet de réaliser des gravures de cylindre en des temps beaucoup plus courts que dans le cas de cylindres à section circulaire. La description ci-dessus vise essentiellement la structure de la diode et l'ordre des étapes de fabrication pourra être modifié. Dans ce qui suit, on utilisera le terme "via" ouSierpinski slightly modified, which further increase the junction area. FIG. 7 is a top view of a silicon wafer in which a large number of vertical cylinders with a section in the form of an undulating curve has been formed, such as those of FIG. 6B constituting a sea of diode cells. Can be formed of different powers diodes (capable of passing current more or less important) electing cut the wafer into 4 unit cells (A-block), according to 9 elementary patterns (block A2), or as 16 units ele ¬ mentary or more (block A3). We can also choose cuts according to rectangular contours. This has the advantage that, by providing silicon wafers of the same structure, it is possible to obtain diodes of different power depending on the cut, which results in a reduction in stocks and production lines. Note also that the curves fractal perme ¬ ttent a good balance of anode-cathode surfaces. In addition, their shape coefficient makes it possible to produce cylinder engravings in much shorter times than in the case of cylinders with circular section. The above description essentially relates to the structure of the diode and the order of the manufacturing steps can be modified. In what follows, we will use the term "via" or
"doigt" pour désigner aussi bien les éléments en forme de plaque de la figure 4 que les éléments en forme de doigt des figures 5 et 6. La figure 8A représente une vue en coupe plus détail- lée d'une structure telle que celle des figures 4 à 6. De mêmes éléments qu'en figures 4 à 6 sont désignés par les mêmes références. Les références 36 et 37 désignent des couches isolantes. La couche isolante 36 sur la face supérieure du substrat recouvre toutes les régions N et la couche isolante 37 sur la face inférieure du substrat recouvre toutes les régions P. Une metallisation Ml de face supérieure est en contact avec tous les vias 32 en contact avec les régions de type P 33 et une metallisation de face inférieure M2 est en contact avec tous les vias 34 en contact avec les régions de type N+ 35, elles-mêmes en contact avec des portions du substrat N 31. Dans l'exemple de la figure 8A, on a représenté les vias de la couche supérieure comme des vias sensiblement traversants et les vias de la couche inférieure comme des vias non traversants. Toutefois, d'autres options pourront être prises selon les technologies de fabrication choisies. La figure 8B représente le schéma équivalent de la structure de la figure 8A entre les métallisations Ml et M2. Selon un avantage de la présente invention, la surface de jonction de l'ensemble des cellules de diodes en parallèle peut être bien supérieure à la surface de la puce contenant ces cellules de diodes, et ce d'autant plus que l'on pourra utiliser des tranches semiconductrices plus épaisses que cela n'est usuel. Un autre avantage de ce type de fabrication est qu'il est possible de réaliser plusieurs composants selon l'invention sur une même tranche, chacun de ces composants pouvant facilement être entouré, si cela est utile, de murs isolants formés de toute façon choisie. Les figures 9A et 9B représentent une vue en coupe schématique et un schéma équivalent de deux diodes ou cellules de diode Dl et D2 en série (montage tandem) formées dans un substrat semiconducteur 40 de type N. En figure 9A, la diode de gauche comprend deux doigts conducteurs presque traversants 41 et 42, partant tous deux de la face supérieure. Le doigt 41 est entouré d'une région P 43 et le doigt 42 est entouré d'une région N+ 44. La diode de droite comprend un doigt conducteur 45 partant de la face supérieure entouré d'une région P 46 et un doigt conducteur 47 partant de la face inférieure entouré d'une région N+ 48. Des couches isolantes sont réalisées de façon qu'une metallisation supérieure Ml est en contact avec le doigt 41, une metallisation isolée M3 relie les doigts conducteurs 42 et 45 et une metallisation de face inférieure M2 est en contact avec le doigt conducteur 47. Comme cela est représenté en vue en coupe partielle en figure 10A et sous forme de schéma en figure 10B, en assemblant deux couples de diodes telles que les diodes Dl et D2 des figures 9A et 9B, et en prévoyant des murs isolants, on peut réaliser un pont redresseur. En figure 10A, la diode de gauche est identique à la diode de gauche de la figure 9A et ses éléments sont désignés par les mêmes références. La diode de droite est également identique à la diode de droite de la figure 9A et ses éléments sont aussi désignés par de mêmes références. La différence essentielle entre les figures 9A et 10A réside dans le positionnement des métallisations. Comme précédemment, la metallisation de face supérieure Ml contacte le doigt 41 et la metallisation de face inférieure M2 contacte le doigt 47. Toutefois, cette fois-ci, la metallisation M3 court-circuitant les doigts conducteurs 42 et 45 n'est pas enfermée dans une couche isolante mais est accessible depuis la surface supérieure. De plus, l'ensemble de la structure est entouré d'un mur 49 en un matériau isolant. En réalisant deux structures identiques à celle de la figure 10A, et en connectant pour ces deux structures les métallisations Ml entre elles, les métallisations M2 entre elles et les métallisations M3 à des bornes distinctes, on obtient un montage de pont redresseur tel que celui illustré en figure 10B. La figure 11A et la figure 11B représentent une combinaison de diodes constituant une diode à avalanche bidirectionnelle. Cette diode est formée dans un substrat semiconducteur de type N 50. Un doigt conducteur 51 partant de la surface supé- rieure est entouré d'une région 52 de type P et un doigt conduc- teur 53 partant de la surface inférieure est entouré d'une région 54 de type P. Une metallisation Ml de face supérieure est en contact avec le doigt 51 et une metallisation M2 de face inférieure est en contact avec le doigt 53. La figure 12A est une vue en coupe et la figure 12B est un schéma de circuit d'un montage de deux diodes en antiparallèle. Les deux diodes sont formées dans un substrat de type N 60. La diode de gauche comprend un doigt conducteur 61 entouré d'une région P 62, solidaire d'une metallisation supérieure Ml. Un doigt conducteur 63 entouré d'une région N+ 64 est solidaire d'une metallisation inférieure M2. A l'inverse, la diode de droite comprend un doigt conducteur 65 entouré d'une région de type N+ 66 solidaire de la metallisation supérieure Ml et un doigt conducteur 67 entouré d'une région N+ 68 solidaire de la metallisation inférieure M2. Les deux diodes sont séparées par un mur isolant 69. Dans les diverses figures, les doigts sont illustrés comme traversants ou non. Cela dépend des modes de réalisation et des technologies de fabrication choisies. Dans le cas de doigts traversants, leur extrémité non connectée à un contact est isolée. Les figures 13A et 13B représentent une vue en perspective partielle et une vue en coupe d'une réalisation selon l'invention d'un transistor bipolaire. Ce transistor bipo- laire est formé dans un substrat de type N 70 et comprend une région d'émetteur 71 fortement dopée de type N autour d'un doigt conducteur central 72 s 'étendant sur toute ou sensiblement toute l'épaisseur du substrat. Une région de base 73 de type P est disposée autour de l'émetteur, entre l'émetteur et une région de collecteur correspondant au substrat 70. Comme le montre mieux la figure 13B, des doigts conducteurs 74 partant de la face inférieure sont entourés de régions N+ 75 et servent de contact de collecteur. Une metallisation intermédiaire M3 du côté de la face supérieure est solidaire de doigts conducteurs 76 faisant contact avec la région de base 73. Comme l'illustre la figure 13A, les doigts conducteurs 76 sont espacés les uns des autres à la façon d'une grille pour permettre un bon fonctionnement de la base. Par contre, dans une réalisation du type de celle des figures 5 et 6, les doigts 74 pourront en fait constituer un cylindre conducteur entourant complètement la cellule de transistor représentée. Les figures 14A et 14B illustrent une structure de thyristor respectivement en perspective et en coupe. La structure est réalisée dans un substrat semiconducteur 80, de type N. Dans une région centrale, un doigt conducteur 81 est entouré d'une région fortement dopée de type N 82 correspondant à la cathode du thyristor et d'une couche P 83. Ces régions peuvent être réalisées en diffusant successivement, à partir d'une ouverture traversante ou sensiblement traversante, un dopant P puis un dopant N ou bien en diffusant simultanément des dopants dont les vitesses de diffusion sont convenablement différentes. Le doigt 81 est connecté à une metallisation de cathode MK. Des doigts conducteurs 84 pénètrent dans la région de type P 83 et constituent des prises de contact de gâchette solidaires d'une metallisation de gâchette MG. Du côté de la face inférieure, à la périphérie du composant, sont réalisés des doigts conducteurs 85 entourés d'une région de type P 86 qui constitue l'anode du thyristor et qui est reliée par les doigts 85 à une metallisation d'anode MA. On notera que l'on peut réaliser, comme cela est classique dans un thyristor, des courts-circuits gâchette- cathode localisés au moyen de doigts conducteurs 87 pénétrant partiellement seulement dans le substrat entre la région N 82 et la région P 84. Des couches isolantes non référencées sont destinées à séparer les diverses métallisations et à isoler les zones appropriées. L'ensemble de la structure pourra être entouré d'un mur isolant. Un triac pourra être réalisé en montant deux thyris- tors du type ci-dessus en parallèle et en opposition. La figure 15A est une vue en coupe schématique d'une portion de tranche semiconductrice dans laquelle est réalisé un ensemble de cellules de transistors MOS selon la présente invention. Les faces principales du composant correspondent aux faces supérieure et inférieure d'une tranche semiconductrice, et la dimension verticale, dont la hauteur est désignée par e, corres- pond à l'épaisseur de la tranche semiconductrice. Les figures 15B et 15C sont deux exemples simplifiés de vues de dessus de la structure formée dans le substrat semiconducteur, correspondant toutes deux à la vue en coupe de la figure 15A. Une cellule élémentaire selon la présente invention comprend un doigt conducteur 111 s 'étendant sur toute l'épaisseur de la tranche ou sur une majeure partie de cette épaisseur. Le doigt conducteur 111 est bordé d'une région 112 fortement dopée de type N (N+) , elle-même bordée d'une région intermé- diaire 113 de type P puis d'une région 114 faiblement dopée de type N et d'une région 115 fortement dopée de type N servant à une reprise de contact ohmique avec un doigt conducteur 116. Comme le doigt conducteur 111, les régions 112, 113, 114 et 115 et le doigt conducteur 116 s'étendent sensiblement sur toute l'épaisseur du substrat, et les jonctions ou limites entre ces éléments sont sensiblement verticales. Le doigt conducteur 111 correspond à une metallisation de source, la région 112 à une zone de source, la région intermédiaire 113 à la zone dans laquelle il peut se former un canal, la région 114 à une zone de drain, la région 115 à une couche de reprise de contact de drain, et le doigt conducteur 116 à une metallisation de drain. La figure 15B est une vue de dessus de la présente invention dans un mode de réalisation dans lequel les doigts conducteurs sont réalisés sous forme de plaques conductrices verticales s 'étendant dans des tranchées ménagées dans un substrat semiconducteur. On voit mieux en figure 15B, le mode de réalisation de la grille du transistor MOS selon la présente invention. Cette grille est réalisée au moyen de doigts conducteurs espacés 121 entourés d'une couche isolante 122 s 'étendant verticalement dans la région intermédiaire 113. Quand une tension positive est appliquée entre les doigts de grille 121 et le doigt de source 111, un canal se forme dans la zone verticale de la région intermédiaire 113 comprise entre deux doigts de grille, de sorte que le transistor MOS devient conducteur entre sa source et son drain, et un courant indiqué par les flèches I est susceptible de circuler horizontalement du drain à la source. On a décrit ci-dessus un transistor MOS à enrichissement ; dans le cas d'un transistor MOS à déplétion, la région intermédiaire 113, au moins au voisinage de l'isolant de grille serait faiblement dopée de type N et l'application d'une tension entre les doigts de grille 121 et le doigt de source 111 rendrait le transistor MOS non conducteur entre sa source et son drain. On a également représenté en figure 15B des doigts conducteurs 123 pénétrant sur tout ou partie de l'épaisseur du substrat et permettant d'établir un court-circuit entre le caisson intermédiaire 113 et la région de source 112, ce qui constitue l'équivalent du court-circuit établi par la metallisation de source MS de la figure 3A entre l'anneau N+ 25 et la partie centrale du caisson P 23. La figure 15C illustre en vue de dessus un autre mode de réalisation d'un composant selon la présente invention dans lequel chaque cellule de transistor MOS présente un contour fermé. Le doigt de source central 111 est entouré d'une région annulaire 112 de type N+, elle-même entourée d'une région inter¬ médiaire annulaire 113 de type P, d'une région annulaire 114 de type N, et d'une région annulaire 115 fortement dopée de type N (N+) . En figure 15C, on a représenté la structure comme complètement entourée d'un anneau conducteur 116. En pratique, cet anneau pourra être constitué d'une succession de doigts conducteurs voisins les uns des autres. Pour simplifier la représentation, on n'a pas représenté en figure 15C les doigts conducteurs 123. On n'a pas représenté en figures 15A, 15B et 15C les métallisations de drain, de grille et de source. On comprendra, que tous les doigts de grille 121 sont reliés à une même metallisation, tous les doigts de source 111 à une même metallisation et tous les doigts de drain 116 à une même metallisation. De préférence, comme dans un composant classique, les métallisa- tions de drain et de source sont réalisées sur deux faces opposées de la puce semiconductrice. Selon un avantage de l'invention, la metallisation de grille peut, au choix et aussi simplement, être réalisée côté drain ou côté source, ce qui simplifie des assemblages monolithiques de composants selon l'invention. La réalisation d'un composant selon la présente invention apparaîtra à l'homme de l'art qui pourra utiliser des techniques classiques de percement d'ouvertures en forme de vias ou de tranchées, de dopage à partir des ouvertures ainsi formées, puis de remplissage de ces ouvertures par un conducteur, par exemple un métal, par exemple du cuivre, ce remplissage étant précédé ou non de la formation d'une couche isolante. On comprendra que, bien que l'on emploie dans la présente description les termes vias ou doigts, ces termes recouvrent aussi les structures en forme de tranchées telles que celles de la figure 15B ou les structures en forme d'anneau telles que la metallisation 116 de la figure 15C. La description ci-dessus vise essentiellement la structure du transistor MOS et l'ordre des étapes de fabrication pourra être modifié. Comme on l'a indiqué précédemment, la présente invention s'applique non seulement à un transistor MOS mais aussi de façon générale à tout composant MOS de puissance ou haute tension, par exemple des transistors bipolaires à grille isolée (IGBT) et autres composants à commande en tension, de type MOS ou Schottky-MOS, à enrichissement ou à dépletion. Notamment, on pourra passer simplement de la structure de transistor MOS de la figure 15 à une structure d'IGBT en remplaçant la couche 115 fortement dopée de type N par une couche fortement dopée de type P. Selon un avantage de la présente invention, la largeur de canal par unité de surface est bien plus grande que celle obtenue dans un transistor MOS vertical diffusé (VDMOS) tel que celui de la figure 3, de même que la surface totale du drain de l'ensemble des cellules peut être supérieure à la surface de la puce contenant ces cellules. Un autre avantage de la présente invention est qu'il est possible de réaliser plusieurs composants selon l' invention dans une même tranche semiconductrice, chacun de ces composants pouvant facilement être entouré de murs isolants formés de toute façon choisie. Des exemples de tels assemblages vont être donnés en figures 16 et 17. La figure 16A représente le schéma d'un assemblage en anti-parallele de deux transistors IGBT selon la présente mven- tion comprenant deux bornes principales Tl et T2 et deux bornes de commande Gl et G2. Dans la description ci-après, on appellera source et drain les bornes principales du transistor IGBT pour simplifier l'analogie avec le transistor MOS décrit précédemment. La figure 16B représente un exemple de réalisation schématique d'un tel assemblage dans lequel de mêmes éléments qu'en figure 15A sont désignés par de mêmes références. La partie gauche de la figure représente un transistor IGBT comprenant un doigt de source 111-1, entouré d'une région N+ 112-1, d'une région intermédiaire 113-1 traversée par des doigts de grille non visibles dans la figure. Une région de type N 114-1 s'étend entre la région 113-1 et une région de type P+ 132-1 qui entoure un doigt de drain 116-1. Cet ensemble est séparé par un mur d'isolement 131 d'une structure disposée symétriquement par rapport à ce mur et comprenant un doigt de drain 116-2 entouré d'une région P+ 132-2 et séparé par une région faiblement dopée de type N 114-2 d'une région intermédiaire 113-2 dans laquelle est susceptible de se former un canal et dans laquelle pénètrent des doigts de grille non représentés. La région intermédiaire 113-2 est en contact avec une région fortement dopée de type N 112-2 en contact avec un doigt de source 111-2. Bien que l'on ait représenté une seule cellule, on comprendra que chacune des structures est constituée d'un ensemble de cellules, comme cela a été décrit précédemment . Les doigts de source des cellules situées à gauche du mur d'isolement sont solidaires d'une metallisation supérieure Tl, de même que les doigts de drain 116-2 des cellules disposées à droite du mur d'isolement. Les doigts de drain 115-1 des cellules situées à gauche du mur d'isolement sont reliés à une metallisation inférieure T2 de même que les doigts de source 111-2 des cellules situées à droite du mur d'isolement. On a représenté seulement de façon symbolique les connexions Gl et G2 dont on notera qu'elles peuvent, sans difficulté, être réalisées sur une même face du composant . Cette structure présente, par rapport aux structures monolithiques assemblant des transistors IGBT verticaux classiques, l'avantage que les deux transistors IGBT sont parfaitement symétriques et que les caractéristiques de ces transistors sont également parfaitement symétriques. Les structures selon la présente invention permettent en outre d'associer des composants MOS tels que décrits précédemment et des composants bipolaires également réalisés avec des jonctions verticales (orthogonales aux faces principales du substrat) . La figure 17A représente un exemple d'une telle asso- dation, comprenant un transistor MOS, TMOS, et une diode, D, l'anode de la diode étant reliée au drain du transistor MOS. Ce circuit constitue un élément couramment utilisé en pratique et difficile à intégrer par les technologies classiques. La figure 17B représente un mode de réalisation d'une telle structure. En figure 17B, la partie de gauche est strictement identique à la partie de gauche de la figure 16B sauf que la région de type P entourant la région de drain est remplacée par une région de type N+ pour constituer un transistor MOS. Ce transistor MOS comprend un doigt de source 111, une région de source 112, une région intermédiaire 113, une région de drain 114, et un doigt de drain 116 entouré d'une région 115 fortement dopée de type N. Cet ensemble est séparé par un mur d'isolement 132 d'une structure de diode comprenant un doigt de cathode 140 entouré d'une région 141 fortement dopée de type N et séparée, par une région 142 faiblement dopée de type N, d'un doigt d'anode 143 entouré d'une région 144 de type P. Le doigt de source du transistor MOS est relié à une première metallisation principale Ml. Les doigts de grille (non représentés) sont reliés à une metallisation de commande Gl. Le doigt de cathode 140 de la diode est relié à une metallisation M2. Les doigts de drain des cellules de transistor MOS ainsi que les doigts d'anode 143 des cellules de diodes sont reliées à une metallisation M3. Dans l'exemple représenté, la metallisation M3 est du côté de la face arrière et les métallisations Ml, M2 et Gl du côté de la face avant. Les diverses structures illustrées sont susceptibles de nombreuses variantes et modifications, et l'homme de l'art notera que des variantes décrites pour certains modes de réali¬ sation s'appliquent à d'autres modes de réalisation. De même que l'on a illustré en figures 4 à 7 des assemblages de cellules de diode en parallèle, on pourra par répétition d'un motif réaliser des thyristors ou des transistors multicellulaires. Chacune des cellules pourra être réalisée à partir de tranchées parallèles comme en figure 4 ou être à géométrie cylindrique, comme en figures 5 et 6. On pourra bien entendu choisir des cylindres à section non circulaire, par exemple polygonale. De même, de nombreuses associations de composants pourront simplement être réalisées dans un même substrat, séparées ou non par des murs d'isolement. D'autre part, de nombreux modes de réalisation apparaîtront à l'homme de l'art et seront possibles en fonction de l'évolution de la technique, la réalisation de doigts conducteurs ou de plaques formées dans des tranchées n'étant que des exemples d'approches possibles à la réalisation des structures à jonctions verticales décrites. On notera que, comme une plus grande densité de composants est obtenue avec des composants à jonctions verticales selon la présente invention et qu'il peut passer plus de courant par unité de surface de puce qu'avec des composants classiques à jonctions horizontales, plus de chaleur sera générée par unité de surface quand ces composants sont passants (encore que la chute de tension à l'état passant est plus faible grâce à l'optimisation possible de l'épaisseur de la couche de tenue en tension inverse) . Toutefois, cette chaleur pourra être avanta- geusement extraite grâce aux doigts conducteurs traversants. En effet, des doigts métalliques ont une conductivite thermique 2 à 3,5 fois plus élevée que le volume équivalent de silicium. Ces doigts pourront occuper une surface importante et notamment les "doigts" périphériques pourront occuper toute la surface libre entre les cellules élémentaires d'un composant. On notera également que, dans la présente description et les revendications ci-après, le terme jonction est utilisé pour désigner aussi bien un contact entre semiconducteurs de types de conductivite différents qu'un contact Schottky entre un semiconducteur et un matériau de type métal ou alliage métallique. "finger" to designate both the plate-shaped elements of FIG. 4 and the finger-shaped elements of FIGS. 5 and 6. FIG. 8A represents a more detailed sectional view of a structure such as that of Figures 4 to 6. Similarly elements that in Figures 4 to 6 are designated by the same references. References 36 and 37 designate insulating layers. The insulating layer 36 on the upper face of the substrate covers all the regions N and the insulating layer 37 on the lower face of the substrate covers all the regions P. A metallization Ml on the upper face is in contact with all the vias 32 in contact with the P type regions 33 and a metallization of lower face M2 is in contact with all the vias 34 in contact with the N + 35 regions, themselves in contact with portions of the substrate N 31. In the example of the FIG. 8A shows the vias of the upper layer as substantially through vias and the vias of the lower layer as non-traversing vias. However, other options may be taken depending on the manufacturing technologies chosen. FIG. 8B represents the equivalent diagram of the structure of FIG. 8A between the metallizations Ml and M2. According to an advantage of the present invention, the junction surface of all the diode cells in parallel can be much greater than the surface of the chip containing these diode cells, and this all the more that one can use semiconductor wafers thicker than usual. Another advantage of this type of manufacture is that it is possible to produce several components according to the invention on the same wafer, each of these components can easily be surrounded, if this is useful, with insulating walls formed in any chosen way. FIGS. 9A and 9B represent a schematic sectional view and an equivalent diagram of two diodes or diode cells Dl and D2 in series (tandem assembly) formed in a semiconductor substrate 40 of type N. In FIG. 9A, the diode on the left comprises two almost through conductive fingers 41 and 42, both starting from the upper face. The finger 41 is surrounded by a region P 43 and the finger 42 is surrounded by a region N + 44. The right diode comprises a conductive finger 45 starting from the upper face surrounded by a region P 46 and a conductive finger 47 starting from the lower face surrounded by a region N + 48. Insulating layers are produced so that an upper metallization Ml is in contact with the finger 41, an insulated metallization M3 connects the conductive fingers 42 and 45 and a metallization of the lower face M2 is in contact with the conductive finger 47. As shown in partial section view in FIG. 10A and in the form of a diagram in FIG. 10B, by assembling two pairs of diodes such as the diodes D1 and D2 of FIGS. 9A and 9B, and by providing insulating walls, a rectifier bridge can be produced. In FIG. 10A, the left diode is identical to the left diode in FIG. 9A and its elements are designated by the same references. The right diode is also identical to the right diode in FIG. 9A and its elements are also designated by the same references. The essential difference between FIGS. 9A and 10A resides in the positioning of the metallizations. As before, the metallization of the upper face M1 contacts the finger 41 and the metallization of the lower face M2 contacts the finger 47. However, this time, the metallization M3 short-circuiting the conducting fingers 42 and 45 is not enclosed in an insulating layer but is accessible from the upper surface. In addition, the entire structure is surrounded by a wall 49 made of an insulating material. By making two structures identical to that of FIG. 10A, and by connecting for these two structures the metallizations Ml together, the metallizations M2 between them and the metallizations M3 at separate terminals, a rectifier bridge assembly is obtained such as that illustrated in Figure 10B. FIG. 11A and FIG. 11B represent a combination of diodes constituting a bi-directional avalanche diode. This diode is formed in an N-type semiconductor substrate 50. A conductive finger 51 extending from the upper surface is surrounded by a P-type region 52 and a conductive finger. tor 53 starting from the lower surface is surrounded by a P type region 54. A metallization Ml on the upper face is in contact with the finger 51 and a metallization M2 on the lower face is in contact with the finger 53. FIG. 12A is a sectional view and FIG. 12B is a circuit diagram of an assembly of two antiparallel diodes. The two diodes are formed in an N-type substrate 60. The diode on the left comprises a conductive finger 61 surrounded by a region P 62, integral with an upper metallization Ml. A conductive finger 63 surrounded by an N + 64 region is integral with a lower metallization M2. Conversely, the right diode comprises a conductive finger 65 surrounded by an N + 66 type region integral with the upper metallization M1 and a conductive finger 67 surrounded by an N + region 68 integral with the lower metallization M2. The two diodes are separated by an insulating wall 69. In the various figures, the fingers are illustrated as crossing or not. It depends on the embodiments and the manufacturing technologies chosen. In the case of through fingers, their end not connected to a contact is isolated. Figures 13A and 13B show a partial perspective view and a sectional view of an embodiment according to the invention of a bipolar transistor. This bipolar transistor is formed in an N-type substrate 70 and comprises a heavily N-doped emitter region 71 around a central conductive finger 72 extending over all or substantially the entire thickness of the substrate. A base region 73 of type P is disposed around the emitter, between the emitter and a collector region corresponding to the substrate 70. As best shown in FIG. 13B, conductive fingers 74 starting from the underside are surrounded by N + 75 regions and serve as a collector contact. An intermediate metallization M3 on the side of the upper face is secured to conductive fingers 76 making contact with the base region 73. As illustrated in the figure 13A, the conductive fingers 76 are spaced from each other like a grid to allow the base to function properly. By cons, in an embodiment of the type of that of Figures 5 and 6, the fingers 74 may in fact constitute a conductive cylinder completely surrounding the transistor cell shown. FIGS. 14A and 14B illustrate a thyristor structure in perspective and in section respectively. The structure is produced in a semiconductor substrate 80, of type N. In a central region, a conductive finger 81 is surrounded by a heavily doped region of type N 82 corresponding to the thyristor cathode and a P layer 83. These regions can be produced by successively diffusing, from a through or substantially through opening, a P dopant and then an N dopant or else by simultaneously diffusing dopants whose diffusion rates are suitably different. The finger 81 is connected to a metallization of cathode MK. Conductive fingers 84 penetrate the P-type region 83 and constitute trigger contact points secured to a trigger metallization MG. On the side of the lower face, at the periphery of the component, are made conductive fingers 85 surrounded by a P-type region 86 which constitutes the anode of the thyristor and which is connected by the fingers 85 to an anode metallization MA . It will be noted that it is possible, as is conventional in a thyristor, to trigger-cathode short-circuits located by means of conductive fingers 87 partially penetrating only in the substrate between the region N 82 and the region P 84. Layers insulating materials not referenced are intended to separate the various metallizations and to isolate the appropriate zones. The entire structure may be surrounded by an insulating wall. A triac can be achieved by mounting two thyristors of the above type in parallel and in opposition. FIG. 15A is a schematic sectional view of a portion of semiconductor wafer in which a set of cells of MOS transistors according to the present invention. The main faces of the component correspond to the upper and lower faces of a semiconductor wafer, and the vertical dimension, the height of which is designated by e, corresponds to the thickness of the semiconductor wafer. Figures 15B and 15C are two simplified examples of top views of the structure formed in the semiconductor substrate, both corresponding to the sectional view of Figure 15A. An elementary cell according to the present invention comprises a conductive finger 111 extending over the entire thickness of the wafer or over a major part of this thickness. The conductive finger 111 is bordered by a heavily doped N-type region (N +), itself bordered by an intermediate P-type region 113 then by a lightly doped N-type region 114 and a heavily doped N-type region 115 used for resumption of ohmic contact with a conductive finger 116. Like the conductive finger 111, the regions 112, 113, 114 and 115 and the conductive finger 116 extend substantially over the entire thickness of the substrate, and the junctions or limits between these elements are substantially vertical. The conductive finger 111 corresponds to a source metallization, the region 112 to a source zone, the intermediate region 113 to the zone in which a channel can form, the region 114 to a drain zone, the region 115 to a drain contact recovery layer, and the conductive finger 116 to a drain metallization. FIG. 15B is a top view of the present invention in an embodiment in which the conductive fingers are produced in the form of vertical conductive plates extending in trenches formed in a semiconductor substrate. We can see better in FIG. 15B, the embodiment of the gate of the MOS transistor according to the present invention. This grid is produced by means of spaced apart conductive fingers 121 surrounded by an insulating layer 122 extending vertically in the intermediate region 113. When a positive voltage is applied between the gate fingers 121 and the source finger 111, a channel is formed in the vertical region of the intermediate region 113 between two gate fingers, so that the MOS transistor becomes conductive between its source and its drain, and a current indicated by the arrows I is likely to flow horizontally from the drain to the source. An enriched MOS transistor has been described above; in the case of a depletion MOS transistor, the intermediate region 113, at least in the vicinity of the gate insulator, would be lightly N-type doped and the application of a voltage between the gate fingers 121 and the gate finger source 111 would make the MOS transistor non-conductive between its source and its drain. FIG. 15B also shows conductive fingers 123 penetrating over all or part of the thickness of the substrate and making it possible to establish a short circuit between the intermediate box 113 and the source region 112, which constitutes the equivalent of the short circuit established by the source metallization MS of FIG. 3A between the ring N + 25 and the central part of the box P 23. FIG. 15C illustrates in top view another embodiment of a component according to the present invention in which each MOS transistor cell has a closed contour. The central source finger 111 is surrounded by an annular region 112 of the type N +, which is itself surrounded by an annular region inter ¬ médiaire 113 P-type with an annular region 114 of N type, and a annular region 115 heavily doped with N (N + ) type. In FIG. 15C, the structure is shown as completely surrounded by a conductive ring 116. In practice, this ring may be made up of a succession of conductive fingers close to each other. To simplify the representation, the conductive fingers 123 have not been shown in FIG. 15C. The drain, gate and source metallizations have not been shown in FIGS. 15A, 15B and 15C. We will understand, that all the gate fingers 121 are connected to the same metallization, all the source fingers 111 to the same metallization and all the drain fingers 116 to the same metallization. Preferably, as in a conventional component, the drain and source metallizations are produced on two opposite faces of the semiconductor chip. According to an advantage of the invention, the grid metallization can, as desired and also simply, be carried out on the drain side or source side, which simplifies monolithic assemblies of components according to the invention. The production of a component according to the present invention will appear to a person skilled in the art who may use conventional techniques for piercing openings in the form of vias or trenches, for doping from the openings thus formed, then for filling. of these openings by a conductor, for example a metal, for example copper, this filling being preceded or not by the formation of an insulating layer. It will be understood that, although the terms vias or fingers are used in the present description, these terms also cover the structures in the form of trenches such as those of FIG. 15B or the ring-shaped structures such as metallization 116 of Figure 15C. The above description essentially relates to the structure of the MOS transistor and the order of the manufacturing steps can be modified. As indicated above, the present invention applies not only to an MOS transistor but also in general to any MOS component of power or high voltage, for example bipolar insulated gate transistors (IGBT) and other components to voltage control, MOS or Schottky-MOS type, enrichment or depletion. In particular, we can simply switch from the MOS transistor structure of FIG. 15 to an IGBT structure by replacing the heavily doped N-type layer 115 with a heavily doped P-type layer. According to an advantage of the present invention, the channel width per unit of area is much greater than that obtained in a diffused vertical MOS transistor (VDMOS) such as that of FIG. 3, as is the total area of the drain of the the set of cells can be larger than the area of the chip containing these cells. Another advantage of the present invention is that it is possible to produce several components according to the invention in the same semiconductor wafer, each of these components can easily be surrounded by insulating walls formed in any chosen way. Examples of such assemblies will be given in FIGS. 16 and 17. FIG. 16A represents the diagram of an anti-parallel assembly of two IGBT transistors according to the present invention comprising two main terminals T1 and T2 and two control terminals Gl and G2. In the description below, the main terminals of the IGBT transistor will be called source and drain to simplify the analogy with the MOS transistor described above. FIG. 16B represents a schematic embodiment of such an assembly in which the same elements as in FIG. 15A are designated by the same references. The left part of the figure represents an IGBT transistor comprising a source finger 111-1, surrounded by an N + region 112-1, an intermediate region 113-1 crossed by gate fingers not visible in the figure. An N type region 114-1 extends between region 113-1 and a P + type region 132-1 which surrounds a drain finger 116-1. This assembly is separated by an isolation wall 131 from a structure arranged symmetrically with respect to this wall and comprising a drain finger 116-2 surrounded by a P + 132-2 region and separated by a weakly doped region of the type N 114-2 of an intermediate region 113-2 in which is likely to form a channel and in which penetrate gate fingers not shown. Intermediate region 113-2 is in contact with a heavily doped N-type region 112-2 in contact with a source finger 111-2. Although only one cell has been represented, it will be understood that each of the structures is made up of a set of cells, as described above. The source fingers of the cells situated to the left of the isolation wall are integral with an upper metallization T1, as are the drain fingers 116-2 of the cells arranged to the right of the isolation wall. The drain fingers 115-1 of the cells located to the left of the isolation wall are connected to a lower metallization T2 as are the source fingers 111-2 of the cells located to the right of the isolation wall. The connections Gl and G2 are only shown symbolically, which it will be noted that they can, without difficulty, be made on the same face of the component. This structure has, compared to the monolithic structures assembling conventional vertical IGBT transistors, the advantage that the two IGBT transistors are perfectly symmetrical and that the characteristics of these transistors are also perfectly symmetrical. The structures according to the present invention also make it possible to associate MOS components as described above and bipolar components also produced with vertical junctions (orthogonal to the main faces of the substrate). FIG. 17A shows an example of such an association, comprising a MOS transistor, TMOS, and a diode, D, the anode of the diode being connected to the drain of the MOS transistor. This circuit constitutes an element commonly used in practice and difficult to integrate by conventional technologies. FIG. 17B shows an embodiment of such a structure. In FIG. 17B, the left part is strictly identical to the left part in FIG. 16B except that the P type region surrounding the drain region is replaced by an N + type region to constitute a MOS transistor. This MOS transistor comprises a source finger 111, a source region 112, an intermediate region 113, a drain region 114, and a drain finger 116 surrounded by a heavily doped N-type region 115. This assembly is separated by an isolation wall 132 from a diode structure comprising a cathode finger 140 surrounded by a strongly 141 region N-type doped and separated, by a lightly N-type doped region 142, from an anode finger 143 surrounded by a P-type region 144. The source finger of the MOS transistor is connected to a first main metallization Ml . The gate fingers (not shown) are connected to a control metallization Gl. The cathode finger 140 of the diode is connected to a metallization M2. The drain fingers of the MOS transistor cells as well as the anode fingers 143 of the diode cells are connected to a metallization M3. In the example shown, the metallization M3 is on the side of the rear face and the metallizations Ml, M2 and Gl on the side of the front face. The various illustrated structures are likely many variations and modifications, and skilled in the art will appreciate that variations described for certain modes of Réali ¬ tion apply to other embodiments. As illustrated in FIGS. 4 to 7, assemblies of diode cells in parallel, it will be possible, by repeating a pattern, to produce thyristors or multicellular transistors. Each of the cells may be produced from parallel trenches as in FIG. 4 or be of cylindrical geometry, as in FIGS. 5 and 6. It will of course be possible to choose cylinders with a non-circular section, for example polygonal. Likewise, many associations of components can simply be made in the same substrate, separated or not by isolation walls. On the other hand, many embodiments will appear to those skilled in the art and will be possible depending on the evolution of the technique, the production of conductive fingers or plates formed in trenches being only examples. possible approaches to the realization of the structures with vertical junctions described. It will be noted that, as a greater density of components is obtained with components with vertical junctions according to the present invention and that it can pass more current per unit of chip area than with conventional components with horizontal junctions, more heat will be generated per unit area when these components are conducting (although the voltage drop in the conducting state is lower thanks to the possible optimization of the thickness of the reverse voltage withstand layer). However, this heat can advantageously be extracted using the through conductive fingers. Indeed, metal fingers have a thermal conductivity 2 to 3.5 times higher than the equivalent volume of silicon. These fingers can occupy a large surface and in particular the peripheral "fingers" can occupy the entire free surface between the elementary cells of a component. It will also be noted that, in the present description and the claims below, the term junction is used to denote both a contact between semiconductors of different conductivity types and a Schottky contact between a semiconductor and a material of metal or alloy type metallic.

Claims

REVENDICATIONS
1. Composant semiconducteur caractérisé en ce que les jonctions actives s'étendent perpendiculairement à la surface d'une puce semiconductrice sensiblement sur toute l'épaisseur de celle-ci. 1. Semiconductor component characterized in that the active junctions extend perpendicular to the surface of a semiconductor chip substantially over the entire thickness thereof.
2. Composant semiconducteur selon la revendication 1, dans lequel les contacts avec les régions devant être connectées sont pris par des doigts conducteurs traversant sensiblement toute la région avec laquelle on souhaite établir un contact. 2. Semiconductor component according to claim 1, wherein the contacts with the regions to be connected are taken by conductive fingers passing through substantially the entire region with which it is desired to establish contact.
3. Composant semiconducteur selon la revendication 2, dans lequel les doigts conducteurs sont des doigts métalliques. 3. Semiconductor component according to claim 2, wherein the conductive fingers are metallic fingers.
4. Composant semiconducteur selon la revendication 1, de type multicellulaire, dans lequel les jonctions sont constituées de plusieurs cylindres perpendiculaires aux faces principales du substrat. 4. Semiconductor component according to claim 1, of multicellular type, in which the junctions consist of several cylinders perpendicular to the main faces of the substrate.
5. Composant semiconducteur selon la revendication 1, dans lequel les jonctions actives s'étendent selon au moins un cylindre perpendiculaire aux faces principales d'une puce semi- conductrice sensiblement sur toute l'épaisseur de celle-ci, le ou lesdits cylindres ayant, en coupe, une section en forme de courbe fermée ondulée. 5. A semiconductor component according to claim 1, in which the active junctions extend along at least one cylinder perpendicular to the main faces of a semiconductor chip substantially over the entire thickness of the latter, the said cylinder or cylinders having, in section, a section in the form of a wavy closed curve.
6. Composant semiconducteur selon la revendication 5, dans lequel ladite courbe ondulée est une courbe de type courbe de Sierpinski. 6. Semiconductor component according to claim 5, wherein said wavy curve is a Sierpinski curve type curve.
7. Composant semiconducteur selon l'une quelconque des revendications 1 à 6, dans lequel les contacts avec les régions devant être connectées sont pris par des doigts conducteurs perpendiculaires aux faces principales de la puce semi- conductrice et traversant sensiblement toute la région avec laquelle on souhaite établir un contact . 7. Semiconductor component according to any one of claims 1 to 6, in which the contacts with the regions to be connected are made by conductive fingers perpendicular to the main faces of the semiconductor chip and passing through substantially the entire region with which wish to make contact.
8. Composant semiconducteur selon la revendication 7, dans lequel ledit au moins un doigt conducteur solidaire de la couche semiconductrice la plus externe constitue un cylindre ou des portions de cylindre entourant ladite couche semiconductrice la plus externe. 8. Semiconductor component according to claim 7, wherein said at least one conductive finger integral with the outermost semiconductor layer constitutes a cylinder or cylinder portions surrounding said outermost semiconductor layer.
9. Composant semiconducteur selon l'une quelconque des revendications 1 à 8, constituant une diode comprenant un doigt conducteur central (32) s'etendant sur toute l'épaisseur du substrat entouré d'une région d'un premier type de conductivite (33) et d'une région d'un second type de conductivite (31), un contact étant repris à la périphérie de la région du second type de conductivite par au moins un doigt conducteur périphérique, le doigt conducteur central étant relié à une première metallisation s'etendant sur toute une face du substrat, et ledit au moins un doigt conducteur périphérique étant relié à une metallisation sur l'autre face du substrat. 9. Semiconductor component according to any one of claims 1 to 8, constituting a diode comprising a central conductive finger (32) extending over the entire thickness of the substrate surrounded by a region of a first type of conductivity (33 ) and a region of a second type of conductivity (31), a contact being taken up at the periphery of the region of the second type of conductivity by at least one peripheral conductive finger, the central conductive finger being connected to a first metallization extending over an entire face of the substrate, and said at least one peripheral conductive finger being connected to a metallization on the other face of the substrate.
10. Composant semiconducteur selon la revendication 1, constituant une diode comprenant une alternance de régions d'un premier type de conductivite (33) et d'un second type de conduc- tivité (31) s'etendant sur toute l'épaisseur du substrat, les régions d'un premier type étant traversées par des doigts conducteurs (32) reliés à une metallisation s'etendant sur toute une face du substrat, et les régions du second type étant traversées par des doigts conducteurs (34) reliés à une metallisation sur l'autre face du substrat. 10. Semiconductor component according to claim 1, constituting a diode comprising an alternation of regions of a first type of conductivity (33) and of a second type of conductivity (31) extending over the entire thickness of the substrate. , the regions of a first type being crossed by conductive fingers (32) connected to a metallization extending over a whole face of the substrate, and the regions of the second type being crossed by conductive fingers (34) connected to a metallization on the other side of the substrate.
11. Composant semiconducteur selon la revendication 10, formé dans un substrat semiconducteur de type N, dans lequel les doigts conducteurs pénétrant les régions de type N sont entourés de régions (35) fortement dopées de type N. 11. Semiconductor component according to claim 10, formed in an N-type semiconductor substrate, in which the conductive fingers penetrating the N-type regions are surrounded by heavily doped N-type regions (35).
12. Composant semiconducteur selon la revendication 1, constituant un transistor bipolaire comprenant en alternance une région d'un premier type de conductivite (71), une région d'un deuxième type de conductivite (73) , et une région du premier type de conductivite (70), chacune de ces régions s'etendant sur toute l'épaisseur du substrat et étant contactée par au moins un doigt conducteur, chacun de ces doigts conducteurs (72, 76, 74) étant respectivement connecté à une metallisation d'émetteur (Ml), à une metallisation de base (M3) , et à une metallisation de collecteur (M2) . 12. Semiconductor component according to claim 1, constituting a bipolar transistor comprising alternately a region of a first type of conductivity (71), a region of a second type of conductivity (73), and a region of the first type of conductivity. (70), each of these regions extending over the entire thickness of the substrate and being contacted by at least one conductive finger, each of these conductive fingers (72, 76, 74) being respectively connected to an emitter metallization ( Ml), to a base metallization (M3), and to a collector metallization (M2).
13. Composant semiconducteur selon la revendication 1, constituant un thyristor comprenant successivement une première région d'un premier type de conductivite (82), une deuxième région du deuxième type de conductivite (83), une troisième région du premier type de conductivite (80) et une quatrième région du deuxième type de conductivite (86) , chacune de ces régions s'etendant sur toute l'épaisseur du substrat, un doigt conducteur (81) s'etendant dans toute la première région, au moins un doigt conducteur (84) s'etendant dans toute la deuxième région, et au moins un doigt conducteur (85) s'etendant dans toute la deuxième région. 13. Semiconductor component according to claim 1, constituting a thyristor successively comprising a first region of a first type of conductivity (82), a second region of the second type of conductivity (83), a third region of the first type of conductivity (80) and a fourth region of the second type of conductivity (86), each of these regions extending over the entire thickness of the substrate, a conductive finger (81) extending throughout the first region, at least one conductive finger (84) extending throughout the second region, and at least one finger conductor (85) extending throughout the second region.
14. Composant semiconducteur selon la revendication14. Semiconductor component according to claim
13, dans lequel le premier type de conductivite est le type N, et le deuxième type de conductivite est le type P, la première région étant une région de cathode et la quatrième région une région d'anode, et dans lequel des métallisations localisées (87) s'étendent verticalement entre la région de gâchette et la région de cathode pour constituer des courts-circuits gâchette- cathode localisés. 13, in which the first type of conductivity is type N, and the second type of conductivity is type P, the first region being a cathode region and the fourth region being an anode region, and in which localized metallizations ( 87) extend vertically between the trigger region and the cathode region to form localized trigger-cathode short circuits.
15. Composant semiconducteur selon l'une quelconque des revendications 1 à 8, constituant un transistor MOS de puissance comprenant en alternance une région de source d'un premier type de conductivite (112) , une région intermédiaire (113) , et une région de drain du premier type de conductivite (114, 115), chacune de ces régions s'etendant sur toute l'épaisseur du substrat, les régions de source et de drain étant contactées par des doigts ou plaques conducteurs (111, 116) tra¬ versant sensiblement le substrat, des doigts conducteurs isolés et espacés (121) traversant de haut en bas la région intermédiaire (113), la distance horizontale entre les doigts isolés (121) étant telle que la région intermédiaire puisse être inversée quand une tension appropriée est appliquée à ces doigts isolés. 15. Semiconductor component according to any one of claims 1 to 8, constituting a power MOS transistor comprising alternately a source region of a first type of conductivity (112), an intermediate region (113), and a region of drain of the first conductivity type (114, 115), each of these regions extending over the entire thickness of the substrate, the source and drain regions being contacted by fingers or conductive plates (111, 116) tra ¬ slope substantially the substrate, insulated and spaced apart conductive fingers (121) traversing from top to bottom the intermediate region (113), the horizontal distance between the isolated fingers (121) being such that the intermediate region can be reversed when an appropriate voltage is applied to these isolated fingers.
16. Composant semiconducteur selon l'une quelconque des revendications 1 à 8, constituant un transistor IGBT comprenant en alternance une région de source d'un premier type de conductivite (112), une région intermédiaire (113), une région de drain du premier type de conductivite (114) et une région supplémentaire (132) du deuxième type de conductivite, chacune de ces régions s'etendant sur toute l'épaisseur du substrat, la région de source et la région supplémentaire étant contactées par des doigts ou plaques conducteurs (111, 116) traversant sensiblement le substrat, des doigts conducteurs isolés et espacés (121) traversant de haut en bas la région intermédiaire (113) , la distance horizontale entre les doigts isolés (121) étant telle que la région intermédiaire puisse être inversée quand une tension appropriée est appliquée à ces doigts isolés. 16. Semiconductor component according to any one of claims 1 to 8, constituting an IGBT transistor alternately comprising a source region of a first type of conductivity (112), an intermediate region (113), a drain region of the first conductivity type (114) and a additional region (132) of the second type of conductivity, each of these regions extending over the entire thickness of the substrate, the source region and the additional region being contacted by fingers or conductive plates (111, 116) substantially passing through the substrate, insulated and spaced apart conductive fingers (121) traversing from top to bottom the intermediate region (113), the horizontal distance between the insulated fingers (121) being such that the intermediate region can be reversed when an appropriate voltage is applied to these isolated fingers.
17. Composant semiconducteur selon la revendication 15 ou 16, constituant un transistor MOS de puissance ou IGBT dans lequel chacun des doigts conducteurs est respectivement connecté à une metallisation de source (Ml), à une metallisation de grille (M3) , et à une metallisation de drain (M2) . 17. Semiconductor component according to claim 15 or 16, constituting a power MOS transistor or IGBT in which each of the conductive fingers is respectively connected to a source metallization (Ml), to a gate metallization (M3), and to a metallization drain (M2).
18. Composant MOS de puissance selon la revendication 15 ou 16, constituant un transistor MOS de puissance ou IGBT dans lequel des métallisations localisées (123) s'étendent verticalement entre la région de source et la région intermé- diaire pour constituer des courts-circuits localisés. 18. Power MOS component according to claim 15 or 16, constituting a power MOS transistor or IGBT in which localized metallizations (123) extend vertically between the source region and the intermediate region to constitute short circuits. located.
19. Composant semiconducteur selon la revendication 15 ou 16, constituant un transistor MOS de puissance ou IGBT dans lequel les doigts conducteurs isolés et espacés (121) sont réalisés à partir de doigts conducteurs traversant toute l'épaisseur de la puce dont les parois sont oxydées et qui sont remplis de silicium polycristallin dopé. 19. Semiconductor component according to claim 15 or 16, constituting a power MOS transistor or IGBT in which the isolated and spaced conductive fingers (121) are made from conductive fingers passing through the entire thickness of the chip whose walls are oxidized and which are filled with doped polycrystalline silicon.
PCT/FR2004/050642 2003-12-05 2004-12-02 Small-surfaced active semiconductor component WO2005057660A1 (en)

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FR2895569A1 (en) * 2005-12-26 2007-06-29 St Microelectronics Sa Vertical power MOS component e.g. insulated gate bipolar transistor, has P-type doped regions extending vertically across silicon plate and bordering conduction zone between gate and drain fingers from ring in direction of drain finger
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EP3029735A1 (en) * 2014-12-04 2016-06-08 Nxp B.V. Semiconductor device
CN109585562A (en) * 2017-09-29 2019-04-05 恩智浦美国有限公司 Bidirectional power MOSFET structure with cathode short-circuit structure
CN109585562B (en) * 2017-09-29 2023-09-19 恩智浦美国有限公司 Bidirectional power MOSFET structure with cathode short circuit structure

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