WO2005052798A1 - Memoire a entrelacement - Google Patents

Memoire a entrelacement Download PDF

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Publication number
WO2005052798A1
WO2005052798A1 PCT/CA2004/002048 CA2004002048W WO2005052798A1 WO 2005052798 A1 WO2005052798 A1 WO 2005052798A1 CA 2004002048 W CA2004002048 W CA 2004002048W WO 2005052798 A1 WO2005052798 A1 WO 2005052798A1
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Prior art keywords
memory
interleaver
address
sequence
sample
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PCT/CA2004/002048
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English (en)
Inventor
Sean G. Gibb
Peter J. W. Graumann
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Cygnus Communications Canada Co.
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Priority claimed from CA 2451167 external-priority patent/CA2451167A1/fr
Application filed by Cygnus Communications Canada Co. filed Critical Cygnus Communications Canada Co.
Publication of WO2005052798A1 publication Critical patent/WO2005052798A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
    • G06F17/141—Discrete Fourier transforms
    • G06F17/142—Fast Fourier transforms, e.g. using a Cooley-Tukey type algorithm

Definitions

  • the present invention generally relates to interleaving memories. More particularly, the present invention relates to interleaving memories for use with transform processors.
  • the discrete Fourier transform (DFT) implementation of the FFT is an important block in many digital signal processing applications, including those which perform spectral analysis or correlation analysis.
  • the purpose of the DFT is to compute the sequence ⁇ x(k) ⁇ , having N complex-valued numbers, given another sequence also of length N, where
  • FFT processors performing the above process are commonly implemented as dedicated processors in an integrated circuit. Many previous approaches have improved the throughput of FFT processors while balancing latency against the area requirements through the use of a pipeline processor- based architecture. In a pipeline processor architecture, the primary concern from the designer's perspective is increasing throughput and decreasing latency while attempting to also minimize the area requirements of the processor architecture when the design is implemented in a manufactured integrated circuit.
  • a common pipeline FFT architecture achieves these aims by implementing one length-2 DFT (also called a radix-2 butterfly) for each stage in the DFT recombination calculation. It is also possible to implement less than or more than one butterfly per recombination stage. However, in a real-time digital system, it is sufficient to match the computing speed of the FFT processor with the input data rate. Thus, if the data acquisition
  • FFT implementations that accept in-order input data are most suitable for systems where data is arriving at the FFT one sample at a time. This includes systems such as wired and wireless data transmissions systems.
  • Out-of-order input handling is most appropriate when the input data is buffered and can be pulled from the buffer in any order, such as in an image analysis system. All of the discussed architectures are based on the Decimation-in-Frequency (DIF) decomposition of the DFT.
  • DIF Decimation-in-Frequency
  • Input and output data is complex valued as are all arithmetic operations. For the radix-2 designs, a constraint that N is a power of 2 applies, and for the radix-4 designs, a constraint that N is a power of 4 applies.
  • FIG. 1 illustrates a conventional Radix-2 Multi-path Delay Commutator ("R2MDC") pipeline FFT processor.
  • R2MDC Radix-2 Multi-path Delay Commutator
  • the R2MDC approach breaks the input sequence into two parallel data streams.
  • a commutator 102 receives the data stream as input and delays half of the data stream with memory 104. The delayed data is then processed with the second half of the data stream in a radix-2 butterfly unit 106.
  • the processor of Figure 1 implements a 16-point R2MDC pipeline FFT. In terms of efficiency of design, the multipliers and adders in the R2MDC architecture are 50% utilized.
  • the R2DMC architecture requires 3/2 N-2 delay registers.
  • a Radix-4 Multi-path Delay Commutator (“R4MDC”) pipeline FFT is a radix-4 version of the R2MDC, where the input sequence is broken into four parallel data streams.
  • FIG. 2 An exemplary 256-point R4MDC pipeline implementation is shown in Figure 2.
  • the FFT processor of Figure 2 is composed of butterfly modules, such as butterfly module 110.
  • Butterfly module 110 includes commutator 112 with an associated memory 114, butterfly unit 116 and an associated memory 118.
  • the commutator 112 orders samples and stores them in memory 114. When memory 114 is sufficiently full, three samples are provided from memory 114 along with one sample from commutator 112 to the radix-4 butterfly unit 116.
  • a standard radix four butterfly operation is performed on the samples, and the results are provided to a subsequent commutator, after some of them have been buffered in memory 118.
  • the use of memories 114 and 118 ensure in order delivery of the samples between butterfly units.
  • a Radix-2 Single-path Delay Feedback (“R2SDF”) pipeline FFT design uses the memory registers more efficiently than the R2MDC implementation by storing the butterfly output in feedback shift registers. In terms of efficiency, R2SDF designs achieve 50% utilization of multipliers and adders and require N-1 delay registers , which are fully utilized.
  • Figure 3 shows the basic architecture of a prior art R2SDF for a 16-bit FFT.
  • a butterfly module is composed of the radix-2 butterfly unit, such as butterfly unit 120, and its associated feedback memory 122.
  • the size of the memory 122a-122d in a butterfly module varies with the position of the module in the series.
  • Butterfly unit 120 receives an input series of 16 samples, and buffers the first 8 samples in feedback memory 122a. Starting with the ninth sample in the series, butterfly unit 120 serially pulls the stored samples from feedback memory 122a and performs butterfly operations on the pair-wise samples. The in order output is provided to the next butterfly module by storing out of order outputs in the feedback memory 122a until they can be provided in order.
  • a Radix-4 Single-path Delay Feedback (“R4SDF”) pipeline FFT is a radix-4 version of the R2SDF design.
  • FIG. 4 A 256-point R4SDF pipeline example from the prior art is shown in Figure 4.
  • the structure of the processor of Figure 4 is similar to that of Figure 3, with butterfly modules being composed of a radix-4 butterfly unit, such as BF4 124, and an associated feedback memory 126.
  • the size of feedback memory 126 decreases from 126a- 126d in accordance with the amount of separation required between samples.
  • the butterfly modules of Figure 4 function in the same fashion as those of Figure 3, with additional samples being stored in feedback memory 126 in each cycle.
  • a Radix-4 Single-path Delay Commutator uses a modified radix-4 algorithm to achieve 75% utilization of multipliers, and has a memory requirement of 2N-2.
  • a prior art 256-point R4SDC pipeline FFT is shown in Figure 5.
  • Figure 5 has single input single output butterfly modules, such as butterfly module 127.
  • butterfly module 127 a single input is provided to commutator 128 which stores and reorders samples using an internal memory.
  • Commutator 128 provides the samples four at a time to radix four butterfly unit 129.
  • the output of butterfly unit 129 is serially provided to the next butterfly module.
  • R2 2 SDF Single-path Delay Feedback
  • Butterfly modules are composed of butterfly units such as BF21 130 and an associated feedback memory such as memory 131.
  • Butterfly unit 130 receives a series of input samples and buffers the first set of samples in memory 131, then performs pairwise butterfly operations using stored samples and the incoming series.
  • the operation of this processor is functionally similar to that of the processor of Figure 4 with the differences noted above.
  • an interleaver memory for receiving an input sequence of samples and for providing as an output the samples of the input sequence in a permuted order.
  • the interleaver memory comprising a plurality of memory elements and an interleaver controller. Each memory element in the plurality stores a sample from the sequence.
  • the interleaver controller receives a sample from the input sequence, determines a storage address associated with a memory element, reads out, as the memory interleaver output, the contents of the memory element in the plurality associated with the storage address, and transfers the received sample to the memory element in the plurality associated with the storage address for storage.
  • the input sequence has n samples
  • the plurality of memory elements has n/2 memory elements, which are preferably dual ported to allow the interleaver controller to read out the contents of a memory element and transfer the received sample to the memory element for storage simultaneously.
  • the interleaver controller includes an address generator for determining the storage address in accordance with the permuted order, as defined by x ,0 ⁇ xmod2 m ⁇ 2 m -' 2" ⁇ m- ⁇ ⁇ ⁇ m- ⁇ ⁇ « ⁇ J m ⁇ m
  • x is the position of the sample in + /(; mod2 m -') ,2 m - ⁇ mod2 m ⁇ 2" V the input sequence
  • 2 m is the number of samples in the input sequence and
  • the address generator includes a complete compressing permuter, having a compressing permuter and a multiplexer.
  • the compressing permuter determines a storage address candidate for the sample in the input sequence in accordance with the equation x + t " (xmod2 m 1 ), where x is the position of the sample in the input sequence, 2 m is
  • the multiplexer determines the storage address by selecting between the storage address candidate determined by the compressing permuter and a storage address candidate determined in accordance with x. In a presently preferred embodiment, the multiplexer switches between the storage address determined in accordance with x for the first 2 m"1 samples in the input sequence, and the storage address determined by the compressing permuter for the second 2 "1 samples in the input sequence.
  • the compressing permuter includes a bit shifter for determining the storage address by right shifting the binary value of x until the least significant bit is removed. In another embodiment, there are m bit shifters.
  • the interleaving memory receives a plurality of input sequences and the address generator includes a complete sequence permuter for offsetting the storage address determined by the complete compressing permuter in accordance with the number of input sequences previously received.
  • the complete sequence permuter optionally includes plurality of sequence permuters for offsetting the storage address by applying a number of predetermined transition patterns.
  • the interleaver controller optionally includes both an input multiplexer for receiving a sample from the input sequence, and for providing the received sample to memory element associated with the storage address determined by the address generator and an output multiplexer for reading out the contents of the memory element associated with the storage address determined by the address generator.
  • a method of permuting an input sequence of samples to obtain an output sequence of samples.
  • the method comprises the steps of receiving and storing a predetermined number of samples in addressable memory elements, optionally n/2 samples, determining the address of the memory element storing the first sample in the output sequence, reading out the contents of the memory element having the determined address, receiving and storing a further sample in the memory element having the determined address and determining the address of the memory element storing the next sample in the output sequence.
  • the steps of reading out, receiving and storing, and determining the address of the memory element storing the next sample are repeated until all the samples in the output sequence have been read out.
  • the steps of determining the address of the memory element storing the first sample and determining the address of the memory element storing the next sample include determining the addresses
  • Figure 1 is a block diagram illustrating a radix-2 multipath delay commutator pipelined FFT processor of the prior art
  • Figure 2 is a block diagram illustrating a radix-4 multipath delay commutator pipelined FFT processor of the prior art
  • Figure 3 is a block diagram illustrating a radix-2 single path delay feedback pipelined FFT processor of the prior art
  • Figure 4 is a block diagram illustrating a radix-4 single path delay feedback pipelined FFT processor of the prior art
  • Figure 5 is a block diagram illustrating a radix-4 single path delay commutator pipelined FFT processor of the prior art
  • Figure 6 is a block diagram illustrating a radix-2 2 single path delay feedback pipelined FFT processor of the prior art
  • Figure 8 is a flow graph of a decim
  • Figure 14 is a signal diagram showing the use of each hardware component in a general purpose butterfly module of the present invention
  • Figure 15 is a signal diagram showing the use of each hardware component in an optimized butterfly module of the present invention
  • Figure 16 is a flow graph for a 16 point R2SDP FFT of the present invention
  • Figure 17 is a memory timing diagram for the l 2x8 memory interleaver of the present invention
  • Figure 18 is a block diagram of a memory address generator for use in an interleaver of the present invention
  • Figure 19 is a block diagram illustrating a compressing permuter for use in an interleaver of the present invention
  • Figure 20 is a block diagram illustrating a sequence permuter for use in an interleaver of the present invention
  • Figure 21 is a block diagram illustrating an exemplary interleaver of the present invention
  • Figure 22 is a flow chart illustrating an exemplary method of interleaving according to the present invention.
  • the present invention provides an interleaving memory architecture to allow for a reduction in implementation area and latency times.
  • the FFT processor of the described herein uses an interleaving memory structure to receive samples out of order, and to permute them so that they are provided to the butterfly unit in the required order. This reduces the memory requirement for the butterfly unit.
  • the interleaver of the present invention is preferably used to connect two butterfly units, so that it recieves out of order samples from one unit and provides in order samples to the other.
  • the first butterfly unit receives a series of input samples organized as pairs, and performs a butterfly operation on each pair, providing the output to the interleaver.
  • the second butterfly unit serially recieves pairs of samples from the interleaver, performs a butterfly operation on the pairs of samples, and provides as an output, a series of samples corresponding to the FFT of the series of input samples.
  • the present invention provides an FFT processor having a plurality of serially connected butterfly modules. Each butterfly module receives the output of the previous module, with the first module receiving the input series of samples. The final butterfly module provides its output as a series of samples corresponding to an FFT of the series of input samples. At least one of the butterfly modules in the plurality includes an interleaving memory which receives samples out of order, and provides them to the associated butterfly unit in the required order.
  • the present invention can best be understood through a cursory examination of the data flows of an FFT and understanding the implications of these data flows in processor architecture.
  • each butterfly is multiplied by twiddle factor W k .
  • W k the lower half of each butterfly is multiplied by twiddle factor W k .
  • stage 3 the final stage, only W 0 is applied as a twiddle factor.
  • stage 2 either W 0 or W 4 is applied, and in stage 1 one of W 0 , W 2 , W 4 and W 6 is applied.
  • Both input values are also provided to adder 138, after input b is sign inverted, and the output of adder 138 is provided to multiplier 140, which multiplies the output by a twiddle factor W k .
  • the present invention provides modified butterfly units based upon optimizations related to the twiddle factor values, W k . These optimizations can reduce the physical implementation of the circuit embodying this form in the last stages of the FFT.
  • a functional block diagram of the implementation of a DIF FFT processor of the present invention is shown in Figure 9. As with previous FFT processors, the FFT processor of Figure 9 is implemented as a series of stages, each stage corresponding to a butterfly module.
  • the final stage of the processor is provided by butterfly module 142, the penultimate stage by butterfly module 144 and the third last stage by butterfly module 146.
  • the butterfly module 146 is optionally preceded by a plurality of butterfly modules 148, the number selected in accordance with the length of the FFT that is to be computed.
  • the initial butterfly unit 150 is preceded by the source 152. It is assumed that the source provides the input series of samples in the order required by BF2n 150.
  • two basic units are employed: butterfly units 154, 158, 162 and 166 respectively, and interleaver memories 156, 160, 164, and 168.
  • An interleaver memory is also referred to as a permuter, as it has a single input and the interleaving of a single channel is functionally equivalent to the permutation of the channel contents. Due to the use of permuters, the architecture of Figure 9 is referred to herein as a Radix-2 Single-path Delay Permuter ("R2SDP") design.
  • R2SDP Radix-2 Single-path Delay Permuter
  • the system of Figure 9 provides three modified butterfly modules 142, 144 and 146, connected in series. Each of the modified butterfly modules includes an interleaving memory for receiving the output of the previous stage and for permuting the received output into the order required for the associated modified butterfly unit.
  • three modified butterfly units BF2
  • These three modified butterfly modules are optionally preceded by a series of general butterfly modules 148 and a butterfly unit 150 that receives the input sequence.
  • preceding the modified butterfly modules by other butterfly modules allows for longer length FFTs to be computed.
  • Interleaver memory units 156, 160, 164 and 168 are also included in the butterfly modules 141, 144, 146 and 148 respectively.
  • the interleaver memory units are named using the nomenclature l ran where r is the radix of the interleaver (in this example, 2) and n is the number of values interleaved in a single operation. Note that n may take a value between 2 in the first stage's interleaver and N in the last stage's interleaver. The actual memory requirements for the memory interleaver stage is n/2. Larger FFTs simply have additional BF2n butterflies and memory interleaver units (each requiring twice as much storage as the previous interleaver). For the purpose of this disclosure, the data acquisition rate is assumed to be one sample per cycle.
  • the complex inputs are of the form r m (k) + P m (k) > where the sample k is in the interval 0 ⁇ k ⁇ N, and are provided to the butterfly unit serially at a rate of one sample per cycle.
  • the samples r m (i) + ji m (i) and r m + + fi m (' + are separated by one clock cycle.
  • the interleaver memory 156 provides them to butterfly unit 154 in adjacent time slots.
  • butterfly unit 154 requires four registers (two registers per input, allowing storage of the real and imaginary components of a sample) and two adder units.
  • An exemplary implementation of butterfly unit 154 is provided in Figure 10. The description of Figure 10 is best understood in combination with the signal timing diagram of Figure 11 which is also used to illustrated the utilization of the hardware components of the embodiment of Figure 10.
  • registers R0 170 and R1 174 receive the real and imaginary components of the i th sample respectively.
  • registers R2 172 and R4 176 receive the real and imaginary components of the i +1 sample respectively.
  • adder A0 178 sums the contents of register R0 170 and the real component of the i th +1 sample while adder A1 180 sums the contents of register R1 174 and the imaginary component of the i th +1 sample.
  • adder A0 178 takes the difference between the contents of registers R0 170 and R2 172
  • Adder A1 180 takes the difference between the contents of registers R1 174 and R3 176.
  • all registers 170, 172, 174 and 176 are emptied, and the i th +2 sample arrives for storage in registers R0 170 and R1 174.
  • the butterfly operation preferably provides the output of the butterfly operation on the two samples in 2 clock cycles to maintain timing and data flow.
  • butterfly module 144 can also have a modified butterfly unit
  • FIG. 12 illustrates an exemplary embodiment of the modified butterfly BF2 N 158.
  • BF2n 158 operates in two modes, one for each of the coefficients. In the first mode, the circuit behaves exactly as BF2
  • BF2n 158 has the same hardware requirements and utilization as in the multiplierless radix-2 butterfly (four registers and two adder units). However, to permit the real-imaginary component swapping required, additional multiplexers are provided on the four adder inputs in order to steer signals to perform the real-imaginary swap when the coefficient -j is applied.
  • a signal diagram in Figure 13 shows the signal characteristics of the R2SDP BF2 butterfly with multiplication by both coefficients.
  • the operation of the butterfly unit of Figure 12 is best illustrated in conjunction with the timing diagram of Figure 13.
  • the butterfly receives the real and imaginary components of the i th sample and stores them respectively in registers RO 182 and R1 186.
  • registers R2 184 and R3 188 receive the real and imaginary components of the i ⁇ +l sample.
  • adder A0 190 sums the contents of R0 182 and the real component of the i th +1 sample
  • adder A1 192 sums the contents of R1 186 with the imaginary component of the i ⁇ +l sample.
  • Adder A0 190 takes the difference between the contents of R0 182 and R2 184
  • Adder A1 192 takes the difference between the contents of R1 186 and R3 188.
  • Adder A0 190 provides as its output the sum of the contents of register R0 182 and the real component of the i th +3 input, while adder A1 192 provides the sum of the contents of register R1 186 and the imaginary component of the i t +3 input.
  • the butterfly operation is achieved without the use of a dedicated multiplier through the use of sign and component inversion.
  • the contents of registers R0 182, R1 186, R2 184 and R3 188 are emptied to receive the next pairwise samples.
  • the multiplexer control can then by handled by a simple modulus-N/2 counter.
  • the butterfly unit of the present invention is preferably preceded by an interleaver that groups data samples together so that all samples requiring a particular twiddle factor are provided to the butterfly unit in a continuous block.
  • BF2 4 166 is a general purpose butterfly unit.
  • This optionally implemented butterfly unit is used in the FFT processor of Figure 9, in conjunction with properly sized interleavers, such as interleaver 168 to form the general purpose butterfly module 148, which is added to the FFT processor illustrated in Figure 9 to allow for processing larger FFTs.
  • the same general butterfly unit is implemented as BF2 7 150, as described in Figure 8, which receives the input sequence of samples from a source 152.
  • BF2n 150 performs a single complex multiplication during each operation.
  • a complex multiplication is comprised of four real multiplications and two real additions.
  • registers R0 and R1 receive the real and imaginary components of the i th input respectively.
  • adder A0 sums the contents of R0 and the real component of the i ,h +1 input
  • A1 sums the contents of R1 and the imaginary component of the i ⁇ +l input
  • A2 computes the difference between the contents of R0 and the real component of the i th +1 input.
  • Multiplier M0 computes the product of the output of A2 and C(i/2), while M1 computes the product of the output of A2 and S(i/2).
  • RO receives the imaginary component of the i th +2 input
  • R2 receives the output of MO
  • R3 receives the output of M1.
  • the real component of the output is A0
  • the imaginary component of the output is A1.
  • adder A0 takes the difference between the contents of R2 and
  • A1 sums the contents of R3 and MO
  • A2 takes the difference between the contents of R1 and RO.
  • MO and M1 take the same products that they did before, but with the new A2 contents.
  • RO and R1 receive the real and imaginary components of the i ,h +2 sample.
  • the real and imaginary outputs of the butterfly unit are A0 and A1 respectively.
  • adder A0 sums the contents of register RO and the real component of the i th +3 input
  • A1 sums the contents of register R1 and the imaginary component of the i th +3 input
  • A2 takes the difference between the contents of register RO and the real component of the i th +3 input.
  • Multiplier MO computes the product of the contents of A2 and C(i/2+1 ) and M1 computes the product of the contents of A2 and S(i/2+1 ).
  • Register RO receives the imaginary component of the i th +3 input, R2 receives the result of multiplier MO, and R3 receives the output of M1.
  • the real and imaginary components of the output signal are A0 and A1 respectively.
  • the two multiplierless coefficients as in the BF2 M 158 butterfly, are present.
  • multiplication by the two additional complex coefficients can be implemented using an optimized single constant multiplier and a subtractor, rather than the two multipliers and adder-subtractor for the complex multiplication as in BF2/1 150.
  • An implementation utilizing a single constant multiplier and a subtractor provides a simpler implementation with a reduced area.
  • the signal diagram of Figure 15 illustrates the operational requirements of a circuit required to implement BF2 m 162.
  • One skilled in the art will appreciate that such a circuit can be implemented without undue experimentation. There are four different states, or operational modes, shown in Figure 15, one for each of the four coefficient multiplications that this butterfly must perform.
  • the coefficients are preferably ordered in a bit-reversed fashion because the input sequence will be coming into this stage in bit-reversed order.
  • these modes are clustered such that the butterfly unit will perform N/4 operations before switching to the next coefficient multiplication mode. This clustering can be achieved by the proper interleaving of the samples in ⁇ m 164.
  • registers R0 and R1 receive the real and imaginary components of the i" 1 sample.
  • adder A0 sums the contents of R0 with the real component of the i th +1 input sample
  • A1 sums the contents of R1 and the imaginary component of the i th +1 input sample.
  • Registers R2 and R3 receive the real and imaginary components of the i th +1 sample respectively.
  • the real and imaginary components of the output are A0 and A1 respectively.
  • A0 takes the difference between the contents of R0 and R2
  • A1 takes the difference between R1 and R3.
  • R0 and R1 receive the real and imaginary components of the i th +2 input sample respectively.
  • adder A0 sums the contents of R0 with the real component of the i th +3 input sample
  • A1 sums the contents of R1 and the imaginary component of the i th +3 input sample.
  • Registers R2 and R3 receive the real and imaginary components of the i h +3 sample respectively.
  • AO takes the difference between the contents of R1 and R3, while A1 takes the difference between R2 and RO.
  • RO and R1 receive the real and imaginary components of the i th +4 input sample respectively.
  • adder AO sums the contents of RO with the real component of the i th +5 input sample
  • A1 sums the contents of R1 and the imaginary component of the i th +5 input sample
  • A2 takes the difference between contents of R0 with the real component of the i th +5 input sample.
  • Multiplier M0 multiplies the constant value by the contents of A2.
  • Register R0 receives the real component of the i th +5 input sample
  • R2 receives the output of M0.
  • Adder A0 sums the contents of R2 and M0
  • A1 takes the difference between the contents of M0 and R2
  • A2 takes the difference between R1 and R0.
  • Multiplier M0 multiplies the constant value by the contents of A2.
  • R0 and R1 receive the real and imaginary components of the i m +6 sample.
  • the fourth operation mode has W k j , and corresponds to the eighth
  • adder A0 sums the contents of R0 with the real component of the i ,h +7 input sample
  • A1 sums the contents of R1 and the imaginary component of the i th +7 input sample
  • A2 takes the difference between the real component
  • Multiplier MO multiplies the constant value by the contents of A2.
  • Register RO receives the real component of the ith+7 input sample, and R2 receives the output of MO.
  • Adder AO takes the difference of the contents of R2 and MO
  • A1 sums the contents of MO and R2
  • A2 takes the difference between RO and R1.
  • Multiplier MO multiplies the constant value by the contents of A2.
  • the architectures of the above described modified butterflies allow for an implementation in a reduced area as there has been a reduction in the number of components required. Furthermore, the reduction in the component count can be used to decrease the power consumption of the FFT processor in operation.
  • the coefficient clustering in an out-of-order input FFT reduces the switching requirements of the block, resulting in reduced power consumption for the FFT over in-order architectures.
  • the clustering is achieved by selection of an interleaver that provides samples to the butterfly unit in such an order that all pairs of samples requiring the same coefficient are provided as contiguous groups.
  • the interleaver architecture described in the following part was developed by considering the operation of the butterfly units, which accept a single complex input each clock cycle and generate a single complex output each clock cycle.
  • the output data for one stage is passed into a memory interleaver block, such as interleavers 156, 160 and 164, as shown in Figure 9, and after the appropriate memory storage period, is then removed and used by the next butterfly stage to perform the butterfly operation required.
  • the input to the FFT processor is assumed to come in bit-reversed form, so for instance the signal x(0) will arrive first, followed by the signal x(8).
  • Figure 16 shows the data flow of a 16-point FFT with signal timing information for an R2SDP
  • each signal takes the general form x s (t) where s is the signal's stage and t is the zero-based arrival time for that signal in its stage.
  • signals 1 cycle apart such as x 0 (0) and x 0 (1), are combined in a butterfly to produce two results.
  • Stage 1 signals 2 cycles apart are combined and Stage 2 signals that are separated by 4 clock cycles are combined. This pattern of doubling the signal separation continues in the FFT until the final butterfly stage is reached, at which point a delay of N/2 cycles is required in order to perform the final butterfly.
  • N/2 cycles is required in order to perform the final butterfly.
  • M registers or RAM entries are required to generate the delay.
  • the I 2X 2 interleaver 160 would be an l 2x8 memory interleaver block.
  • One objective of the interleaver of the present invention is to avoid both large numbers of storage elements and complex memory addressing systems used to ensure that a storage element is not re-used until its contents have been read out.
  • the interleaver presented below reduces the number of required storage elements, or memory locations, to Yz the size of the data sequence length. Thus, 8 samples can be interleaved in the using only 4 memory locations (assuming that each sample is sized to fit in one memory location).
  • FIG. 17 A signal timing diagram for an interleaver, such as interleaver 160, is shown in Figure 17.
  • the l 2x8 memory interleaver 160 allows signals four clock cycles apart to be butterflied together by storing the first four signals that enter the interleaver and then by interleaving these stored signals with the next four signals that enter the block.
  • a general interleaver block the first n/2 signals are stored and then are interleaved with the next n/2 signals.
  • x n - ⁇ is permuted to provide the interleaver output pattern of Xo, Xn/ 2 , X ⁇ , Xn/ 2 + ⁇ .--- . Xn/2-1, x n - ⁇ .
  • the memory of l 2x8 160 is initially loaded in sequential order, though this is not necessary. Once the interleaver has been filled, data is read out of the interleaver and input data is directed to the same place as the most recently read data to avoid overwriting valid data.
  • I 2x8 160 can be used to interleave eight symbols in four memory locations.
  • each cycle a new input is passed into the interleaver and once the fifth signal arrives, each cycle thereafter a new output is also generated by the interleaver.
  • the input sequence x 0 (0), x 0 (1 ), Xo(2), Xo(3), x 0 (4), Xo(5), x 0 (6), x 0 (7) is interleaved to produce the output sequence x 0 (0), x 0 (4), x 0 (1 ), Xo(5), Xo(2), Xo(6), x 0 (3), x 0 (7).
  • the first four symbols are placed into memory locations determined by the sequential addresses 0, 1 , 2, and 3 in the first four clock cycles.
  • the memory is a dual port register file, having unique read and write ports.
  • the remaining three inputs, x 0 (5) through x 0 (7), are placed in memory locations as those locations become available.
  • the final input address pattern for the eight incoming signals is 0, 1 , 2, 3, 0, 1, 0, 0. Assuming that the input data is continuous and without pause, the memory will not be completely available by the time the next eight input symbols begin to arrive.
  • the first symbol in the second set of input data, X ⁇ (0) will need to go into the available memory location which is address 2.
  • the remaining three entries for the first half of the input data will go into the available memory locations 1 , 3, and 0.
  • the remaining four incoming data values, x ⁇ 4) through X ⁇ (7), will follow a similar pattern to the second half of the previous eight input values.
  • the resulting input address pattern for the second eight incoming values is 2, 1 , 3, 0, 2, 2, 1 , 2.
  • the third set of eight incoming values has a new order, the overall pattern is periodic and repeats every log 2 N input patterns.
  • a sequence of n input data is broken into two distinct sequences in the interleaver.
  • the first n/2 input data values fill the available n/2 memory locations from the previous operation and the second n/2 input values fill the available n/2 memory locations from the current operation.
  • These two sets of n/2 input data are interleaved together performing a single interleave operation that produces one output symbol per cycle to match the data rate of the incoming data stream.
  • the addresses of the second half of the input data relative to the addresses filled in the first half of the operation, follow a very distinct pattern. In order to observe this result, consider the first memory interleaving operation described above (i.e. 0, 1 , 2, 3, 0, 0, 1 , 0).
  • the addresses of the second half of the input data can also be described in terms of relationship position to previous inputs.
  • the signals x 0 (4), Xo(5), Xo(7) go into the memory position of the original input signal Xo(0).
  • the signal x 0 (6) goes into the memory position of the original input signal Xo(1 ).
  • the same behavior is observed in the second set, and all remaining sets, of input data.
  • the first four inputs of the second input data set, x ⁇ O) through Xi(3) can be compared with the first four inputs of the first input data set, x 0 (0) through Xo(3).
  • Signal x ⁇ O) follows signal x 0 (2);
  • signal x ⁇ 1) follows signal Xo(1) and so forth.
  • the l 2x8 memory interleaver can be extended to length M patterns for an I 2XM memory interleaver.
  • the addresses used by the interleaver are described by the sequence 0, 0, 1 , 0, 2, 1 , 3, 0, ... which appears in Sloane's Encyclopedia of Integer Sequences as sequence A025480. This sequence is described by the
  • x is the position of the sample in the input sequence.
  • g(x) performs the bitwise-and of an input value and its sign inverse. The result of g(x) is the greatest odd divisor of x, which in turn is the largest value that x is divided evenly by, the division resulting in the smallest odd numbered divisor.
  • g(x) provides as a result, the power of 2 that can be used to divide x by to remove all trailing zeros.
  • the following complete compressing permuter equation describes the procedure used to generate the addresses for the first interleaver operation: m '
  • the output of the complete compressing permuter 200 is fed directly into the first sequence permuter 198a.
  • the addition of the term 2 m [ /2 m J to the compressing permuter allows the data to be set up such that the sequence permuters will produce the correct results across all input signal values x.
  • Complete compressing permuter 200 uses multiplexer 196 to switch between the two states, and is described in more detail below.
  • counter signal ctr is used to control multiplexers 196 and 202, and is used to provide the input value x to the equation p m (x).
  • Multiplexer 196 differentiates the two cases in the equation c m (x) which describes the behavior of complete compressing permuter 200.
  • the selection of input bits, ctr[m-2:0], into the complete compressing permuter 200 removes the complexity of the
  • Each successive shifter uses an additional multiplexer, with shifter 206 having none, and shifter 212 having m-1 multiplexers.
  • the first multiplexer in each shifter receives 0 and inp[n-1] as inputs to its 1 and 0 ports respectively.
  • the output of each multiplexer is fed to the next multiplexer's 1 port, while the next successive lower inp[x] value is provided to the 0 port.
  • Each multiplexer is controlled by inp[x], with x decreasing from the first multiplexer to the last, with the last multiplexer controlled by inp[0].
  • the implementation of the sequence permuter 198 is also based upon the same sequence generator equation f(x) with the addition of a 2" ⁇ 1 term.
  • Shifters 214, 216 and 218 are each receive 0 and 1 as inputs to the 1 and 0 data ports of a first multiplexer.
  • the number of multiplexers in each shifter increases from shifter 214 having 1 multiplexer to shifter 218 having m multiplexers. In shifters having more than 1 multiplexer, the output of each multiplexer is provided as the input to 1 port of the next multiplexer. Control of the multiplexer is handled by the inp[x] signal.
  • Figure 21 illustrates the use of the address generator 193 of the present invention in an interleaver memory such as interleavers 156, 160, 164 and 168.
  • the interleaver contains both interleaver controller 220 and a plurality of memory cells, or storage elements 222.
  • Interleaver controller 220 determines a storage address for each incoming sample, reads out the data in the storage address, and sends the received sample to the determined storage address. This allows for re-use of a memory element, such as elements 224, 226, 228 and 230, after it has been read out.
  • Interleaver controller 220 includes address generator 193, which is preferably implemented as described above, and multiplexers 232 and 234. Multiplexer 232 receives the samples from the input channel, and routes them to one of the plurality of memory elements 222 in accordance with the address generated by address generator 193. Multiplexer 234 receives the same address from address generator 193, and reads out the data stored in the addressed memory element. Thus, address generator 193 not only generates the addresses to which data is saved, but also generates the addresses from which data is read, which allows the output channel to transmit the permuted sequence. Address generator 193 has as an input ctr[], which allows for synchronization with the input sequence of samples.
  • FIG. 22 illustrates a method of interleaving according to the present invention.
  • step 240 a predetermined number of samples are received and stored in the memory.
  • n/2 samples are stored, and the capacity of the memory is n/2 to achieve 100% utilization of the allocated resources, however one skilled in the art will appreciate that the number of stored elements is determined by the maximum distance between two input samples that are adjacent in the permuted output sequence.
  • the above described embodiment of the present invention receives the input sequence Xo, X ⁇ , x 2 ,..., X n/2 . ⁇ , Xn/2 ⁇ Xn/ 2 + ⁇ n- ⁇ and permutes it to provide the interleaver output pattern of Xo, X n / 2 , X ⁇ , X n 2
  • the first n/2 samples are stored in sequential memory addresses, so that the first sample Xo would be stored in memory address 0, as shown in the timing diagram of Figure 17.
  • the address of the memory element storing the first sample in the permuted sequence is determined.
  • the contents of the memory element at the determined address are read out, and replaced with a newly received sample.
  • step 248 the address of the next sample in the permuted sequence is determined, and the process returns to step 244.
  • incoming samples are received they are placed in the memory element storing the sample that is read out.
  • n/2 samples are initially stored in step 240, the actual number of samples that has to be stored is determined by the maximum distance between samples, and the permuted output order of the samples.
  • a single dual port memory is used in the interleaver along with two address generators.
  • the first address generator is used to determine the address to which data will be written, while the second generator is used to determine the address from which data is read out.
  • the first address generator is used to determine the address to which data will be written, while the second generator is used to determine the address from which data is read out.
  • the read controller can then use this signal to determine if data is available for reading (i.e. by comparing the write ctr to the read ctr).
  • the write controller writes data every time data is presented to it.
  • the read controller monitors the amount of data that has been written and begins reading when the first n/2 samples have been written. At this point the read is driven by the input data presentation, however once the full n samples have been written to the memory unit the read controller then continuously dumps the presented output data regardless of whether input data is presented or not.
  • One skilled in the art will appreciate that such an embodiment can be implemented using two address generators 193, as described above, one for the read address generator and one for the write address generator.
  • the two address generators 193 would be connected to each other, so that the read controller can determine if data is available, either by determining that the required sample has been stored, or that a complete n samples have been stored.
  • Such an interleaver architecture allows the write address generator to determine a storage address for a received sample, while the read address generator determines the storage address associated with the next output sample.
  • the connection between the two address generators allows a comparison of the read and write counters to allow the write address generator to avoid overwriting valid data, while allowing the read address generator to determine which addresses contain valid data to allow for reading out the memory addresses in the correct order.
  • the interleaver of the present invention can be used in a number of other environments.
  • the above described interleaver is applicable to, but not limited to, use in other discrete transform applications, such as z-transform processors and Hadamard transform processors.
  • Table 1 A comparison of the hardware requirements of the prior art pipeline processor FFT architectures is shown in Table 1. In order to ease comparisons of radix-2 with radix-4 architectures all values in Table 1 have been listed using the base-4 logarithm. The results show that the R2SDP architecture of this invention reduces the requirement for complex multipliers, complex adders, and memory allocation with out-of-order input data. With in- order input data the memory size doubles in order to implement a buffer to generate the bit- reversed data sequence for the FFT processor.
  • the address generation scheme of the R2SDP design is more complex than a simple R2SDF or R2MDC implementation, however the requirements for the rest of the system are significantly smaller than those two implementations, offsetting the area and cost of the extra controls.
  • a radix-4 implementation (“R4SDP") utilizing interleavers extended for the purpose can achieve a multiplier count of 75% that described for the radix-2 algorithm by removing redundant multiplications.
  • a radix-8 design following this invention can achieve a reduced multiplier count of 66% that described for the radix-2 design by further reducing redundant multiplications.

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Abstract

Dans cette invention, on utilise un entrelaceur avec des processeurs de transformation pour obtenir un générateur d'adresses permettant une mise en oeuvre au moyen d'un encombrement de mémoire réduit et permettant l'entrelacement d'une séquence d'entrée tout en réduisant au minimum les temps de latence.
PCT/CA2004/002048 2003-11-26 2004-11-26 Memoire a entrelacement WO2005052798A1 (fr)

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US52487903P 2003-11-26 2003-11-26
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CA 2451167 CA2451167A1 (fr) 2003-11-26 2003-11-26 Processeur fft a pipeline permettant l'entrelacement des adresses de memoire
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CN101650706B (zh) * 2009-06-30 2012-02-22 重庆重邮信科通信技术有限公司 Fft分支计算方法及装置

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