WO2005041457A1

WO2005041457A1 - Ofdm transmitter/receiver apparatus

Info

Publication number: WO2005041457A1
Application number: PCT/JP2004/014721
Authority: WO
Inventors: Yoshiteru Matsushita; Seiichi Sanpei
Original assignee: Sharp Kabushiki Kaisha
Priority date: 2003-10-23
Filing date: 2004-10-06
Publication date: 2005-05-06
Also published as: JPWO2005041457A1; JP4287432B2

Abstract

In a radio communication system using OFDM/MTPC method, the MLI demodulation success rate is improved. An MLI demodulation part (100) includes an MLI vector addition part (101) for performing a vector addition of MLI symbol portions outputted from a demultiplexer (214); and an error detection circuit (105) for detecting, from an output signal of a symbol demodulation circuit (218), an error by use of an error detection code or the like. The MLI vector addition part (101) comprises a vector addition circuit (102) for vector adding an output of the demultiplexer (214) to an output of a storage circuit (103); the storage circuit (103) for storing an output of the vector addition circuit (102); and a switch circuit (104) for switching between the output of the demultiplexer (214) and the output of the vector addition circuit (102).

Description

Specification

OFDM transceiver

Technical field

[0001] The present invention relates to an OF DM transmission / reception apparatus applied to an orthogonal frequency division multiplexing (hereinafter referred to as OFDM) transmission method used in a wireless communication system.

Background art

[0002] OFDM is a type of multi-carrier modulation scheme, and is characterized in that it is more resistant to multipath fading that occurs when propagation paths are complicated by an obstacle than conventional single-carrier modulation schemes.

However, even in the case of an OFDM signal, multipath fading reduces the received power of subcarriers of a specific frequency as shown in FIG. 19, and a desired signal-to-noise power ratio (Signal to Noise). Power Ratio: In the case where SNR can not be obtained, some data can not be demodulated, and the transmission capacity of the system decreases.

In order to solve such problems, measures as shown in FIGS. 20 to 22 have been conventionally taken.

(1) As shown in FIG. 20, the first countermeasure is reception based on multipath fading based on propagation path characteristics of each subcarrier between the transmitting side (shown left) and the receiving side (shown right). This is a subcarrier transmission power control system that adjusts the transmission power of each subcarrier in a manner to compensate for the power attenuation.

(2) As the second measure, as shown in FIG. 21, the attenuation of received power is large due to multipath fading, the subcarrier is low, the modulation scheme with multiple levels is small, the subcarrier is high, This is an adaptive modulation scheme that transmits with a multi-level modulation scheme.

(3) As a third measure, as shown in FIG. 22, multilevel transmission power is used to perform adaptive modulation and adjust the transmission power of subcarriers transmitting data so as to obtain a desired SNR. It is a control method (Multilevel Transmit Power Control: hereinafter referred to as "MTPC method"). Among the above three measures from the first to the third, from the viewpoints of limiting the maximum value of transmission power etc., efficiently using subcarriers, and taking measures against multipath fading, 3 The second MTPC method is attracting attention!

[0009] FIG. 23 is a diagram showing a configuration example of a frame format in the case of transmission according to the OFDMZ MTPC system. As shown in FIG. 23, the transmission frame 201 is composed of ten slots 202-1 to 202-10, and each slot 202-1 to 202-10 is roughly divided into synchronous Z control data part 203 and And the user data unit 204.

[0010] A channel estimation data string 205 (Channel Estimation word known to the receiving side used for channel estimation, which defines the modulation scheme of each subcarrier, which is a feature of the OFDMZ MTPC scheme, and the transmission power of each subcarrier. (Hereinafter referred to as CE)) and “modulation method information 206 (Modulation Level Information: hereinafter referred to as MLI)” for notifying the receiving side of the modulation method of each subcarrier for transmitting user data. , Sync Z control data unit 203 is included. MLI is usually updated every frame.

[0011] When transmitting a signal of the frame format shown in FIG. 23, according to the OFDMZMTPC system, modulation schemes of subcarriers in the synchronous Z control data unit and transmission powers of the subcarriers are as follows.

[0012] (1) The modulation scheme of all subcarriers is unified into a high reliability modulation scheme that is highly resistant to noise such as BPSK.

(2) When transmitting CE data, the transmission powers of the respective subcarriers are all made equal. When transmitting MLI data, the transmit power of each subcarrier is adjusted according to the channel quality so that the receiver can obtain the desired reception CNR for each subcarrier.

The modulation scheme of subcarriers in the user data section and the transmission power of each subcarrier are transmitted as follows.

(1) The modulation scheme for each subcarrier is the modulation scheme specified by MLI in the synchronous Z control data section.

(2) The transmit power of each subcarrier is adjusted according to the quality of the propagation path so that the desired reception CNR can be obtained on the reception side for each subcarrier. (3) A subcarrier hole may be used without transmitting power to subcarriers with extremely poor propagation path quality.

FIG. 24 shows the configuration of a communication device of the OFDMZ MTPC communication system. The RF signal is input to the OFDMZMTPC demodulation circuit 209 through the reception antenna 211 and the RF down converter 212 which down converts the RF signal.

Then, the OFDMZMTPC demodulation circuit 209 converts the RF downconverter output 212 into an analog signal strength digital signal, an analog Z digital conversion circuit 213, and an output of the analog Z digital conversion circuit 213 in the slot configuration shown in FIG. In addition, the demultiplexer 214 separately outputs each of the CE data unit 205, the MLI symbol unit 206, and the user data symbol unit 204, and the FFT circuit 215-1-215-3 for Fourier transforming the output of the demultiplexer 214 , Fourier transform circuit 215-1: A propagation path estimation circuit 216 that compares received CE data reproduced by the reference CE data with reference CE data and estimates the quality of the propagation path of each subcarrier; and Fourier transform circuit 215-2. A propagation path compensation circuit 217 performs propagation path compensation on the regenerated received MLI symbol based on the estimation result of the propagation path estimation circuit 216. A symbol demodulation circuit 218 that demodulates MLI data from the received MLI symbols that are channel-compensated by the path compensation circuit 217, and a demodulation scheme designation circuit that designates the demodulation scheme of each subcarrier of user data based on the demodulated MLI 2 19 and a channel compensation circuit 220 for performing channel compensation based on the estimation result of the channel estimation circuit 216 with respect to the received user data symbol reproduced by the Fourier transform circuit 215-3, and the channel compensation circuit The symbol demodulation circuit 221 demodulates the reception user data symbol subjected to propagation path compensation in 220 by the demodulation method of the user data symbol portion of each subcarrier designated by the demodulation method designation circuit 219, and the symbol portion demodulation circuit 221. A decoding circuit 222 for performing error correction and expansion processing on the demodulated code / user data and decoding the user data; There is.

In the circuit shown in FIG. 24, the CE, MLI, and portions for demodulating user data can be summarized as follows.

(L) A CE demodulation unit composed of an FFT circuit 215-1.

(2) FFT circuit 215-2 and propagation path compensation circuit 217 composed of symbol demodulation circuit 218 MLI demodulator 223.

(3) FFT circuit 215-3, propagation path compensation circuit 220, symbol demodulation circuit 221 and decoding circuit 22

2. A user data demodulator 224 comprising two.

The OFDMZ MTPC modulation circuit 210 includes the following configuration.

(1) Based on the propagation path estimation result for each subcarrier of propagation path estimation circuit 216 of OFDMZMTPC demodulation circuit 209, the transmission power of each subcarrier at the time of user data transmission, each subcarrier at the time of user data transmission Modulation scheme transmission power specification circuit 225 that determines the modulation scheme of the carrier.

(2) An encoding circuit 2 26 that performs processing such as compression encoding of user data and addition of an error correction code.

(3) Modulation scheme A symbol modulation circuit 2 27 that modulates user data encoded by the coding circuit 226 based on the modulation scheme of each subcarrier determined by the transmission power designation circuit 225.

(4) A transmission power control circuit 228 which adjusts the modulation signal output of the symbol modulation circuit 227 to a value determined by the modulation scheme transmission power designation circuit 225 for each subcarrier.

(5) Inverse Fourier Transform of Output of Transmission Power Control Circuit 228 IFFT Circuit 229.

(6) Modulation scheme MLI generation circuit 230 that generates an MLI based on the modulation scheme of each subcarrier at the time of user data transmission determined by the transmission power designation circuit 225.

(7) A symbol modulation circuit 231 that modulates the MLI generated by the MLI generation circuit 230.

(8) A transmission power control circuit 232 which adjusts the modulation signal output of the symbol modulation circuit 231 to a value determined by the modulation scheme transmission power designation circuit 225 for each subcarrier.

(9) IFFT circuit 233 that performs inverse Fourier transform on the output of the transmission power control circuit 232.

(10) CE generating circuit 234 for generating CE.

(L l) CE The IFFT circuit 235 that performs an inverse Fourier transform on the CE generated by the CE generation circuit 234.

(12) A multiplexer 236 which multiplexes the outputs of the three IFFT circuits (229, 233, 235) so as to have the slot configuration of FIG.

(13) A digital Z analog conversion circuit 237 which converts the output of the multiplexer 236 from a digital signal to an analog signal. [0038] In the above circuit shown in FIG. 24, the CE, MLI, and the part that modulates user data can be summarized as follows.

(1) A CE modulation unit 238 configured of a CE generation circuit 234 and an IFFT circuit 235.

(2) MLI modulation unit 239 including MLI generation circuit 230, symbol modulation circuit 231, transmission power control circuit 232, and IFFT circuit 233.

(3) Code circuit 226, symbol modulation circuit 227, transmission power control circuit 228, IFFT circuit 22

A user data modulation unit 240 comprising 9.

Then, the output of the OFDMZ MTPC modulation circuit 210 is transmitted through the up converter 241 and the transmission antenna 242.

Disclosure of the invention

Problem that invention tries to solve

[0043] MLI is basic information and must be transmitted using all subcarriers. It is necessary to give a large amount of transmit power to the sub-carriers present at the drop point of the transmission path characteristic etc. so as to obtain the required reception SNR.

While the transmission power control circuit controls the power by changing the amplitude by multiplying the coefficient according to the transmission power designation signal, the transmission power control circuit is a digital circuit, and therefore the multiplication coefficient and the multiplication result The data such as has a certain bit width. Therefore, there is a certain limit to the range in which power can be controlled.

Therefore, sufficient transmission power can not be provided, and even the required SNR of BPSK may not be satisfied. In such a case, since the receiver fails to demodulate the MLI and can not demodulate the data, the transmitter will repeat retransmission of the slot that failed to receive, resulting in the data transmission efficiency of the entire system. It will decrease.

[0046] In view of the above problems, the present invention aims to provide an OFDM transceiver capable of improving the probability of successful MLI demodulation in a wireless communication system using the OFDMZ MTPC scheme.

Non-Patent Document 1: 2003 IEICE General Conference "Study on interference countermeasures in 1 cell repetition OFDM adaptive modulation with multilevel transmission power control ZTDM A system" Means to solve the problem

[0047] According to one aspect of the present invention, as a means for reducing the influence of noise on MLI in the demodulation circuit, it is possible to perform vector calculation M on the MLI symbols of a plurality of slots in the same frame.

It is characterized by using LI generation means and using this vector addition MLI as MLI for user data demodulation (scheme 1).

[0048] Further, the vector addition MLI means of the above-mentioned method 1 is characterized in that the vector addition MLI is generated using the propagation path compensated MLI symbol (method 2). In addition, the vector addition MLI means of method 2 is characterized by using MLI transmitted by assigning data to different subcarriers in each slot (method 3). In addition, the demodulator circuit is characterized in that it comprises a majority decision circuit for comparing the MLI data bit strings of a plurality of slots in the same frame to make a majority decision as a means for improving the demodulation success rate (scheme 4).

Further, the majority decision judging means of the system 4 is characterized by using the MLI transmitted by assigning data to different subcarriers in each slot (system 5).

Further, the majority decision judging means of the system 4 is characterized by using the MLI transmitted by rearranging the data bit sequence for each slot (system 6).

[0051] Further, the data allocation subcarrier selection means of the above-mentioned method 3 and method 5 is a subcarrier selection method characterized in that reordering is performed according to a known reordering method at the transmitter / receiver.

(Method 7).

[0052] Further, the data allocation subcarrier selection means of the above-mentioned method 3 and method 5 is characterized by using the propagation path characteristic estimated from the slot sent from the receiver side (method 8).

) o

In addition, the data allocation subcarrier selection means of the above-mentioned method 8 is to select from among several kinds of arrays set in advance in order to reduce the amount of information for notifying the reception side of the arrangement of subcarriers to which data are allocated. It is characterized in that the optimal sequence is selected and the sequence number is notified (scheme 9).

In addition, the data allocation subcarrier selection means of the above-mentioned method 8 can reduce the amount of information for notifying the reception side of the arrangement of subcarriers to which data are allocated, by using the arrangement of each slot in the frame. Several combinations are set, and among It is characterized in that the appropriate combination is selected and the combination number is notified in the first slot (scheme 10).

Effect of the invention

According to the present invention, the probability of successful demodulation of MLI can be improved, and there is an advantage that a decrease in data transmission efficiency as a whole system can be avoided.

Brief description of the drawings

FIG. 1 is a block diagram showing a configuration of an MLI demodulation unit according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing a flow of vector addition processing operation according to the first embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration example of an MLI demodulation unit according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration example of an MLI demodulation unit according to a third embodiment of the present invention.

FIG. 5 is a flowchart showing a flow of majority decision processing operation according to the third embodiment of the present invention.

FIG. 6 is a diagram showing an example of majority decision processing according to the third embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration example of an MLI modulator according to a fourth embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration example of an MLI demodulation unit according to a fourth embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration example of an MLI modulator according to a fifth embodiment of the present invention.

FIG. 10 is a block diagram showing a configuration example of an MLI demodulation unit according to a fifth embodiment of the present invention.

FIG. 11 is a diagram showing a data allocation method according to the sixth embodiment of the present invention.

FIG. 12 is a block diagram showing a configuration example of an OFDM Z MTPC modulation circuit according to a seventh embodiment of the present invention.

[FIG. 13] A block showing an example of configuration of a data sorting unit according to the seventh embodiment of the present invention FIG.

FIG. 14 is a diagram showing an example of a slot format according to the seventh embodiment of the present invention.

FIG. 15 is a flowchart showing a flow of data rearrangement processing operation according to the seventh embodiment of the present invention.

FIG. 16 is a correspondence table of MLI symbols to subcarriers in the conventional rearrangement scheme.

FIG. 17 is a MLI symbol-to-subcarrier correspondence table according to the eighth embodiment of the present invention.

FIG. 18 is a correspondence table of slot pair reordering scheme combinations according to the ninth embodiment of the present invention.

[Fig. 19] Spectrum in the conventional orthogonal frequency division multiplexing system

[Fig. 20] This is a spectrum in an orthogonal frequency division multiplexing system using subcarrier transmission power control.

[Fig. 21] A spectrum in an orthogonal frequency division multiplexing system using an adaptive modulation scheme.

[Fig. 22] A spectrum in an orthogonal frequency division multiplexing system using a multilevel transmission power control system.

FIG. 23 is a diagram showing a frame format in an orthogonal frequency division multiplexing system using a multilevel transmission power control system.

[Fig. 24] A communication device of an orthogonal frequency division multiplexing system using a conventional multilevel transmission power control system.

BEST MODE FOR CARRYING OUT THE INVENTION

First, the transmission / reception apparatus according to the first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a configuration example of the MLI demodulation unit according to the present embodiment. As shown in FIG. 1, the MLI demodulation unit 100 generates an error based on an error detection code or the like from the MLI vector addition unit 101 that performs vector addition of the MLI symbol unit output from the demultiplexer 214 and the output signal of the symbol demodulation circuit 218. And an error detection circuit 105 for detecting the

The MLI vector addition unit 101 stores the output of the vector addition circuit 102 for performing vector addition of the output of the demultiplexer 214 and the output of the memory circuit 103, and the output of the vector addition circuit 102. And a switching circuit 104 for switching the output of the demultiplexer 214 and the output of the vector addition circuit 102.

FIG. 2 is a flowchart showing the flow of the vector calculation process. The operation of the beta addition processing when the Nth slot after MLI modulation is received will be described according to the flowchart of FIG. 2 with reference to FIG. At the start of the demodulation operation, the switching circuit 104 is set to output the output signal of the demultiplexer 128 !.

First, in step S1, the Nth slot is received in step S1 and the received MLI in the Nth slot is demodulated (step S2). The error detection circuit 102 determines whether or not the MLI has successfully demodulated the power (step S3). As a result of the determination in step S3, when it is determined that the MLI demodulation has failed, the switching circuit 104 is switched to the vector addition circuit 102 side (step S4).

[0061] Vector calculation circuit 102 includes an MLI symbol portion of the Nth slot output from demultiplexer 214 and an MLI symbol portion from the 1st slot stored in storage circuit 103 to the (N-1) th slot. The vector calculation result of the vector calculation is performed (step S5).

The storage circuit 103 stores the result of vector addition of the MLI symbol part from the first slot to the Nth slot, which is output from the vector addition circuit 102 (step S6). The vector addition results are demodulated (step S7). The switching circuit 104 is switched to the multiplexer 214 (step S8). The error detection circuit 105 determines whether the vector addition result has been correctly demodulated (step S9).

If it is determined in step S 9 that the demodulation of the vector addition result has failed, the process returns to step S 1 to receive the next (N + 1) -th slot. After that, it operates according to the above rules. As a result of the determination in step S3 and step S9, when it is determined that the demodulation is successful, the data stored in the memory circuit 103 is discarded (step S10). If the MLI demodulation succeeds, the user data in the slot in the same frame is demodulated using that MLI. When the next frame is received, the MLI is demodulated again in the above manner.

[0064] Using the above-described technique, the MLI of each slot in the same frame is the same, while the noise components included in those slots have no correlation. Therefore, by performing vector addition, only the desired signal power can be strengthened, and the SNR can be improved.

Next, a demodulation technique according to the second embodiment of the present invention will be described. Figure 3 is a book It is a figure which shows the structural example of the MLI demodulation part 106 by embodiment. In MLI demodulation section 106, MLI vector addition section 107 performs vector addition of the MLI symbol section output from propagation path compensation circuit 217. Since the propagation path changes with time, the amount of phase rotation that each slot receives in the propagation path is different. The demodulation unit according to the present embodiment compensates for the rotation of the phase with the propagation path compensation circuit and adds the force vectors, so that the desired signal can be efficiently added compared to the first embodiment. The amount of improvement is significant.

Next, a demodulator according to a third embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a diagram showing a configuration example of the MLI demodulation unit 108 according to the present embodiment. The MLI demodulation unit 108 includes a majority decision unit 119 that determines the symbol-demodulated MLI by majority.

Majority determination section 109 determines majority determination circuit 110 which determines the output of symbol demodulation circuit 218 and the output of storage circuit 111 by majority determination, storage circuit 111 storing the output of symbol demodulation circuit 218, and And a switching circuit 112 that switches between the output of the symbol demodulation circuit 218 and the output of the majority decision circuit 110.

FIG. 5 is a flowchart showing the flow of the majority decision processing operation. The flow of the majority decision process when the Nth slot is received will be described along the flow chart shown in FIG. At the start of the demodulation operation, the switching circuit 112 is set to output the symbol demodulation circuit output signal 218.

First, in step S11, the Nth slot is received. Then, in step S12, the received MLI of the Nth slot is demodulated. The error detection circuit 105 determines whether the MLI has been correctly demodulated (step S13). If it is determined in step S13 that the MLI demodulation has failed, it is determined whether the slot number N is even or odd (step S14). By performing the determination in step S14, the slot that has been correctly demodulated when N is even and the incorrect slot become the same number, and it becomes impossible to make the determination by majority decision, so it is meaningful to avoid the situation. If it is determined in step S14 that N is an even number, the process returns to step S11, and the next (N + 1) th slot is received. When N is an odd number, the switching circuit 112 is switched to the majority decision circuit 110 (step S15). The majority decision circuit 110 stores the N-th slot MLI output from the symbol modulation circuit 218 and the storage circuit 111. Each bit with the MLI from the existing first slot to the (N−1) slot is subjected to majority decision (step S16). As an example, the method of majority decision for the first to seventh seven slots will be described with reference to FIG.

The storage circuit 111 additionally stores the MLI output from the symbol demodulation circuit 218 (step S17), and demodulates the majority decision result (step S18). Next, the switching circuit 112 is switched to the symbol demodulation circuit 218 (step S19), and the error detection circuit 105 determines whether the majority decision result is correctly demodulated (step S20). As a result of the determination in step S20, when it is determined that the demodulation of the majority determination result has failed, the process returns to step S11, and the (N + 1) th slot is received. Thereafter, the operation is performed in accordance with the above rules. As a result of the determination in step S13 and step S20, when it is determined that the demodulation is successful, the data stored in the memory circuit 111 is discarded (step S21). If the MLI is successfully demodulated, user data in slots in the same frame is demodulated using that MLI. When the next frame is received, MLI demodulation is performed again by the above method.

In FIG. 6, it is determined that the demodulation is successful in all cases.

As described above, by performing the majority decision, there is an advantage that it is possible to correct an error appearing at a random position due to noise or the like.

Next, a modulator according to a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 7 is a diagram showing a configuration example of the MLI modulation unit 113 according to the present embodiment. The MLI modulation unit 113 includes an MLI generation circuit 230, a data rearrangement circuit 114 that rearranges bit strings output from the MLI generation circuit 230, a symbol modulation circuit 231, a transmission power control circuit 232, and an IFFT circuit 233. And. A signal is output from the IFFT circuit 233 to the multiplexer. FIG. 8 is a diagram showing a configuration example of the MLI demodulation unit 115 according to the present embodiment. According to the configuration of the MLI demodulation unit 108 according to the third embodiment, the MLI demodulation unit 115 rearranges the MLI, which has been symbol-demodulated and has become a bit string, in the reverse order of the transmission procedure, and puts it in the original order. A data rearrangement circuit 116 is provided.

[0074] Since MLI is basic information, even if there is a subcarrier with poor SNR, it is not possible to set a carrier hole, and transmission must be performed on all subcarriers. Therefore, even if it is retransmitted, the MLI symbol error transmitted on that subcarrier causes MLI. There is a high possibility of failing to demodulate. Therefore, in the present embodiment, the bit sequence of M LI is rearranged for each slot and transmission is performed. Since the SNR is low and the bits transmitted on subcarriers are different in each slot, when demodulation and rearrangement are performed in the original order, the position at which error bits appear is different in each S slot. Therefore, the error correction ability of the majority decision is extremely excellent against such an error, so that there is an advantage that the MLI demodulation success probability can be improved.

Next, a modulation / demodulation unit according to a fifth embodiment of the present invention will be described with reference to the drawings. FIG. 9 is a diagram showing a configuration example of the MLI modulation unit 117 according to the present embodiment. As shown in FIG. 9, the MLI modulator 117 according to the present embodiment is characterized in that it comprises a data reordering circuit 118 for reordering the output from the symbol modulation circuit 231. FIG. 10 is a diagram showing a configuration example of the MLI demodulation unit 119 according to the present embodiment. In addition to the configuration of the MLI demodulation unit 106 according to the second embodiment, the MLI demodulation unit 119 rearranges the propagation path compensated MLI symbols in the reverse procedure to that for transmission, and restores the data to the original order. A replacement circuit 120 is provided. In the second embodiment of the present invention, when there is a subcarrier with an extremely low SNR due to, for example, a drop in channel characteristics, the SNR of the MLI symbol transmitted in the subcarrier over several slots is bad. Therefore, even if vector power calculation is performed, the amount of improvement in the SNR of the M LI symbol is small, which becomes a bottleneck of the MLI demodulation success probability.

Therefore, in the present embodiment, by transmitting the MLI symbols allocated to different subcarriers in each slot, it is possible to prevent the SNR of a specific MLI symbol from being lowered, and the MLI demodulation success probability Has the advantage of being able to improve

Next, a modulation / demodulation unit according to a sixth embodiment of the present invention will be described with reference to the drawings. FIG. 11 is a diagram showing an assignment method when the number of subcarriers in the present embodiment is 32. The symbols dl to d32 shown in FIG. 11 are MLI symbols. Also, let SC1-SC32 be the subcarrier number. The reordering method when transmitting the second slot is as follows.

(1) The subcarrier is divided into two blocks of SC1-SC16 and SC17-SC32, which are respectively referred to as a first block and a second block. (2) The MLI symbol transmitted in the first block when transmitting the first slot is assigned to the second block.

(3) When transmitting the first slot, the MLI symbol transmitted in the second block is assigned to the first block.

The rearrangement scheme when transmitting the third slot is as follows.

(1) The subcarrier is divided into four blocks of SC1-SC8, SC9-SC16, SC17-SC24, and SC25-SC32, which are respectively referred to as a first block, a second block, a third block, and a fourth block.

(2) The MLI symbol transmitted in the first block when transmitting the second slot is assigned to the second block.

(3) The MLI symbol transmitted in the second block when transmitting the second slot is assigned to the first block.

(4) The MLI symbol transmitted in the third block when transmitting the second slot is assigned to the fourth block.

(5) The MLI symbol transmitted in the fourth block when transmitting the second slot is assigned to the third block.

Thereafter, the third slot is divided into eight blocks, and the fourth slot is divided into 16 blocks, and MLI symbols are similarly allocated. If the number of blocks can not be divided equally, the remaining subcarriers are assigned to any block. In this embodiment, the number of subcarriers is equally divided and divided into blocks, and those blocks are allocated as a pair of two. MLI symbol replacement force is obtained. A similar effect can be obtained. The alternative method is not limited to the above-described method.

There is a correlation between propagation path characteristics received by adjacent subcarriers, so even if MLI symbols are assigned to adjacent subcarriers, the propagation path characteristics received will not change significantly. Since the purpose of the fifth embodiment is to avoid the lowering of the SNR of a particular MLI symbol, it is desirable to assign to subcarriers without correlation. The above reordering scheme has the advantage that all MLI symbols can be assigned to subcarriers away from the subcarriers used in the previous slot, and early MLI demodulation can be successful. Next, a seventh embodiment of the present invention will be described with reference to the drawings. This embodiment is one of the MLI symbol reordering methods performed by the data reordering circuit according to the fifth embodiment, and is characterized in that reordering is performed based on the propagation path estimation result.

FIG. 12 is a diagram showing a configuration example of the OFDM Z MTPC modulation circuit 121 according to the present embodiment. The OFDMZMTPC modulation circuit 121 is a data specifying a data reordering method of the data reordering circuit based on the propagation path estimation result for each subcarrier of the propagation path estimation circuit 216 (FIG. 24) of the OFDMZMTPC demodulation circuit 209 (FIG. 24). Based on the rearrangement scheme determined by the rearrangement designation unit 122 and the data rearrangement designation unit 122, the signal generation circuit 123 for generating a signal and the signal generated in the signal generation circuit 123 are modulated. A transmission power control circuit 125 for adjusting the modulation signal output of the symbol modulation circuit 124 and the symbol modulation circuit 124 to a value determined by the modulation type transmission power designation circuit 225 for each subcarrier, and an output of the transmission power control circuit 125 It comprises: an IFFT circuit 126 that performs inverse Fourier transform; and a data sorting circuit 127 that sorts data based on a data sorting specification signal.

FIG. 13 is a diagram showing a configuration example of the data rearrangement designation unit 122. As shown in FIG. As shown in FIG. 13, the data reordering specification unit 122 measures the power per subcarrier of the propagation path estimation result output from the propagation path estimation circuit 216 (FIG. 24) of the OFDMZMTPC demodulation circuit 209 (FIG. 24). Power calculation circuit 128 to be calculated, data sorting circuit 129 that rearranges the output signals of power calculation circuit 128 in subcarrier order as well as data, the output signal of data sorting circuit 129 and the output signal of storage circuit 131 The addition circuit 130 that adds the data, the storage circuit 131 that stores the output signal of the addition circuit 130, and the data arrangement that specifies the MLI symbol rearrangement method from the output signal of the addition circuit 130 and the output signal of the power calculation circuit 128 And a replacement designation circuit 132.

A frame format in the present embodiment is shown in FIG. At the end of CE subframe 205, Signal subframe 133 is inserted to indicate the sort order of the MLI symbols. The data reordering specification circuit 132 internally has a table in which subcarrier numbers and MLI symbol numbers correspond to each other. Sub carrier number column at present The subcarrier power of the propagation path estimation result of the channel number is sequentially written in the subcarrier power, and the MLI symbol number column indicates the MLI symbol number in order from the MLI symbol estimated that the transmit / receive power of the slot transmitted so far is small. Write The data rearrangement specification circuit 132 specifies the rearrangement scheme to assign the MLI symbol to the corresponding subcarrier on the table. The table is sequentially updated each time a slot is transmitted.

FIG. 15 is a flowchart showing the flow of the operation of the data rearrangement designation unit. The operation of the data reordering unit 122 at the time of Nth slot transmission will be described with reference to this flowchart. The power calculation circuit 128 takes the latest propagation path estimation result output from the propagation path estimation circuit 216 (FIG. 24) of the OFDMZMTPC demodulation circuit 209 (FIG. 24) as the propagation path estimation result at the time of the Nth slot transmission. The power of the propagation path estimation result for each subcarrier is calculated (step S31). The subcarriers are rearranged in descending order of the power of the propagation path estimation result, and the subcarrier numbers are written in the table (step S32). The data reordering specification circuit 132 specifies the reordering method so as to assign the MLI symbols to the corresponding subcarriers on the table (step S33). The data sorting circuit 231 sorts the MLI symbols in accordance with the data sorting designation signal (step S34). The data reordering circuit 129 reorders the power of the propagation path estimation result according to the data reordering designation signal. This corresponds to reordering the power of the channel estimation result at the time of Nth slot transmission in the order of MLI symbols (step S35). Adder circuit 130 calculates the power of the propagation path estimation result at the time of Nth slot transmission output from data reordering circuit 129 and the received power estimation value up to the (N-1) th slot output from storage circuit 131. Add the sum (step S36). The memory circuit 131 stores the output signal of the adder circuit 130 as the sum of the reception power estimated values up to the Nth slot (step S37). The MLI symbols are rearranged in ascending order of the sum of received power estimated values, and the MLI symbol number is written to the table (step S38). It is determined whether the frame processing has been completed (step S39). If it is determined in the step S39 that the frame processing has been completed and it is determined that the frame processing is completed, the process returns to the step S31 to prepare for the transmission of the (N + 1) th slot. Hereafter, it operates according to the above-mentioned rule. If it is determined as a result of step S39 that the frame processing has been completed, the data stored in the storage circuit 131 is discarded. And reset the table to the initial value (Reset: step S40).

According to the above method, reordering is performed based on channel estimation results! /, So that the situation in which the SNR of a particular MLI symbol is low can be reliably avoided. Also, since the reordering method can be finely controlled, there is an advantage that the SNR can be efficiently raised.

Next, a modem according to an eighth embodiment of the present invention will be described with reference to the drawings. The present embodiment is a kind of sorting method in the seventh embodiment, and relates to a sorting method for reducing the amount of sorting notification information. In the present embodiment, the number of subcarriers is 32.

First, as an example of general sort order notification information, the MLI symbol powers assigned to the first subcarrier are described in the previous slot in the order of MLI symbol power! Let's go. If the number of subcarriers is 32, 5 bits are required to indicate the subcarrier number, which is 32 for the number of subcarriers. Therefore, the sort order notification information is 5 x 32 = 160 (bits) Is required. An example of the sorting order notification information at this time is shown in FIG. From the left, correspondence between subcarrier numbers and data numbers at the time of transmission of the first slot, transmission of the second slot, and transmission of the third slot is shown.

In the present embodiment, eight types of rearrangement methods up to 18 shown in FIG. 17 are set in advance as the rearrangement method, and this rearrangement method is also known on the receiving side. I assume. In the seventh embodiment, data rearrangement is performed so as to assign the MLI symbols to the corresponding subcarriers on the table, but in the present embodiment, after considering the created table, Select the most appropriate sorting method out of the set 8 sorting methods, and sort according to the sorting method. As the subcarrier sort order notification information, it is possible to transmit the sort method number of 3 bits (represented by "000", "0 0 ...": L 11 "in FIG. 17) shown in the table. There is an advantage that the sort order notification information can be significantly reduced.

Next, a modulation / demodulation unit according to a ninth embodiment of the present invention will be described with reference to the drawings. The present embodiment is a sort of sorting method in the eighth embodiment, and is a sorting method for reducing the amount of sorting notification information. In the present embodiment, the subcarriers The number is 32 and 10 slots are one frame. In the present embodiment, eight combinations are set as shown in FIG. 18 as a combination of the reordering method performed in each slot up to the 10th slot also in the first slot power, and this reordering method is known on the receiving side as well. Shall be The numbers from 1 to 18 listed in the matrix in FIG. 18 correspond to the numbers from 1 to 8 in the reordering system shown in FIG. It is assumed that the variation of the propagation path is small within the frame time, and the combination of the eight types of permutation methods set in consideration of the propagation path estimation result at the time of the first slot transmission, assuming that the variation of the propagation path is small within the frame time. Select the optimal combination of sorting methods from. As the subcarrier rearrangement order notification information, it is possible to significantly reduce the rearrangement order notification information by transmitting the combination number of the 3-bit rearrangement scheme shown in the figure only in the first slot. There is an advantage.

It goes without saying that various modifications can be made to the OFDM communication apparatus according to each of the embodiments described above, which are not limited to the specifically described embodiments. For example, a program for causing a computer to execute the steps described in the above embodiments also falls within the scope of the present invention.

Industrial applicability

Since the SNR in high-speed data communication and the like can be significantly reduced, a communication system with good quality can be realized.

Claims

The scope of the claims

[1] A plurality of slots are used to transmit data and control information for demodulating the data in the same communication frame using a plurality of subcarriers, and at least each sub- A demodulator for use in a wireless communication system including modulation scheme information for notifying a receiving side of a modulation scheme of a carrier,

Vector-added modulation scheme information generation means for adding the amplitude component and the phase component of the received signal corresponding to the modulation scheme information to individual slots belonging to the same communication frame;

Data demodulation means for using the modulation scheme information subjected to vector addition as modulation scheme information at the time of demodulating each subcarrier corresponding to data in each slot present in the same communication frame;

Demodulator with.

[2] The vector addition modulation method information generation means includes vector addition modulation method information generation means for generating vector addition modulation method information using propagation path compensated modulation method information. Demodulator as described in.

[3] The modulation scheme information of the communication system according to claim 1 is

In the same frame, each slot is assigned to different subcarriers and transmitted,

The demodulator according to claim 1, wherein the vector addition modulation scheme information is generated using modulation scheme information assigned to different subcarriers for each slot.

[4] A demodulator for use in the wireless communication system according to claim 1;

The received signal corresponding to the modulation scheme information is symbol-demodulated with respect to each slot belonging to the same communication frame, and each bit string of the modulation scheme information of each symbol-demodulated slot is compared with each other for each bit sequence. A demodulator characterized in that bits are determined by majority decision, and a bit arrangement combining the determined bits is used as modulation scheme information at the time of demodulation of each subcarrier.

[5] Further, in the same frame, the modulation scheme information is allocated to different subcarriers for each slot and transmitted, and the modulation scheme information used for the majority decision is 5. The demodulator according to claim 4, wherein modulation scheme information assigned to different subcarriers is used for each slot.

[6] Further, in the same frame, the modulation scheme information is transmitted after being rearranged into a different bit arrangement for each slot.

The demodulator according to claim 6, wherein the modulation scheme information used for the majority decision is that the modulation scheme information rearranged to the bit arrangement for each slot is restored to the original arrangement and used. .

[7] The allocation method in each slot of the subcarrier is

In the first step, in the first allocated slot, the subcarrier to which the modulation scheme information is allocated is divided into a first subcarrier block and a second subcarrier block with reference to a frequency band,

In the second step, the frequency bands of the first subcarrier block and the second subcarrier block are exchanged,

In the third step, the second subcarrier block after exchange with the first subcarrier block after frequency band exchange is assigned to the next slot,

In the fourth step, each subcarrier block allocated in the third step is divided into the third subcarrier block and the fourth subcarrier block based on the frequency band,

In a fifth step, the frequency bands of the third subcarrier block and the fourth subcarrier block are exchanged,

In the sixth step, the third subcarrier block after frequency band exchange and the fourth subcarrier block after frequency band exchange are allocated to the next slot,

The demodulator according to claim 3, further comprising repeating the steps up to the sixth step.

[8] A receiving apparatus comprising the demodulator according to any one of claims 1 to 7, and a signal according to any one of claims 1 to 7 that is received by the demodulator. And a transmitter comprising a modulator for modulation.

[9] Further, in the control information, a series of symbols constituting the modulation scheme information for each slot is provided. The wireless communication system according to claim 1, further comprising rearranging order notification information for notifying the receiving side of the rearrangement information.

[10] A modulator for use in the wireless communication system according to claim 9;

It has a function to receive, as input information, the propagation path estimation result indicating the propagation path state of each subcarrier with the communication partner, and using the propagation path estimation result, the above-mentioned propagation path state of each subcarrier is used according to the propagation path state. A modulator comprising subcarrier selection means for selecting to which subcarrier modulation scheme information is to be assigned.

11. The modulator according to claim 10, wherein the propagation path estimation result is a propagation path characteristic of each subcarrier estimated from the slot sent from the receiving side.

[12] Further, the subcarrier selection means

11. The modulator according to claim 10, wherein sub-carriers are assigned by selecting an array pattern of a plurality of pieces of modulation scheme information set in advance.

[13] Further, the subcarrier selection means selects from the array pattern of the plurality of modulation system information set in advance, and notifies the communication partner of the alignment notion of the selected modulation system information in the first slot. The modulator according to claim 11, characterized in that:

[14] A demodulator for use in the wireless communication system according to claim 9;

The rearrangement order notification information is received, and the symbols of the modulation scheme information of each slot are rearranged so as to restore the original arrangement based on the rearrangement order notification information, and demodulation of each subcarrier is performed. A demodulator characterized in that it is used as modulation method information.

[15] A wireless communication device comprising: a transmitter having the modulator according to any one of claims 10 to 13; and a receiver having the demodulator according to claim 14.

[16] Using a plurality of subcarriers, and having a plurality of slots for transmitting data and control information for demodulating the data in the same communication frame, and at least each of the A demodulation method in a wireless communication system including modulation scheme information for notifying a receiving side of a modulation scheme of a carrier,

Generating vector addition modulation scheme information in which the amplitude component and the phase component of the reception signal corresponding to the modulation scheme information are added to each slot belonging to the same communication frame; A data demodulation step of using the modulation scheme information subjected to vector addition as modulation scheme information at the time of demodulating each subcarrier corresponding to data in each slot present in the same communication frame;

A demodulation method comprising:

A plurality of slots are used to transmit data and control information for demodulating the data in the same communication frame using a plurality of subcarriers, and at least the control information includes A modulation method in a wireless communication system including modulation method information for notifying a receiving side of a modulation method,

Receiving, as input information, a propagation path estimation result indicating a propagation path state of each subcarrier with a communication partner, and using the propagation path estimation result, the modulation scheme according to the propagation path state of each subcarrier And d) selecting a subcarrier to which information is to be assigned.