WHAT IS CLAIMED IS:
1. A thermoelectric device, comprising a first heat conducting layer having a cold pole and a second heat conducting layer substantially devoid of a hot pole, said first and said second heat conducting layers being interposed by at least one semiconductor layer, being under a potential difference and capable of transporting heat away from said first heat conducting layer, in a manner that said heat is dissipated substantially uniformly over said second heat conducting layer.
2. The device of claim 1, wherein a portion of said at least one semiconductor layer is characterized by a monotonically reducing Seebeck coefficient.
3. The device of claim 1, wherein a portion of said at least one semiconductor layer is characterized by a stepwise reducing Seebeck coefficient.
4. The device of claim 1, further comprising a heat sink being a thermal communication with said second heat conducting layer.
5. The device of claim 4, wherein said heat sink comprises a plurality of micro-structured fins, designed and constructed to allow accumulation of free electrons of said second heat conducting layer, thereby to improve dissipation of heat carried by said free electrons.
6. The device of claim 1, wherein said second heat conducting layer is a heat sink comprising a plurality of micro-structured fins, designed and constructed to allow accumulation of free electrons of said second heat conducting layer, thereby to improve dissipation of heat carried by said free electrons.
7. The device of claim 1, wherein at least one of said first heat conducting layer, said second heat conducting layer and said at least one semiconductor layer is flexible.
8. The device of claim 1, further comprising a substrate coupled to said first heat conducting layer.
9. The device of claim 1, further comprising at least one interface layer, positioned between said at least one semiconductor layer and said second heat conducting layer, said at least one interface layer being a semiconductor layer characterized by a monotonically reducing Seebeck coefficient.
10. The device of claim 1, further comprising at least one interface layer, positioned between said at least one semiconductor layer and said second heat conducting layer, said at least one interface layer being a semiconductor layer characterized by a stepwise reducing Seebeck coefficient.
11. The device of claim 9, wherein said at least one interface layer comprises a metallic impurity distributed spatially in a monotonically increasing fashion.
12. The device of claim 9, wherein said at least one interface layer is flexible.
13. The device of claim 9, further comprising at least one adhesion layer, positioned between said at least one interface layer and said second heat conducting layer.
14. The device of claim 8, further comprising at least one adhesion layer, positioned between said substrate and said first heat conducting layer.
15. The device of claim 9, further comprising at least one adhesion layer, positioned between said at least one interface layer and said second heat conducting layer.
16. The device of claim 1, further comprising at least one adhesion layer, positioned between said first heat conducting layer and said at least one semiconductor layer.
17. The device of claim 9, further comprising at least one adhesion layer, positioned between said at least one semiconductor layer and said at least one interface layer.
18. The device of claim 8, wherein said substrate is an organic substrate.
19. The device of claim 8, wherein said substrate is flexible.
20. The device of claim 8, wherein said substrate is made of a material selected from the group consisting of polyamide, alumina, aluminum, silicon, germanium, copper, silver, gold, quartz, glass, sapphire, polyethylene and polyvinyl chloride.
21. The device of claim 20, wherein said polyamide is kapton.
22. The device of claim 1, wherein said at least one semiconductor layer is made of a material selected so as to maximize a Seebeck coefficient thereof.
23. The device of claim 1, wherein said at least one semiconductor layer is made of a material selected so as to maximize a figure-of-merit thereof.
24. The device of claim 1, wherein said at least one semiconductor layer is selected from the group consisting of gallium arsenide, indium phosphide, silicon, silicon germanium, lead telluride, indium gallium arsenide, indium arsenide, indium antimonide, indium gallium arsenide antimonide, mercury cadmium telluride, mercury cadmium selenide, gallium nitride, aluminum gallium nitride, indium gallium nitride, indium arsenide phosphide, indium gallium arsenide phosphide, indium gallium aluminum arsenide, lead tin telluride, aluminum arsenide, aluminum antimonide, zinc selenide, zinc telluride, boron nitride, germanium, gallium phosphide, gallium
antimonide, gallium aluminum arsenide, gallium arsenide phosphide, gallium indium phosphide, gallium indium antimonide, bismuth telluride bismuth selenide , antimony telluride, bismuth antimony telluride and bismuth selenium telluride.
25. The device of claim 1, wherein said first heat conducting layer and said second heat conducting layer are each independently selected from the group consisting of copper, aluminum, silicon, germanium, gold and silver.
26. The device of claim 1, wherein a thickness of said first heat conducting layer is from about 0.005 μm to about 10 μm.
27. The device of claim 1, wherein a thickness of said second heat conducting layer is from about 0.1 μm to about 50 μm.
28. The device of claim 1, wherein a thickness of said at least one semiconductor layer is from about 0.1 μm to about 50 μm.
29. The device of claim 9, wherein a thickness of said at least one interface layer is from about 0.005 μm to about 10 μm.
30. The device of claim 1 , which is a thermoelectric cooler.
31. The device of claim 1 , which is a temperature stabilizer.
32. The device of claim 1, which is a thermal-to-electrical energy converter.
33. A thermoelectric device, comprising a first heat conducting layer having a hot pole and a second heat conducting layer substantially devoid of a cold pole, said first and said second heat conducting layers being interposed by at least one semiconductor layer, being under a potential difference and capable of transporting heat to said first heat conducting layer, in a manner that an environmental heat is collected, substantial uniformly, by a surface of said second heat conducting layer.
34. The device of claim 33, wherein a portion of said at least one semiconductor layer is characterized by a monotonically reducing Seebeck coefficient.
35. The device of claim 33, wherein a portion of said at least one semiconductor layer is characterized by a stepwise reducing Seebeck coefficient.
36. The device of claim 33, further comprising a heat sink being a thermal communication with said second heat conducting layer.
37. The device of claim 35, wherein said heat sink comprises a plurality of micro-structured fins, designed and constructed to allow accumulation of free electrons of said second heat conducting layer, thereby to improve collection of environmental heat by said free electrons.
38. The device of claim 33, wherein said second heat conducting layer is a heat sink comprising a plurality of micro-structured fins, designed and constructed to allow accumulation of free electrons of said second heat conducting layer, thereby to improve collection of environmental heat by said free electrons.
39. The device of claim 33, wherein at least one of said first heat conducting layer, said second heat conducting layer and said at least one semiconductor layer is flexible.
40. The device of claim 33, further comprising a substrate coupled to said first heat conducting layer.
41. The device of claim 33, further comprising at least one interface layer, positioned between said at least one semiconductor layer and said second heat conducting layer, said at least one interface layer being a semiconductor layer characterized by a monotonically reducing Seebeck coefficient.
42. The device of claim 33, further comprising at least one interface layer, positioned between said at least one semiconductor layer and said second heat
conducting layer, said at least one interface layer being a semiconductor layer characterized by a stepwise reducing Seebeck coefficient.
43. The device of claim 40, wherein said at least one interface layer comprises a metallic impurity distributed spatially in a monotonically increasing fashion.
44. The device of claim 40, wherein said at least one interface layer is flexible.
45. The device of claim 40, further comprising at least one adhesion layer, positioned between said at least one interface layer and said second heat conducting layer.
46. The device of claim 39, further comprising at least one adhesion layer, positioned between said substrate and said first heat conducting layer.
47. The device of claim 40, further comprising at least one adhesion layer, positioned between said at least one interface layer and said second heat conducting layer.
48. The device of claim 33, further comprising at least one adhesion layer, positioned between said first heat conducting layer and said at least one semiconductor layer.
49. The device of claim 40, further comprising at least one adhesion layer, positioned between said at least one semiconductor layer and said at least one interface layer.
50. The device of claim 39, wherein said substrate is an organic substrate.
51. The device of claim 39, wherein said substrate is flexible.
52. The device of claim 39, wherein said substiate is made of a material selected from the group consisting of polyamide, alumina, aluminum, silicon, germanium, copper, silver, gold, quartz, glass, sapphire, polyethylene and polyvinyl chloride.
53. The device of claim 50, wherein said polyamide is kapton.
54. The device of claim 33, wherein said at least one semiconductor layer is made of a material selected so as to maximize a Seebeck coefficient thereof.
55. The device of claim 33, wherein said at least one semiconductor layer is made of a material selected so as to maximize a figure-of-merit thereof.
56. The device of claim 33, wherein said at least one semiconductor layer is selected from the group consisting of gallium arsenide, indium phosphide, silicon, silicon germanium, lead telluride, indium gallium arsenide, indium arsenide, indium antimonide, indium gallium arsenide antimonide, mercury cadmium telluride, mercury cadmium selenide, gallium nitride, aluminum gallium nitride, indium gallium nitride, indium arsenide phosphide, indium gallium arsenide phosphide, indium galhum aluminum arsenide, lead tin telluride, aluminum arsenide, aluminum antimonide, zinc selenide, zinc telluride, boron nitride, germanium, gallium phosphide, gallium antimonide, gallium aluminum arsenide, gallium arsenide phosphide, gallium indium phosphide, gallium indium antimonide, bismuth telluride bismuth selenide , antimony telluride, bismuth antimony telluride and bismuth selenium telluride.
57. The device of claim 33, wherein said first heat conducting layer and said second heat conducting layer are each independently selected from the group consisting of copper, aluminum, silicon, germanium, gold and silver.
58. The device of claim 33, wherein a thickness of said first heat conducting layer is from about 0.1 μm to about 50 μm.
59. The device of claim 33, wherein a thickness of said second heat conducting layer is from about 0.1 μm to about 50 μm.
60. The device of claim 33, wherein a thickness of said at least one semiconductor layer is from about 0.005 μm to about 20 μm.
61. The device of claim 40, wherein a thickness of said at least one interface layer is from about 0.005 μm to about 10 μm.
62. The device of claim 33, which is a thermoelectric heater.
63. The device of claim 33, which is a thermal-to-electrical energy converter.
64. A thermoelectric device, comprising: (a) a first heat conducting layer having a cold pole; (b) a second heat conducting layer substantially devoid of a hot pole; (c) at least one semiconductor layer interposing said first and said second heat conducting layers, being under a potential difference and capable of transporting heat away from said first heat conducting layer; and (d) at least one interface layer, positioned between said at least one semiconductor layer and said second heat conducting layer, said at least one interface layer being designed and constructed to allow delivery of energy to electrons or holes, and to ntinimize dehvery of energy to phonons, thereby to dissipate heat substantially uniformly over said second heat conducting layer.
65. The device of claim 64, wherein a portion of said at least one interface layer is a semiconductor layer characterized by a monotonically reducing Seebeck coefficient.
66. The device of claim 64, wherein a portion of said at least one interface layer is a semiconductor layer characterized by a stepwise reducing Seebeck coefficient.
67. The device of claim 64, wherein said at least one interface layer comprises a metallic impurity distributed spatially in a monotonically increasing fashion.
68. The device of claim 64, further comprising a heat sink being a thermal communication with said second heat conducting layer.
69. The device of claim 68, wherein said heat sink comprises a plurality of micro-structured fins, designed and constructed to allow accumulation of free electrons of said second heat conducting layer, thereby to improve dissipation of heat carried by said free electrons.
70. The device of claim 64, wherein said second heat conducting layer is a heat sink comprising a plurality of micro-structured fins, designed and constructed to allow accumulation of free electrons of said second heat conducting layer, thereby to improve dissipation of heat carried by said free electrons.
71. The device of claim 64, wherein at least one of said first heat conducting layer, said second heat conducting layer and said at least one semiconductor layer is flexible.
72. The device of claim 64, further comprising a substiate coupled to said first heat conducting layer.
73. The device of claim 64, wherein said at least one interface layer is flexible.
74. The device of claim 64, further comprising at least one adhesion layer, positioned between said at least one interface layer and said second heat conducting layer.
75. The device of claim 72, further comprising at least one adhesion layer, positioned between said substiate and said first heat conducting layer.
76. The device of claim 64, further comprising at least one adhesion layer, positioned between said at least one interface layer and said second heat conducting layer.
77. The device of claim 64, further comprising at least one adhesion layer, positioned between said first heat conducting layer and said at least one semiconductor layer.
78. The device of claim 64, further comprising at least one adhesion layer, positioned between said at least one semiconductor layer and said at least one interface layer.
79. The device of claim 72, wherein said substrate is an organic substrate.
80. The device of claim 72, wherein said substrate is flexible.
81. The device of claim 72, wherein said substrate is made of a material selected from the group consisting of polyamide, alumina, aluminum, silicon, germanium, copper, silver, gold, quartz, glass, sapphire, polyethylene and polyvinyl chloride.
82. The device of claim 81 , wherein said polyamide is kapton.
83. The device of claim 64, wherein said at least one semiconductor layer is made of a material selected so as to maximize a Seebeck coefficient thereof.
84. The device of claim 64, wherein said at least one semiconductor layer is made of a material selected so as to maximize a figure-of-merit thereof.
85. The device of claim 64, wherein said at least one semiconductor layer is selected from the group consisting of gallium arsenide, indium phosphide, silicon, silicon germanium, lead telluride, indium gallium arsenide, indium arsenide, indium antimonide, indium gallium arsenide antimonide, mercury cadmium telluride, mercury
cadmium selenide, gallium nitride, aluminum gallium nitride, indium gallium nitride, indium arsenide phosphide, indium gallium arsenide phosphide, indium gallium aluminum arsenide, lead tin telluride, aluminum arsenide, aluminum antimonide, zinc selenide, zinc telluride, boron nitride, germanium, gallium phosphide, gallium antimonide, gallium aluminum arsenide, gallium arsenide phosphide, gallium indium phosphide, gallium indium antimonide, bismuth telluride bismuth selenide , antimony telluride, bismuth antimony telluride and bismuth selenium telluride.
86. The device of claim 64, wherein said first heat conducting layer and said second heat conducting layer are each independently selected from the group consisting of copper, aluminum, silicon, germanium, gold and silver.
87. The device of claim 64, wherein a thickness of said first heat conducting layer is from about 0.1 μm to about 50 μm.
88. The device of claim 64, wherein a thickness of said second heat conducting layer is from about 0.1 μm to about 50 μm.
89. The device of claim 64, wherein a thickness of said at least one semiconductor layer is from about 0.005 μm to about 20 μm.
90. The device of claim 64, wherein a thickness of said at least one interface layer is from about 0.005 μm to about 10 μm.
91. The device of claim 64, which is a thermoelectric cooler.
92. The device of claim 64, which is a temperature stabilizer.
93. The device of claim 64, which is a theπnal-to-electrical energy converter.
94. A thermoelectric device, comprising: (a) a first heat conducting layer having a hot pole;
(b) a second heat conducting layer substantially devoid of a cold pole; (c) at least one semiconductor layer interposing said first and said second heat conducting layers, being under a potential difference and capable of transporting heat to said first heat conducting layer; and (d) at least one interface layer, positioned between said at least one semiconductor layer and said second heat conducting layer, said at least one interface layer being designed and constructed to allow delivery of energy to electrons or holes, and to minimize delivery of energy to phonons, thereby to collect environmental heat, substantially uniformly, by a surface of said second heat conducting layer.
95. The device of claim 94, wherein a portion of said at least one interface layer is a semiconductor layer characterized by a monotonically reducing Seebeck coefficient.
96. The device of claim 94, wherein a portion of said at least one interface layer is a semiconductor layer characterized by a stepwise reducing Seebeck coefficient.
97. The device of claim 94, wherein said at least one interface layer comprises a metallic impurity distributed spatially in a monotonically increasing fashion.
98. The device of claim 94, further comprising a heat sink being a thermal communication with said second heat conducting layer.
99. The device of claim 98, wherein said heat sink comprises a plurality of micro-structured fins, designed and constructed to allow accumulation of free electrons of said second heat conducting layer, thereby to improve collection of environmental heat by said free elections.
100. The device of claim 94, wherein said second heat conducting layer is a heat sink comprising a plurality of micro-structured fins, designed and constructed to
allow accumulation of free electrons of said second heat conducting layer, thereby to improve collection of environmental heat by said free electrons.
101. The device of claim 94, wherein at least one of said first heat conducting layer, said second heat conducting layer and said at least one semiconductor layer is flexible.
102. The device of claim 94, further comprising a substrate coupled to said first heat conducting layer.
103. The device of claim 94, wherein said at least one interface layer is flexible.
104. The device of claim 94, further comprising at least one adhesion layer, positioned between said at least one interface layer and said second heat conducting layer.
105. The device of claim 102, further comprising at least one adhesion layer, positioned between said substiate and said first heat conducting layer.
106. The device of claim 94, further comprising at least one adhesion layer, positioned between said at least one interface layer and said second heat conducting layer.
107. The device of claim 94, further comprising at least one adhesion layer, positioned between said first heat conducting layer and said at least one semiconductor layer.
108. The device of claim 94, further comprising at least one adhesion layer, positioned between said at least one semiconductor layer and said at least one interface layer.
109. The device of claim 102, wherein said substrate is an organic substrate.
110. The device of claim 102, wherein said substrate is flexible.
111. The device of claim 102, wherein said substrate is made of a material selected from the group consisting of polyamide, alumina, aluminum, silicon, germanium, copper, silver, gold, quartz, glass, sapphire, polyethylene and polyvinyl chloride.
112. The device of claim 111, wherein said polyamide is kapton.
113. The device of claim 94, wherein said at least one semiconductor layer is made of a material selected so as to maximize a Seebeck coefficient thereof.
114. The device of claim 94, wherein said at least one semiconductor layer is made of a material selected so as to maximize a figure-of-merit thereof.
115. The device of claim 94, wherein said at least one semiconductor layer is selected from the group consisting of gallium arsenide, indium phosphide, silicon, silicon germanium, lead telluride, indium gallium arsenide, indium arsenide, indium antimonide, indium gallium arsenide antimonide, mercury cadmium telluride, mercury cadmium selenide, gallium nitride, aluminum gallium nitride, indium gallium nitride, indium arsenide phosphide, indium gallium arsenide phosphide, indium gallium aluminum arsenide, lead tin telluride, aluminum arsenide, aluminum antimonide, zinc selenide, zinc telluride, boron nitride, germanium, gallium phosphide, gallium antimonide, gallium aluminum arsenide, gallium arsenide phosphide, gallium indium phosphide, gallium indium antimonide, bismuth telluride bismuth selenide , antimony telluride, bismuth antimony telluride and bismuth selenium telluride.
116. The device of claim 94, wherein said first heat conductmg layer and said second heat conducting layer are each independently selected from the group consisting of copper, aluminum, silicon, germanium, gold and silver.
117. The device of claim 94, wherein a thickness of said first heat conducting layer is from about 0.1 μm to about 50 μm.
118. The device of claim 94, wherein a thickness of said second heat conducting layer is from about 0.1 μm to about 50 μm.
119. The device of claim 94, wherein a thickness of said at least one semiconductor layer is from about 0.005 μm to about 20 μm.
120. The device of claim 94, wherein a thickness of said at least one interface layer is from about 0.005 μm to about 10 μm.
121. The device of claim 94, which is a thermoelectric heater.
122. The device of claim 94, which is a thermal-to-electrical energy converter.
123. A method of manufacturing a thermoelectric device, the method comprising: (a) depositing a first heat conducting layer on a substrate; (b) depositing at least one semiconductor layer on said first heat conducting layer; (c) depositing at least one interface layer on said at least one semiconductor layer; (d) depositing a second heat conducting layer on said at least one interface layer; wherein said at least one interface layer being designed and constructed to allow delivery of energy to electrons or holes, and to minimize delivery of energy to phonons, thereby to dissipate heat substantially unifoπnly over said second heat conducting layer.
124. The method of claim 123, wherein a portion of said at least one interface layer is a semiconductor layer characterized by a monotonically reducing Seebeck coefficient.
125. The method of claim 123, wherein a portion of said at least one interface layer is a semiconductor layer characterized by a stepwise reducing Seebeck coefficient.
126. The method of claim 123, wherein said at least one interface layer comprises a metallic impurity distributed spatially in a monotonically increasing fashion.
127. The method of claim 123, further comprising providing a heat sink and coupling said heat sink to said second heat conducting layer.
128. The method of claim 127, wherein said heat sink comprises a plurality of micro-structured fins, designed and constructed to allow accumulation of free electrons of said second heat conducting layer, thereby to improve dissipation of heat carried by said free electrons.
129. The method of claim 123, wherein at least one of said first heat conducting layer, said second heat conducting layer and said at least one semiconductor layer is flexible.
130. The method of claim 123, wherein said at least one interface layer is flexible.
131. The method of claim 123, further comprising applying at least one adhesion layer on said at least one interface layer prior to said deposition of said second heat conducting layer.
132. The method of claim 123, further comprising applying at least one adhesion layer on said substrate prior to said deposition of said first heat conducting layer.
133. The method of claim 123, further comprising applying at least one adhesion layer on said at least one interface layer prior to said deposition of said second heat conducting layer.
134. The method of claim 123, further comprising applying at least one adhesion layer on said first heat conducting layer prior to said deposition of said at least one semiconductor layer.
135. The method of claim 123, further comprising applying at least one adhesion layer on said at least one semiconductor layer prior to said deposition of said at least one interface layer.
136. The method of claim 123, wherein said substrate is an organic substrate.
137. The method of claim 123, wherein said substrate is flexible.
138. The method of claim 123, wherein said substiate is made of a material selected from the group consisting of polyamide, alumina, aluminum, silicon, germanium, copper, silver, gold, quartz, glass, sapphire, polyethylene and polyvinyl chloride.
139. The method of claim 138, wherein said polyamide is kapton.
140. The method of claim 123, wherein said at least one semiconductor layer is made of a material selected so as to maximize a Seebeck coefficient thereof.
141. The method of claim 123, wherein said at least one semiconductor layer is made of a material selected so as to maximize a figure-of-merit thereof.
142. The method of claim 123, wherein said at least one semiconductor layer is selected from the group consisting of gallium arsenide, indium phosphide, silicon, silicon germanium, lead telluride, indium gallium arsenide, indium arsenide, indium
antimonide, indium gallium arsenide antimonide, mercury cadmium telluride, mercury cadmium selenide, gallium nitride, aluminum gallium nitride, indium gallium nitride, indium arsenide phosphide, indium gallium arsenide phosphide, indium gallium aluminum arsenide, lead tin telluride, aluminum arsenide, aluminum antimonide, zinc selenide, zinc telluride, boron nitride, germanium, gallium phosphide, gallium antimonide, gallium aluminum arsenide, gallium arsenide phosphide, gallium indium phosphide, gallium indium antimonide, bismuth telluride bismuth selenide , antimony telluride, bismuth antimony telluride and bismuth selenium telluride.
143. The method of claim 123, wherein said first heat conducting layer and said second heat conducting layer are each independently selected from the group consisting of copper, aluminum, silicon, germanium, gold and silver.
144. The method of claim 123, wherein a thickness of said first heat conducting layer is from about 0.1 μm to about 50 μm.
145. The method of claim 123, wherein a thickness of said second heat conducting layer is from about 0.1 μm to about 50 μm.
146. The method of claim 123, wherein a thickness of said at least one semiconductor layer is from about 0.005 μm to about 20 μm.
147. The method of claim 123, wherein a thickness of said at least one interface layer is from about 0.005 μm to about 10 μm.
148. The method of claim 123, wherein the device is a thermoelectric cooler.
149. The method of claim 28, wherein the device is temperature stabilizer.
150. The method of claim 123, wherein the device wherein the device is a thermal-to-electrical energy converter.
151. A method of cooling an object, the method comprising,
(a) absorbing heat from the object using a first heat conducting layer; (b) transporting said heat away from said first heat conducting layer through at least one semiconductor layer being under a potential difference; and (c) delivering said heat to free electrons present in a second heat conducting layer, and, at the same time, minimizing delivery of energy to phonons of said second heat conducting layer thereby dissipating heat substantially unifoπnly over said second heat conducting layer; thereby cooling the object.
152. The method of claim 151, wherein a portion of said at least one semiconductor layer is characterized by a monotonically reducing Seebeck coefficient.
153. The method of claim 151, wherein a portion of said at least one semiconductor layer is characterized by a stepwise reducing Seebeck coefficient.
154. The method of claim 151, further comprising dissipating heat to the environment using a heat sink being in a thermal communication with said second heat conducting layer.
155. The method of claim 154, wherein said heat sink comprises a plurality of micro-structured fins, designed and constructed to allow accumulation of said free electrons, thereby to improve said dissipation of heat.
156. The method of claim 151, wherein at least one of said first heat conducting layer, said second heat conducting layer and said at least one semiconductor layer is flexible.
157. The method of claim 151, wherein said delivering said heat to said free electrons is by at least one interface layer, positioned between said at least one semiconductor layer and said second heat conducting layer, said at least one interface layer being a semiconductor layer characterized by a monotonically reducing Seebeck coefficient.
158. The method of claim 151, wherein said delivering said heat to said free electrons is by at least one interface layer, positioned between said at least one semiconductor layer and said second heat conducting layer, said at least one interface layer being a semiconductor layer characterized by a stepwise reducing Seebeck coefficient.
159. The method of claim 157, wherein said at least one interface layer comprises a metallic impurity distributed spatially in a monotonically increasing fashion.
160. The method of claim 157, wherein said at least one interface layer is flexible.
161. The method of claim 151, wherein said at least one semiconductor layer is made of a material selected so as to maximize a Seebeck coefficient thereof.
162. The method of claim 151, wherein said at least one semiconductor layer is made of a material selected so as to maximize a figure-of-merit thereof.
1.63. The method of claim 151, wherein said at least one semiconductor layer is selected from the group consisting of gallium arsenide, indium phosphide, silicon, silicon germanium, lead telluride, indium gallium arsenide, indium arsenide, indium antimonide, indium gallium arsenide antimonide, mercury cadmium telluride, mercury cadmium selenide, gallium nitride, aluminum gallium nitride, indium gallium nitride, indium arsenide phosphide, indium gallium arsenide phosphide, indium gallium aluminum arsenide, lead tin telluride, aluminum arsenide, aluminum antimonide, zinc selenide, zinc telluride, boron nitride, germanium, gallium phosphide, gallium antimonide, gallium aluminum arsenide, gallium arsenide phosphide, gallium indium phosphide, gallium indium antimonide, bismuth telluride bismuth selenide , antimony telluride, bismuth antimony telluride and bismuth selenium telluride.
164. The method of claim 151, wherein said first heat conducting layer and said second heat conducting layer are each independently selected from the group consisting of copper, aluminum, silicon, germanium, gold and silver.
165. The method of claim 151, wherein a thickness of said first heat conducting layer is from about 0.1 μm to about 50 μm.
166. The method of claim 151, wherein a thickness of said second heat conducting layer is from about 0.1 μm to about 50 μm.
167. The method of claim 151, wherein a thickness of said at least one semiconductor layer is from about 0.0O5 μm to about 20 μm.
168. The method of claim 157, wherein a thickness of said at least one interface layer is from about 0.005 μm to about 10 μm.
169. A thermoelectric system having an arrangement of thermoelectric devices, each one of said thermoelectric devices comprising a first heat conducting layer having a cold pole and a second heat conducting layer substantially devoid of a hot pole, said first and said second heat conducting layers being interposed by at least one semiconductor layer, being under a potential difference and capable of transporting heat away from said first heat conducting layer, in a manner that said heat is dissipated substantially uniformly over said second heat conducting layer.
170. The system of claim 169, wherein a portion of said at least one semiconductor layer is characterized by a monotonically reducing Seebeck coefficient.
171. The system of claim 169, wherein a portion of said at least one semiconductor layer is characterized by a stepwise reducing Seebeck coefficient.
172. The system of claim 1 9, further comprising a heat sink being a thermal communication with said second heat conducting layer.
173. The system of claim 172, wherein said heat sink comprises a plurality of micro-structured fins, designed and constructed to allow accumulation of free electrons of said second heat conducting layer, thereby to improve dissipation of heat carried by said free electrons.
174. The system of claim 169, wherein said second heat conducting layer is a heat sink comprising a plurality of micro-structured fins, designed and constructed to allow accumulation of free electrons of said second heat conducting layer, thereby to improve dissipation of heat carried by said free electrons.
175. The system of claim 169, wherein at least one of said first heat conducting layer, said second heat conducting layer and said at least one semiconductor layer is flexible.
176. The system of claim 169, further comprising a substrate coupled to said first heat conducting layer.
177. The system of claim 169, further comprising at least one interface layer, positioned between said at least one semiconductor layer and said second heat conducting layer, said at least one interface layer being a semiconductor layer characterized by a monotonically reducing Seebeck coefficient.
178. The system of claim 169, further comprising at least one interface layer, positioned between said at least one semiconductor layer and said second heat conducting layer, said at least one interface layer being a semiconductor layer characterized by a stepwise reducing Seebeck coefficient.
179. The system of claim 177, wherein said at least one interface layer comprises a metallic impurity distributed spatially in a monotonically increasing fashion.
180. The system of claim 177, wherein said at least one interface layer is flexible.
181. The system of claim 177, further comprising at least one adhesion layer, positioned between said at least one interface layer and said second heat conducting layer.
182. The system of claim 176, further comprising at least one adhesion layer, positioned between said substrate and said first heat conducting layer.
183. The system of claim 177, further comprising at least one adhesion layer, positioned between said at least one interface layer and said second heat conducting layer.
184. The system of claim 169, further comprising at least one adhesion layer, positioned between said first heat conducting layer and said at least one semiconductor layer.
185. The system of claim 177, further comprising at least one adhesion layer, positioned between said at least one semiconductor layer and said at least one interface layer.
186. The system of claim 176, wherein said substiate is an organic substrate.
187. The system of claim 176, wherein said substrate is flexible.
188. The system of claim 176, wherein said substrate is made of a material selected from the group consisting of polyamide, alumina, aluminum, silicon, germanium, copper, silver, gold, quartz, glass, sapphire, polyethylene and polyvinyl chloride.
189. The system of claim 188, wherein said polyamide is kapton.
190. The system of claim 169, wherein said at least one semiconductor layer is made of a material selected so as to maximize a Seebeck coefficient thereof.
191. The system of claim 169, wherein said at least one semiconductor layer is made of a material selected so as to maximize a figure-of-merit thereof.
192. The system of claim 169, wherein said at least one semiconductor layer is selected from the group consisting of gallium arsenide, indium phosphide, silicon, silicon germanium, lead telluride, indium gallium arsenide, indium arsenide, indium antimonide, indium gallium arsenide antimonide, mercury cadmium telluride, mercury cadmium selenide, gallium nitride, aluminum gallium nitride, indium gallium nitride, indium arsenide phosphide, indium gallium arsenide phosphide, indium gallium alurninum arsenide, lead tin telluride, aluminum arsenide, aluminum antimonide, zinc selenide, zinc telluride, boron nitride, germanium, gallium phosphide, gallium antimonide, gallium aluminum arsenide, gallium arsenide phosphide, gallium indium phosphide, gallium indium antimonide, bismuth telluride bismuth selenide , antimony telluride, bismuth antimony telluride and bismuth selenium telluride.
193. The system of claim 169, wherein said first heat conducting layer and said second heat conducting layer are each independently selected from the group consisting of copper, aluminum, silicon, germanium, gold and silver.
194. The system of claim 169, wherein a thickness of said first heat conducting layer is from about 0.1 μm to about 50 μm.
195. The system of claim 169, wherein a thickness of said second heat conducting layer is from about 0.1 μm to about 50 μm.
196. The system of claim 169, wherein a thickness of said at least one semiconductor layer is from about 0.005 μm to about 20 μm.
197. The system of claim 177, wherein a thickness of said at least one interface layer is from about 0.005 μm to about 10 μm.
198. The system of claim 169, which is a thermoelectric cooler.
199. The system of claim 169, which is a temperature stabilizer.
200. The system of claim 169, which is a thermal-to-electrical energy converter.
201. An electronic chip having at least one thermoelectric device integrated thereon, the at least one thermoelectric device comprising a first heat conducting layer having a cold pole and a second heat conducting layer substantially devoid of a hot pole, said first and said second heat conducting layers being interposed by at least one semiconductor layer, being under a potential difference and capable of transporting heat away from said first heat conducting layer, in a manner that said heat is dissipated substantially uniformly over said second heat conducting layer.
202. The electronic chip of claim 201, wherein a portion of said at least one semiconductor layer is characterized by a monotonically reducing Seebeck coefficient.
203. The electronic chip of claim 201, wherein a portion of said at least one semiconductor layer is characterized by a stepwise reducing Seebeck coefficient.
204. The electronic chip of claim 201 , further comprising a heat sink being a thermal communication with said second heat conducting layer.
205. The electronic chip of claim 204, wherein said heat sink comprises a plurality of micro-structured fins, designed and constructed to allow accumulation of free electrons of said second heat conducting layer, thereby to improve dissipation of heat carried by said free electrons.
206. The electronic chip of claim 201, wherein said second heat conducting layer is a heat sink comprising a plurality of micro-structured fins, designed and constructed to allow accumulation of free electrons of said second heat conducting layer, thereby to improve dissipation of heat carried by said free electrons.
207. The electronic chip of claim 201, wherein at least one of said first heat conducting layer, said second heat conducting layer and said at least one semiconductor layer is flexible.
208. The electronic chip of claim 201, further comprising a substrate coupled to said first heat conducting layer.
209. The electronic chip of claim 201, further comprising at least one interface layer, positioned between said at least one semiconductor layer and said second heat conducting layer, said at least one interface layer being a semiconductor layer characterized by a monotonically reducing Seebeck coefficient.
210. The electronic chip of claim 201, further comprising at least one interface layer, positioned between said at least one semiconductor layer and said second heat conducting layer, said at least one interface layer being a semiconductor layer characterized by a stepwise reducing Seebeck coefficient.
211. The electronic chip of claim 209, wherein said at least one interface layer comprises a metallic impurity distributed spatially in a monotonically increasing fashion.
212. The electronic chip of claim 209, wherein said at least one interface layer is flexible.
213. The electronic chip of claim 209, further comprising at least one adhesion layer, positioned between said at least one interface layer and said second heat conducting layer.
214. The electronic chip of claim 208, further comprising at least one adhesion layer, positioned between said substrate and said first heat conducting layer.
215. The electronic chip of claim 209, further comprising at least one adhesion layer, positioned between said at least one interface layer and said second heat conducting layer.
216. The electronic chip of claim 201, further comprising at least one adhesion layer, positioned between said first heat conducting layer and said at least one semiconductor layer.
217. The electronic chip of claim 209, further comprising at least one adhesion layer, positioned between said at least one semiconductor layer and said at least one interface layer.
218. The electronic chip of claim 208, wherein said substrate is an organic substrate.
219. The electronic chip of claim 208, wherein said substrate is flexible.
220. The electronic chip of claim 208, wherein said substrate is made of a material selected from the group consisting of polyamide, alumina, aluminum, silicon, germanium, copper, silver, gold, quartz, glass, sapphire, polyethylene and polyvinyl chloride.
221. The electronic chip of claim 220, wherein said polyamide is kapton.
222. The electronic chip of claim 201, wherein said at least one semiconductor layer is made of a material selected so as to maximize a Seebeck coefficient thereof.
223. The electronic chip of claim 201, wherein said at least one semiconductor layer is made of a material selected so as to maximize a figure-of-merit thereof.
224. The electronic chip of claim 201, wherein said at least one semiconductor layer is selected from the group consisting of gallium arsenide, indium phosphide, silicon, silicon germanium, lead telluride, indium gallium arsenide, indium arsenide, indium antimonide, indium gallium arsenide antimomde, mercury cadmium telluride, mercury cadmium selenide, gallium nitride, aluminum gallium nitride, indium gallium nitride, indium arsenide phosphide, indium gallium arsenide phosphide, indium gallium aluminum arsenide, lead tin telluride, aluminum arsemde, aluminum antimonide, zinc selenide, zinc telluride, boron nitride, germanium, gallium phosphide, gallium antimonide, gallium aluminum arsenide, gallium arsenide phosphide, gallium indium phosphide, gallium indium antimonide, bismuth telluride bismuth selenide , antimony telluride, bismuth antimony telluride and bismuth selenium telluride.
225. The electronic chip of claim 201, wherein said first heat conducting layer and said second heat conducting layer are each independently selected from the group consisting of copper, aluminum, silicon, germanium, gold and silver.
226. The electronic chip of claim 201, wherein a thickness of said first heat conducting layer is from about 0.1 μm to about 50 μm.
227. The electronic chip of claim 201, wherein a thickness of said second heat conducting layer is from about 0.1 μm to about 50 μm.
228. The electronic chip of claim 201, wherein a thickness of said at least one semiconductor layer is from about 0.005 μm to about 20 μm.
229. The electronic chip of claim 209, wherein a thickness of said at least one interface layer is from about 0.005 μm to about 10 μm.
230. A device for converting thermal energy into electrical energy, the device comprising: (a) a first heat conducting layer having a hot pole; (b) a second heat conducting layer substantially devoid of a cold pole;
(c) a third heat conducting layer having a cold pole and being in thermal communication with said first heat conducting layer; (d) a fourth heat conducting layer substantially devoid of a hot pole; (e) a first semiconductor layer positioned between said first and said second heat conducting layers; and (f) a second semiconductor layer positioned between said third and said fourth heat conducting layers; said first and said second semiconductor layers are designed and constructed such that when environmental heat is collected, substantial uniformly, by a surface of said second heat conducting layer, transferred to said cold pole through said hot pole, and dissipated, substantially unifoπnly, over said second heat conducting layer, an electric potential difference is developed on said first and said second semiconductor layers.
231. The device of claim 230, wherein a portion of said first and said second semiconductor layers is characterized by a monotonically reducing Seebeck coefficient.
232. The device of claim 230, wherein a portion of said first and said second semiconductor layers is characterized by a stepwise reducing Seebeck coefficient.
233. The device of claim 230, further comprising a heat sink being a thermal communication with at least one of said second heat conducting layer and said fourth heat conducting layer.
234. The device of claim 230, further comprising at least one interface layer, positioned between said first semiconductor layer and said second heat conducting layer, said at least one interface layer being a semiconductor layer characterized by a monotonically reducing Seebeck coefficient.
235. The device of claim 230, further comprising at least one interface layer, positioned between said second semiconductor layer and said fourth heat conducting
layer, said at least one interface layer being a semiconductor layer characterized by a monotonically reducing Seebeck coefficient.
236. The device of claim 230, further comprising at least one interface layer, positioned between said at least one semiconductor layer and said second heat conducting layer, said at least one interface layer being a semiconductor layer characterized by a stepwise reducing Seebeck coefficient.
237. The device of claim 230, further comprising at least one interface layer, positioned between said second semiconductor layer and said fourth heat conducting layer, said at least one interface layer being a semiconductor layer characterized by a stepwise reducing Seebeck coefficient.
238. The device of claim 234, wherein said at least one interface layer comprises a metallic impurity distributed spatially in a monotonically increasing fashion.
239. The device of claim 235, wherein said at least one interface layer comprises a metallic impurity distributed spatially in a monotonically increasing fashion.
240. The device of claim 230, wherein at least one of said first semiconductor layer and said second first semiconductor layer is made of a material selected so as to maximize a Seebeck coefficient thereof.
241. The device of claim 230, wherein at least one of said first semiconductor layer and said second first semiconductor layer is made of a material selected so as to maximize a figure-of-merit thereof.
242. The device of claim 230, wherein said first semiconductor layer and said second first semiconductor layer are selected from the group consisting of gallium arsenide, indium phosphide, silicon, silicon germanium, lead telluride, indium gallium arsenide, indium arsenide, indium antimonide, indium gallium arsemde antimonide,
mercury cadmium telluride, mercury cadmium selenide, gallium nitride, aluminum gallium nitride, indium gallium nitride, indium arsenide phosphide, indium gallium arsenide phosphide, indium galhum aluminum arsenide, lead tin telluride, aluminum arsenide, aluminum antimomde, zinc selenide, zinc telluride, boron nitride, germanium, gallium phosphide, gallium antimonide, gallium aluminum arsenide, gallium arsenide phosphide, gallium indium phosphide, gallium indium antimonide, bismuth telluride bismuth selenide , antimony telluride, bismuth antimony telluride and bismuth selenium telluride.
243. The device of claim 230, wherein said heat conducting layers are each independently selected from the group consisting of copper, aluminum, silicon, germanium, gold and silver.