WO2005041042A3 - Memory interface for systems with multiple processors and one memory system - Google Patents

Memory interface for systems with multiple processors and one memory system Download PDF

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Publication number
WO2005041042A3
WO2005041042A3 PCT/EP2004/011163 EP2004011163W WO2005041042A3 WO 2005041042 A3 WO2005041042 A3 WO 2005041042A3 EP 2004011163 W EP2004011163 W EP 2004011163W WO 2005041042 A3 WO2005041042 A3 WO 2005041042A3
Authority
WO
WIPO (PCT)
Prior art keywords
cpu
memory
abstract
external memory
time slot
Prior art date
Application number
PCT/EP2004/011163
Other languages
French (fr)
Other versions
WO2005041042A2 (en
Inventor
Fredrik Angsmark
Tord Nilsson
David Barrow
Original Assignee
Ericsson Telefon Ab L M
Fredrik Angsmark
Tord Nilsson
David Barrow
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M, Fredrik Angsmark, Tord Nilsson, David Barrow filed Critical Ericsson Telefon Ab L M
Priority to KR1020067006802A priority Critical patent/KR101050019B1/en
Priority to CN2004800293261A priority patent/CN1864140B/en
Priority to EP04765854A priority patent/EP1685484B1/en
Priority to JP2006530103A priority patent/JP2007508607A/en
Priority to DE602004012310T priority patent/DE602004012310T2/en
Publication of WO2005041042A2 publication Critical patent/WO2005041042A2/en
Publication of WO2005041042A3 publication Critical patent/WO2005041042A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
    • G06F12/1425—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block
    • G06F12/1441—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block for a range
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Security & Cryptography (AREA)
  • Multi Processors (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

Memory interface for multi-CPU system provides predefined time slots in which each CPU may access an external memory. The time slot assigned to each CPU may be defined according to the expected memory requirements of the CPU. In this way, each CPU is guaranteed to have a certain amount of dedicated bandwidth to the external memory. The predefined time slots also allow the latency of the system to be known, which is useful for real-time oriented applications. Moreover, each CPU may use its own clock during its allotted time slot to control the external memory, thus accommodating various clock domains in the system. Memory refresh and data protection functions are also provided. This Abstract is provided to comply with rules requiring an Abstract that allows a searcher or other reader to quickly ascertain subject matter of the technical disclosure. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
PCT/EP2004/011163 2003-10-08 2004-10-06 Memory interface for systems with multiple processors and one memory system WO2005041042A2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1020067006802A KR101050019B1 (en) 2003-10-08 2004-10-06 Memory interface for systems with multiple processors and one memory system
CN2004800293261A CN1864140B (en) 2003-10-08 2004-10-06 Memory interface for systems with multiple processors and one memory system
EP04765854A EP1685484B1 (en) 2003-10-08 2004-10-06 Memory interface for systems with multiple processors and one memory system
JP2006530103A JP2007508607A (en) 2003-10-08 2004-10-06 Memory interface for a system having multiple processors and a memory system
DE602004012310T DE602004012310T2 (en) 2003-10-08 2004-10-06 MEMORY INTERFACE FOR SYSTEMS WITH MULTIPLE PROCESSORS AND A STORAGE SYSTEM

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US50950303P 2003-10-08 2003-10-08
US60/509,503 2003-10-08
US51007403P 2003-10-09 2003-10-09
US60/510,074 2003-10-09
US53096003P 2003-12-19 2003-12-19
US60/530,960 2003-12-19
US10/857,319 US20050080999A1 (en) 2003-10-08 2004-05-27 Memory interface for systems with multiple processors and one memory system
US10/857,319 2004-05-27

Publications (2)

Publication Number Publication Date
WO2005041042A2 WO2005041042A2 (en) 2005-05-06
WO2005041042A3 true WO2005041042A3 (en) 2005-11-24

Family

ID=34427064

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2004/011163 WO2005041042A2 (en) 2003-10-08 2004-10-06 Memory interface for systems with multiple processors and one memory system

Country Status (8)

Country Link
US (1) US20050080999A1 (en)
EP (1) EP1685484B1 (en)
JP (1) JP2007508607A (en)
KR (1) KR101050019B1 (en)
CN (1) CN1864140B (en)
AT (1) ATE388439T1 (en)
DE (1) DE602004012310T2 (en)
WO (1) WO2005041042A2 (en)

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US7409572B1 (en) * 2003-12-05 2008-08-05 Lsi Corporation Low power memory controller with leaded double data rate DRAM package arranged on a two layer printed circuit board
WO2005074138A2 (en) * 2004-01-29 2005-08-11 Koninklijke Philips Electronics N.V. Programmable and pausable clock generation unit
DE102005038567A1 (en) * 2005-08-12 2007-02-15 Micronas Gmbh Multi-processor architecture and method for controlling memory access in a multi-process architecture
US7647476B2 (en) * 2006-03-14 2010-01-12 Intel Corporation Common analog interface for multiple processor cores
US7752373B2 (en) * 2007-02-09 2010-07-06 Sigmatel, Inc. System and method for controlling memory operations
US8694737B2 (en) 2010-06-09 2014-04-08 Micron Technology, Inc. Persistent memory for processor main memory
US9448938B2 (en) * 2010-06-09 2016-09-20 Micron Technology, Inc. Cache coherence protocol for persistent memories
US8799685B2 (en) * 2010-08-25 2014-08-05 Advanced Micro Devices, Inc. Circuits and methods for providing adjustable power consumption
US8613074B2 (en) 2010-09-30 2013-12-17 Micron Technology, Inc. Security protection for memory content of processor main memory
US20130117168A1 (en) 2011-11-04 2013-05-09 Mark Henrik Sandstrom Maximizing Throughput of Multi-user Parallel Data Processing Systems
US8561078B2 (en) * 2011-09-27 2013-10-15 Throughputer, Inc. Task switching and inter-task communications for multi-core processors
US8789065B2 (en) 2012-06-08 2014-07-22 Throughputer, Inc. System and method for input data load adaptive parallel processing
EP2686774B1 (en) * 2011-03-14 2017-02-01 Hewlett-Packard Enterprise Development LP Memory interface
JP5716824B2 (en) * 2011-03-28 2015-05-13 富士通株式会社 Multi-core processor system
US8683100B1 (en) 2011-06-21 2014-03-25 Netlogic Microsystems, Inc. Method and apparatus for handling data flow in a multi-chip environment using an interchip interface
US9448847B2 (en) 2011-07-15 2016-09-20 Throughputer, Inc. Concurrent program execution optimization
CN105339917A (en) 2013-05-30 2016-02-17 惠普发展公司，有限责任合伙企业 Separate memory controllers to access data in memory
CN105612493A (en) * 2013-09-30 2016-05-25 慧与发展有限责任合伙企业 Programming memory controllers to allow performance of active memory operations
US12061803B2 (en) * 2020-10-14 2024-08-13 Microchip Technology Incorporated System with increasing protected storage area and erase protection

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US5010476A (en) * 1986-06-20 1991-04-23 International Business Machines Corporation Time multiplexed system for tightly coupling pipelined processors to separate shared instruction and data storage units
US5659688A (en) * 1992-11-25 1997-08-19 Zilog, Inc. Technique and circuit for providing two or more processors with time multiplexed access to a shared system resource
EP1132818A2 (en) * 1999-12-21 2001-09-12 Visteon Global Technologies, Inc. Multiple processor interface, synchronization, and arbitration scheme using time multiplexed shared memory for real time systems
US20010029590A1 (en) * 1996-11-13 2001-10-11 Intel Corporation Processor having execution core sections operating at different clock rates
US20020166017A1 (en) * 2001-05-02 2002-11-07 Kim Jason Seung-Min Cross bar multipath resource controller system and method

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US5010476A (en) * 1986-06-20 1991-04-23 International Business Machines Corporation Time multiplexed system for tightly coupling pipelined processors to separate shared instruction and data storage units
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Also Published As

Publication number Publication date
DE602004012310D1 (en) 2008-04-17
WO2005041042A2 (en) 2005-05-06
CN1864140A (en) 2006-11-15
EP1685484A2 (en) 2006-08-02
US20050080999A1 (en) 2005-04-14
EP1685484B1 (en) 2008-03-05
KR101050019B1 (en) 2011-07-19
JP2007508607A (en) 2007-04-05
ATE388439T1 (en) 2008-03-15
CN1864140B (en) 2013-03-20
KR20060134923A (en) 2006-12-28
DE602004012310T2 (en) 2009-03-19

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