WO2005038920A2

WO2005038920A2 - Embedded power supplies, particularly for ultra large scale integrated circuits

Info

Publication number: WO2005038920A2
Application number: PCT/GB2004/004382
Authority: WO
Inventors: Mark Huggins
Original assignee: Xipower Limited
Priority date: 2003-10-17
Filing date: 2004-10-15
Publication date: 2005-04-28
Also published as: GB0609237D0; WO2005038920A3; GB2425196B; GB2425196A; GB0324292D0

Abstract

A solid state device of system level integration or system-on-chip (24) is provided comprising, in a single semiconductor chip, an embedded power management system (18) to cooperate with an external power source (16, 20). The semiconductor chip may comprise a plurality of system blocks and in which one of the system blocks is surrounded by a guard ring maintained at a higher voltage that the voltage supply to the system block. The embedded power management system may also comprise low drop out voltage regulators comprising an amplifier and feedforward paths feeding into the bias system of the amplifier. The power management system may be under the control of the digital core (10).

Description

Embedded Power Supplies, particularly for Ultra Large Scale Integrated Circuits

This invention relates to power supplies and particularly, but not exclusively, to power supplies for System On Chip (SoC) and other ultra large scale ±ntegrated circuits.

Most SoC devices in commercial use rely on external ϋevices to provide the required power supplies from a. battery or other voltage source. This increases costs, complexity, and the number of physical connections and it would obviously be desirable to -avoid this .

Additionally, as semiconductor device geometries have shrunk to accommodate ever greater functionality on the same semiconductor area, the requirements of power management have increased. In particular, smaller cLevice geometries have required lower operating voltages -while the battery voltage from which the device is powered has remained largely unchanged, leaving a greater voltage difference between the system chip.- requirements and the battery supply. This -voltage difference is generally externally stepped clown by external power management devices such as linear voltage regulators or switching voltage regulators. Linear voltage regulators are low noise but low efficiency devices, whereas switching regulators are high efficiency but high noise.

System level integration requires a low noise supply, and due to the supply being powered by battery a high efficiency is desirable.

More generally, it has not hitherto been possible to include an entire power management system within System level Integration or SoC. Power management includes monitoring and controlling the charging of any battery, supervising the distribution of power to various elements such as the digital core and digital and analog I/O, and responding to control signals from the digital core asking for increases in power as equipment usage demands and making appropriate decisions about the best mode of power delivery for a particular set of circumstances. The technical problems of electrical noise, thermal dissipation and oevice incompatibility with SLI or SoC process flows have to date prevented large scale integration of power management circuitry.

There have been attempts to provide Low Drop Out (LDO) voltage regulators on SoC devices to step the battery voltage down to the device core voltage, but this is an inefficient technique and results in the pr-oduction of hotspots on the system level integrated device. LDO regulators are increasingly used as power filters to isolate one functional circuit block from another within the same system. This has placed enormous demands on power supply ripple rejection (PSRR) , both, in terms of magnitude and the rejection bandwidth. Current state of the art calls for PSRR of >60dB up to 40kHz and >40dB up to 100kHz. Future generations of portable appliances are demanding >60dB up to 100kHz and better than 40dB up to 1MHz . To achieve these higher levels of PSRR, designers of LDO voltage regulators have had to increase the bandwidth of the LDO control loop, but this inevitably increases current consumption and is not consistent with increasing the battery life of portable appliances.

It is also known to provide noise isolation in large scale integrated circuits by the use of guard rings. However, known forms of guard ring have limitations, especially in pure CMOS circuits, as is discussed further below.

The present invention, in one aspect, provides a solid state device of system level integration or system-on- chip which comprises, in a single semiconductor chip, a digital core, one or more input/output cir/cuits, and an embedded power management system arranged to cooperate with an external power source.

In preferred forms of the invention, the power management system comprises a common regulated power supply, preferably a quasi-resonant switching regulator which converts the battery voltage to a lower level and supplies a number of low drop out (LDO) voltage regulators distributed around the chip. Each of the LDO voltage regulators further reduces the voltage to provide a local supply to part of the system, and is preferably provided with a novel guard ring arrangement to minimise noise.

From another aspect, the invention resides in a. solid state device of system level integration or system-on- chip which comprises a plurality of system blocks in a single semiconductor chip, and in which at least one of said system blocks is surrounded by a guard ring maintained at a higher voltage than the voltage supply to the system block.

A further aspect of the present invention provides an integrated circuit which includes at least one voltage regulator in the form of a low drop out (LDO) voltage regulator; and in which the or each LDO voltage regulator comprises an amplifier and feedforward paths feeding into the bias system of the amplifier.

A further aspect of the. present invention provides an integrated circuit comprising a power supply circuit in the form of a resonant or quasi-resonant mode DC to DC converter, and in which said converter is adapted to operate at a switching frequency which is determined by the output load current of the converter.

Another aspect of the invention resides in an integrated circuit comprising a power supply arrangement formed by a resonant or quasi-resonant mode DC to DC converter which supplies one or more LDO voltage regulators .

Preferred features and advantages of the invention will be apparent from the following description and the claims.

Embodiments of the invention will now be (described, by way of example only, with reference to the drawings , in which:

Figure 1 is an overview of an embodiment of an SoC device embodying the present invention;

Figure 2 is a block diagram of a resonant switching converter used in the device of Figure 1;

Figure 3 is a schematic diagram of the operation of a half wave resonant converter circuit;

Figure 4 is a schematic diagram of the operation of a full wave resonant converter circuit;

Figure 5 shows operational current and voltage waveforms for the circuit shown in figure 2;

Figure 6 is a circuit diagram for a basic controller used in the present invention;

Figure 7 is a circuit diagram for a switch implementation used in the present invention;

Figure 8 is a graph relating to the efficiency of the converter of Figure 2 ;

Figure 9 is a block circuit diagram of a LDO voltage regulator used in the device of Figure 1 ;

Figure 10 is a circuit diagram for achieving high power supply ripple rejection;

Figure 11 provides an example of implementation of a high PSRR regulator;

Figure 12 is a block diagram of a quasi-resonant switching converter used in the device of Figure 1;

Figure 13 is a graph relating to the efficiency of the converter of Figure 2;

Figure 14 is a graph showing the relationship between frequency and output current in the converter of Figure 2;

Figure 15 illustrates, in plan and partial cross- section_r a prior art CMOS guard ring;

Figure 16 illustrates, in plan and cross-section, a prior art BiCMOS isolation scheme;

Figure 17 illustrates, in plan and partial cross-section_r a guard ring arrangement which may be used in the present invention; and

Figure 18 is a schematic of a current-fed charge pump which may be; used in implementing the guard ring of Figure 17 ; and

Figure 19 is an overview of a second embodiment of the present invention where the battery manager is embedded in a battery pack.

Referring to Figure 1, a typical SoC device comprises a digital core 10, a digital input/output (I/O) circuit 12 and an analog I/O circuit 14. A battery 16 powers the foregoing via a power management circuit 18, which also controls usage of a charge source 20 when this is connected.

It is known in the prior art to have the digital core 10 and Σ/O circuits 12, 14 implemented as a single SoC device as indicated by dashed line 22, with the power management circuit 18 formed by one or more external devices. In the present invention, the power management circuit 18 is an embedded circuit formed within the SoC device, as indicated by dashed line 24.

In the preferred form of the present invention, the power management circuit 18 comprises a resonant switching regulator connected to the system battery and supplying a number of LDO voltage regulators dispersed across the SoC device. A quasi-resonant switching regulator may also be used for this purpose.

The use of a resonant or quasi-resonant switching regulator to pre-regulate the supply provides high efficiency and overcomes the problem of noise being coupled through the semiconductor substrate by reducing di/dt and dv/dt. The distributed L.DO regulators act as distributed power filters to remove unwanted conducted noise and also spread the heat dissipation. It is also preferable to further reduce noise transmission by the use of guard rings, as described below.

In the embodiment shown in Figure 2, the battery 16 supplies 3.6V to resonant switching regulator 26. The output circuit of regulator 26 includes a resonant tank inductor L_r 21 and resonant tank capacitor C_r 23 and output capacitor C₀25. A stabilised and regulated voltage, in this example 2.2V, is provided across the capacitor C_D 25 which acts as an input voltage: to a first LDO voltage regulator 28 supplying a regulated 1.2V; to the digital core 10; to a second LDO voltage regulator 30 supplying a regulated 1.8V to the digital I/O circuit 12; and any other LDO voltage regulators as required, as indicated at 32. It will be understood that these voltages are examples only, and that different SoC or SLI will require different internal voltages depending on the nature of the incorporated circuits and components.

The battery voltage is also, in this embodiment, supplied directly to a further LDO voltage regulator 34 for supplying the analog I/O circuit 14 at 3.3V. It is generally suitable for LDO voltage regulators having an output within 0.5V of the battery supply voltage to be connected directly to the battery.

All the elements of Figure 2 (apart from the battery 16) are part of a single SoC device and the various LDO voltage regulators are physically separated within the SoC device. In Figure 2 , the frequency of operation F_sw is determined by the output load current. When the load current reduces, the frequency of operation reduces; this minimises switching losses and improves efficiency. When off load, the power switches Qi and Q₂ can be turned fully on to prevent switching and quiescent losses degrading efficiency. The resonant frequency F_r should be at least equal to the maximum switching frequency F_sw.

Control of the regulator 26 is achieved, in two parts:

(a) the resonant frequency is controlled by sensing zero resonant tank current after trigger.

(b) switching frequency is controlled by sensing the output voltage of the buck filter, as indicated by feedback loop 36. The resonant tank is triggered when the threshold output voltage falls below a defined threshold.

As an alternative, the switching frequency can be controlled by a signal output of a LDO voltage regulator, as indicated by feedback loop 38. This will keep the input voltage to the LDO voltage regulator at an optimum level for conversion efficiency.

The topology and operation of resonant switching regulator 26, is displayed in figure 3 with operational waveforms provided in figure 5. The topology consists of three switches and a series connected resonant LC tank. Switches QI 31 and Q2 33 switch at zero current and switch Q3 35 switches at zero voltage this operation eliminates all switching losses with trie exception of gate charge losses . The variable frequency operation extends efficiency at low loading by reducing gate charge losses. These innovations ensure high efficiency over a wide output load range as shown in figures 8 and 13.

A more detailed description of the operation of this circuit is provided as follows.

Charge Current, Ich 29, flows when switch Ql 31 is ON and switches Q2 33 and Q3 35 are OFF. Ql turns OFF when Ich 29 falls to zero. Q2 turns ON when Ql turns OFF and Idis 37 flows delivery energy to C₀ 25 and R₀ 27. When the voltage across C_r falls to zero, switch Q3 turns ON to enable complete discharge of L_r into C₀ and R₀. Once L_r has discharged its energy into C₀ and R₀ a new Ql charge cycle can begin. The Ql switch cycle is initiated by a controller that regulates output voltage, Vout .

Ich 29 can be sensed through the voltage dropped across Ql 31 . When Ql ^λON' voltage reverses, Ql 31 should be turned OFF to ensure resonant operation. Switch Ql 31 is ON for the first half cycle of resonant frequency, switch Q2 33 is ON for the second half cycle. During first half cycle the resonant tank is charged from input, during second half cycle the resonant tank is discharged into output load. Output voltage, Vout, is controlled by controlling the rate of charging of output capacitor C_Q 25, the operational frequency. The maximum operational frequency is equal to the resonant frequency.

Max Output Power neglecting Loses:

Operational Frequency neglecting Loses , F_E

Input Peak Current :

An alternative embodiment is shown in Figure 4 where two resonant converters are connected in parallel to double the output power capability and significantly reduce the input and output rms currents. The input current at full load resembles a rectified sinusoid as opposed to half wave rectified sinusoid for a single converter stage. The two converters operate 180 degrees out of phase with the primary converter Qla initiated by the voltage regulator and the secondary converter initiated by termination of primary converter Qla cycle.

Charge Current, Ich 39, flows when switch Ql is ON and switches Q2/Q3 are OFF. Qla 31a and Qlh 31b turns OFF when Ich 39 falls to zero. Q2a 33a and Q2b 33b turns ON when Ql turns OFF and Idis 41 flows delivery energy to C₀ 25 and R_Q 27. When the voltages across C_ra 35a and C_rb 35b falls to zero, switches Q3a and Q3b turn ON to enable complete discharge of L_r into C_σ 25 and R₀ 27. 1 2 Once L_ra and L_rb have discharged their energ-y into C_Q 25 3 and R_D 27 a new Ql charge cycle can begin. Qla switch 4 cycle is initiated by a controller that regulates output 5 voltage, Vout. 6 Qlb switch cycle initiated by Qla turn OFF. 7 8 Ich 39 can be sensed through the voltage dropped across 9 Ql (Qla and Qlb) . When Ql 'ON' voltage reverses, Ql

10 should be turned OFF to ensure resonant operation. Switch

11 Ql is ON for the first half cycle of resonant frequency,

12 switch Q2 is ON for the second half cycle . During first

13 half cycle the resonant tank is charged from input,

14 during second half cycle the resonant tank is discharged

15 into output load. Output voltage, Vout, is controlled by

16 controlling the rate of charging of output capacitor C₀,

17 the operational frequency. The maximum operational

18 frequency is twice the resonant frequency. 19

20 Max Output Power neglecting Loses: 21

22 Pømax = Cr./r.(2.Vm)²

23

24 Operational Frequency neglecting Loses, F_sw :

26 Input Peak Current :

28

29 It is also possible to have the resonant

30 converter external^" to the SoC device either as a discrete integrated circuit or as part of an ASIC forming the battery management system with all LDO voltage regulators being embedded on the SoC device .

In the circuit of Figure 2, the tank circuit C_ro, L_r 21 forces the current to a half sinusoid when the power switch Qi is turned on. The current pulse is terminated when the control circuitry senses that the switch current has fallen to zero. This allows the turn on and turn off to be conducted with zero switching loss .

Figure 5 provides operational voltage and current waveforms while figure 6 shows a typical controller implementation, with switch control, and figure 7 provides a typical switch implementation.

The controller of figure 6 comprises a Voltage Controlled Oscillator (VCO) 41 connected to a Monostable (MONO) with pulse width set at l/f_r. LOGIC 45 is provided to ensure Ql and Q2 are not ON at the same instant in time. Blk input 47 prevents a new Ql cycle from commencing until after complete discharge of the resonant tank into the output. Error amplifier 'a' controls the frequency of the Voltage Controlled Oscillator 41. Voltage Controlled Oscillator 41 controls the rate of energy delivery to output load which in turn controls output voltage. Clr 51 terminates the Ql cycle at zero current to ensure resonant operation.

The Ql zero current is sensed by amplifier 57 (c) . Amplifier 53 (d) ensures that energy can only flow from the resonant tank into output load. The resonant tank voltage V_r is twice Vin and is peak rectified to provide a drive voltage for Q2. V_r can provide a voltage source for the Guard Rings.

Figure 7 shows a typical switch implementation. Q3 is the Extended Drain (Lightly Doped Drain, LDD) . C_f is of order 20pf, use of guard ring capacitance. Q2a NMOS gate driven from peak rectified V_r. The guard ring can be driven from rectified V_r to remove the need for a charge pump. The switch Q2 is formed by NMOS and PMOS integrated circuits arranged in parallel to enable variable Vout .

Figure 8 is a graph of total efficiency against output current for the prior art 40 and the above embodiment 42 of the present invention with output voltage of 1.2V and battery voltage of 3.6V. Figure 14 shows the relationship of operational frequency versus output load current of the resonant switching regulator.

One suitable form of LDO voltage regulator circuit 71 for use in the system of Figure 2 is shown by way of example in Figure 9. Details of this example of the LDO regulator are as follows.

The regulator is PMOS type with an embedded output capacitor Co. The output capacitor Co utilises the highest capacitance density primitive which is a MOSCAP (NMOS configured in accumulation) . Typical values of InF may be achieved without too great a die area sacrifice. Though it may be desirable to make provision for a larger external discrete capacitor to provide access for testability and greater decoupling affect. Regulation is based on an amplifier 79 which is suitably a transconductance type with large signal speedup added to the output stage to provide fast dynamic response without having to resort to high bandwidth and high current consumption. To improve response time to fast dynamic changes in line and load, feedforward is used. Capacitor Clff feeds any line disturbance into the bias system in a way to reject the disturbance. In a similar manner capacitor Coff feeds any load disturbance into the bias system in a way to reject the load disturbance. These two feedforward paths reduce the bandwidth requirements of the amplifier 79 and hence keep the current consumption to a minimum.

This embodiment thus enables the provision of an LDO regulator with high PSRR, fast dynamic response and low operating current. The use of feedforward paths reduces the need for high control bandwidth. The use of feedforward paths feeding into the bias system of the amplifier offers large signal performance improvements. Output speedup networks improve the large signal slew rate of the low Iq amplifier.

An alternative embodiment 81 that provides wide bandwidth PSRR is shown in figure 10. To achieve high PSRR the error amplifier 83 (a) and bandgap voltage reference 85 (b) is supplied from the LDO voltage regulator output. The power PMOS 87 (e) device is driven by a transconductance amplifier 89 (c) configured in 'Unity Gain' to push the power PMOS 87 gate pole out beyond lOMhz to remove it from the active control bandwidth of around IMhz. The Unity Gain amplifier 89 (c) also serves to provide a low gate source impedance to the power PMOS which ^Λ common modes' any gate source ripple derived from the LDO voltage regulator input supply and hence removes any output voltage modulation effect thus helping to attain high PSRR. To enable LDO voltage regulator start up a pull down device 91 (d) is placed on the power PMOS gate to supply initial power to the error amplifier and bandgap reference . Once the LDO voltage regulator output has risen the start up device can be turned off to enable output voltage regulation. Miller 'pole splitting' compensation is implemented by way of capacitor C_c that connects the output voltage directly into the error amplifier bias system in such a way that C_c sits across an inverting gm stage. This has the effect of pushing the output pole out above the IMhz control bandwidth and makes the error amplifier output pole the dominant compensation pole to role the loop gain off by 20db/decade through unity gain at IMhz.

Figure 11 shows another implementation based upon an NMOS output device e.

An alternative embodiment of LDO voltage regulator uses a power NMOS device. It is to be noted that the power NMOS gate voltage should be at least several volts higher than the input supply to enable a low drop out voltage. The power NMOS gate can be driven from either a charge pump or from the peak rectified V_r voltage obtained from the resonant converter, both these sources will provide adequate gate drive voltage for low drop out voltage.

In the embodiment of the present invention shown in figure 12, the battery 116 supplies 4.2V to resonant switching regulator 126. The output circuit of regulator 126 includes a resonant tank inductor L_r 121 and resonant tank capacitor C_r 123 diode 124 and buck filter inductor L_f 119 and output capacitor C_Q 125. A stabilised and regulated voltage, in this example 2.5V, is provided across the capacitor C 125 which acts as an input voltage: to a first LDO voltage regulator 28 supplying a regulated 1.0V; to the digital core 10; to a second LDO voltage regulator 30 supplying a regulated 1.8V to the digital I/O circuit 12; and any other LDO voltage regulators as required, as indicated at 132.

Figure 13 shows total efficiency against output current for the prior art 40 and the embodiment of the present invention 42 shown in figure 12 . Figure 14 shows the relationship of operational frequency versus output load current of the resonant switching regulator.

Turning to Figures 15 to 18, as noted above it is known to use guard rings to prevent unwanted flow of minority carriers into sensitive areas of circuits with large- scale integration. However, known guard ring arrangements have limitations.

Figure 15 shows a typical known guard ring in a CMOS circuit, which uses N+ diffusion on top of NWELL . In the known arrangement of figure 16, the guard ring consists of N+ on Deep N+ which penetrates to the N+ Buried Layer NBL. The figure 16 arrangement is only possible in BiCMOS. Pure CMOS process flows do not give access to NBL or Deep N+, and thus only a relatively shallow N+ layer is available to form a guard ring, allowing significant minority carrier migration below the guard ring.

The present invention enables a much improved effect to be achieved in pure CMOS . In the embodiment of Figure 17, a guard ring 60 is formed by N+ diffusion on top of NWELL diffusion. A high voltage is applied to the N+ of the guard ring 60, which has the effect of driving the depletion region deep down into the substrate, thus providing a performance similar to the BiCMOS arrangement of Figure 16.

"High voltage" in this context means above the supply voltage, preferably at or close to the maximum permitted on the guard ring by process. In the example shown, the supply voltage Vcc is 1.0V and the voltage applied to the guard ring 60 is 2.0V. In other cases, a maximum N+/Psub voltage may be in the region of 5V and the supply voltage about 1.8V. Thus the guard ring may be held at twice the supply voltage or greater in typical examples.

The guard ring is even more effective if used in conjunction with one or more hole collecting rings 62, 64 of P+ material connected to local ground, the preferred arrangement as shown being to have one hole collecting ring on either side of the electron collecting guard ring 60. The guard ring 60 rejects holes and forces their collection by the P+ rings 62,64.

The foregoing example illustrates the guard ring feature of the present invention as applied to a CMOS structure. It may equally be applied to other semiconductor processes, such as Bipolar devices where there would be no epitaxial layer.

A particularly preferred means of providing the high voltage for the guard ring 60 is by use of a current fed charge pump circuit 66, one example of which is shown in Figure 18. The charge pump is controlled via a current source and feedback. By switching at a suitably high frequency the use of external components can be avoided. The NWELL/N+ capacitance can be used as the charge pump output capacitor. The guard rings do not require any significant current, which allows the charge pump supply to be used or other purposes , for example to power the gates of NMOS LDO voltage regulators.

Another means of providing a high voltage to the guard ring 60 is to supply it from the peak rectified V_r voltage of the resonant converter.

The foregoing guard ring arrangement is preferably used to isolate circuit blocks on the system level integrated dice. For example, one ring may be placed round the power management block, one around the digital core, one around the digital I/O, and one around the analog I/O. The supply for the N+ guard ring should be local to the circuit block concerned to avoid cross-talk between circuit blocks.

In another embodiment of the present invention shown in figure 19, the battery management circuitry is contained within the battery pack. Although described above with reference to System on Chip applications, the present invention may also be employed in other semiconductor products including nanotechnology and mechatronics .

Although described herein largely in terms of SoC or SLI chips, aspects of the invention also find application in less highly integrated circuits. In particular, the guard ring arrangement of the invention may be applied in less complex circuit chips, the resonant variable frequency DC to DC converter may be applied in less complex chips or even as a discrete device, and the combination of a resonant DC to DC converter with one or more LDO regulators may likewise be used in less complex chips or as a discrete device.

Modifications and improvements may be made to the foregoing within the scope of the present invention.

Claims

1. A solid state device of system level integration or system-on-chip which comprises, in a single semiconductor chip, a digital core, one or more input/output circuits, and an embedded power management system arranged to cooperate with an external power source.

2. A device according to claim 1 which comprises one or more digital input/output circuits and one or more analog input/output circuits.

3. A device according to claim 1 or claim 2, in which said power source is a battery, and the power management system is adapted to control battery charging.

4. A device according to any preceding claim, in which the power management system includes a plurality of voltage regulator circuits distributed across the chip.

5. A device according to claim 4, in which said voltage regulators are low drop out (LDO) voltage regulators.

6. A device according to claim 5, in which the or each LDO voltage regulator includes feedforward paths to reduce the control bandwidth.

7. A device according to claim 6, in which the feedforward paths couple into the bias system of an amplifier of the regulator.

8. A device according to any of claims 5 to 7 , in which the or each regulator includes an output speedup network.

9. A device according to any of claims 5 to 8, in which the LDO voltage regulators are supplied by a common voltage regulator interposed between the power source and the LDO voltage regulators .

10. A device according to claim 9, in which the common voltage regulator comprises a switching regulator.

11. A device according to claim 10 in which the common voltage regulator comprises a resonant switching regulator

12. A device according to claim 10 in which the common voltage regulator comprises a quasi-resonant switching regulator

13. A device according to any of claims 10 to 12, in which the switching regulator comprises a resonant tank circuit.

14. A device according to any of claims 10 to 13, in which the frequency of the switching regulator is controlled so as to reduce with reducing load.

15. A device according to claim 14, in which said frequency is controlled by a signal from one or more of the LDO voltage regulators.

16. A device according to claims 9 to 15 wherein the switching cycle of the voltage regulator is controlled by a controller which senses when the switch current has fallen to zero

17. A device according to claim 10 wherein the common voltage regulator comprises a resonant tank circuit and a plurality of switches including, a first switch which is closed to allow charge current to flow in the first half . of a cycle and a second switch which is closed to deliver energy to a capacitor when the first switch is open and when the current is at or near zero in the second half of the cycle.

18. A device according to claim 17 wherein the common voltage regulator further comprises a switch which is closed to facilitate complete discharge of the circuit when the voltage is zero.

19. A device according to any preceding claim, including one or more guard rings around selected circuits of the chip to minimise the transmission of noise.

20. A device according to claim 19 when dependent on any of claims 4 to 6, in which each of said distributed voltage regulator circuits is provided with a guard ring.

21. A device according to claim 19 or claim 20, in which the chip comprises a P-type silicon substrate having a P- epitaxial layer, and the or each guard ring comprises N+ material surrounded by an N well.

22. A device according to claim 21, in which there is provided on one or both sides of the guard ring a hole- collecting ring of P+ material.

23. A device according to any of claims 19 to 22, in which the or each guard ring is maintained at a voltage at or close to the maximum permitted by process on the guard ring.

24. A device according to claim 23, in which said voltage is about twice the supply voltage to the circuit within the guard ring.

25. A device according to claim 23 or 24, in which said voltage is supplied to the or each guard ring by a respective local source.

26. A device according to claim 25, in which said local source is a current fed charge pump.

27. A solid state device of system level integration or system-on-chip which comprises a plurality of system blocks in a single semiconductor chip, and in which at least one of said system blocks is surrounded by a guard ring maintained at a higher voltage than the voltage supply to the system block.

28. A device according to claim 27, in which the chip comprises a P-type silicon substrate, and the or each guard ring comprises N+ material surrounded by an N well.

29. A device according to claim 28, in which there is provided on one or both sides of the guard ring a hole- collecting ring of P+ material.

30. A device according to any of claims 27 to 29, in which the guard ring voltage is supplied by a local voltage source in the form of a current fed charge pump.

31. An integrated circuit which includes at least one voltage regulator in the form of a low drop out (LDO) voltage regulator; and in which the or each LDO voltage regulator comprises an amplifier and feedforward paths feeding into the bias system of the amplifier.

32. An integrated circuit according to claim 31, in which the LDO voltage regulator further comprises an output speedup network.

33. An integrated circuit comprising a power supply circuit in the form of a resonant or quasi-resonant mode DC to DC converter, and in which said converter is adapted to operate at a switching frequency which is determined by the output load current of the converter.

34. An integrated circuit according to claim 33, in which the converter includes a resonant tank having an inductor and a capacitor, and a buck filter having an inductor and a capacitor.

35. An integrated circuit according to claim 34, in which the resonant frequency is controlled by sensing zero resonant tank current after trigger.

36. An integrated circuit according to claim 34 or claim 35, in which the switching frequency is controlled by sensing the output voltage of the buck filter.

37. An integrated circuit according to claim 34 or claim 35, in which the switching frequency is controlled by feedback from a load supplied by the converter.

38. An integrated circuit comprising a power supply arrangement formed by a resonant or quasi-resonant mode DC to DC converter which supplies one or more LDO voltage regulators .

39. An integrated circuit according to claim 38, in which the DC to DC converter is as specified in any of claims 33 to 37.