WO2005020077A1 - Dual bank shared data ram for efficient pipelined video and data processing - Google Patents

Dual bank shared data ram for efficient pipelined video and data processing Download PDF

Info

Publication number
WO2005020077A1
WO2005020077A1 PCT/US2003/025238 US0325238W WO2005020077A1 WO 2005020077 A1 WO2005020077 A1 WO 2005020077A1 US 0325238 W US0325238 W US 0325238W WO 2005020077 A1 WO2005020077 A1 WO 2005020077A1
Authority
WO
WIPO (PCT)
Prior art keywords
processor
memory
switch
bank
data
Prior art date
Application number
PCT/US2003/025238
Other languages
French (fr)
Inventor
Jean-Louis Yves Diascorn
Charles Bryan Hunt
Original Assignee
Thomson Licensing S.A.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson Licensing S.A. filed Critical Thomson Licensing S.A.
Priority to PCT/US2003/025238 priority Critical patent/WO2005020077A1/en
Priority to AU2003255280A priority patent/AU2003255280A1/en
Publication of WO2005020077A1 publication Critical patent/WO2005020077A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1663—Access to shared memory
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/436—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation using parallelised computational arrangements

Definitions

  • the present invention relates to high performance multiprocessor design, and, more particularly, to dual bank shared data RAM for efficient pipelined video and data processing.
  • FIFO first-in-first-out
  • the memory elements generally include a fast memory (hereinafter referred to as a "FIFO memory"), such as a fast static RAM.
  • data exchange may also be implemented using a shared common memory.
  • the shared common memory is generally implemented using some control logic and a dedicated datapath routing logic to logically connect the respective bus structures of two processors.
  • a special mechanism such as a semaphore, may be implemented to prevent bus contentions.
  • FIFO Like the FIFO, data exchange between processors with a shared common memory requires at least one read and one write instruction from the shared common memory. Additional steps to write or read from the processors may also be necessary.
  • the FIFO and shared common memory methods have several drawbacks. Each transfer of data from one processor to another processor requires at least two actions: a write to the FIFO or shared common memory and a read from the FIFO or shared common memory. Furthermore, if data needs to be processed, a processor may need an extra step to write the data to the processor RAM. These extra steps are time-consuming and may be particularly troublesome in high performance designs where fast data access speeds are crucial. Therefore, a need exists for an apparatus that provides efficient data exchange between processors. The data should be transferred fast enough to support a high performance design, such as needed for video processing. Duplication of data among processors should also be avoided.
  • the present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
  • a dual bank memory device includes a first memory; a second memory; a first switch that operatively couples the first memory to a first processor, wherein the first switch is capable of operatively coupling the second memory to the first processor, wherein the first switch directs data and address information from the first processor to the first memory and directs data information from the first memory to the first processor, and wherein the first switch is capable of directing data and address information from the first processor to the second memory and directing data information from the second memory to the first processor; a second switch that operatively couples the second memory to a second processor, wherein the second switch is capable of operatively coupling the first memory to the second processor, wherein the second switch directs data and address information from the second processor to the second memory and directs data information from the second memory to the second processor, and wherein the second switch is capable of directing data and address information from the second processor to the first memory and directs data information from the first memory
  • a method of acquiring data from a dual bank shared memory device includes transmitting address information from a first processor to a first memory bank, transmitting address information from a second processor to a second memory bank, transmitting data information from a first processor to a first memory bank, transmitting data information from a second processor to a second memory bank, transmitting data information from a first processor to a first memory bank, transmitting data information from a second processor to a second memory bank, and swapping the first memory and the second memory.
  • a multiprocessor architecture is provided.
  • the multiprocessor architecture comprises a first processor; a second processor; one or more main memories operatively coupled to the first processor and the second processor; one or more cache memories coupled to the first processor and the second processor; a first memory bank; a second memory bank; a first switch that operatively couples the first memory bank to a first processor, wherein the first switch is capable of operatively coupling the second memory bank to the first processor, wherein the first switch directs data and address information from the first processor to the first memory bank and directs data information from the first memory bank to the first processor, and wherein the first switch is capable of directing data and address information from the first processor to the second memory bank and directing data information from the second memory bank to the first processor; a second switch operatively couples the second memory bank to a second processor, wherein the second switch is capable of operatively coupling the first memory bank to the second processor, wherein the second switch directs data and address information from the second processor to the second memory bank and directs data information from the second memory bank to the second processor, and wherein
  • FIG. 1 depicts a memory configuration of a multiprocessor architecture in accordance with one embodiment of the present invention
  • FIG. 2 depicts an alternate memory configuration of the multiprocessor architecture of FIG. 1
  • FIG. 3 depicts, in further detail, the connection of the DBSM to the processors, as described in FIG. 1
  • FIG. 4 depicts, in further detail, a schematic diagram of the DBSM architecture, as described in FIG. 1 ;
  • the multiprocessor architecture 100 comprises a first processor 105 and a second processor 110 sharing a main memory 1 15.
  • main memory 1 15 is typically implemented using slower, cheaper dynamic random access memory (“DRAM”) devices.
  • the main memory 115 may include random access memory (“RAM”), read-only memory (“ROM”), or both.
  • RAM random access memory
  • ROM read-only memory
  • a computer may boot up using the contents of the ROM and thereafter use the RAM for temporary storage of data associated with applications and the operating system.
  • main memory it is contemplated that it may include any combination of the ROM and RAM.
  • the first processor 105 and second processor 110 (collectively known as “processors”) each comprise a bifurcated level 1 ("LI”) instruction cache memory 120 and data cache memory 125 (collectively known as a "cache").
  • L2 level 2
  • L2 level 2
  • the multiprocessor architecture 100 may include one or more cache memories for further reducing latency between the main memory 1 15 and the processors 105, 110.
  • the cache 120, 125 is implemented using faster random access memory devices, such as static random access memory devices ("SRAMs") so that accessing the cache 120, 125 takes much less time to complete than to access main memory. SRAMs typically require greater number of devices per bit of information stored, and thus are more expensive than
  • the cache 120 In other embodiments, the cache 120,
  • a dual bank shared memory 130 is shown operatively coupled to the first processor 105 and the second processor 110.
  • the DBSM is preferably implemented using a fast memory, such as the memory used for the cache 120, 125.
  • additional DBSM memories may be coupled to additional processors in a multiprocessor architecture.
  • a second DBSM (not shown) may be coupled to the second processor 110 and a third processor (not shown).
  • the multiprocessor architecture 100 of Figure 1 may be implemented as a processor ring 200, as illustrated in Figure 2.
  • each processor 205, 210, 215, 220 is coupled to each other via four respective DBSMs 130, 135, 140, 145.
  • each processor 205, 210, 215, 220 may be operatively coupled to its own main memory or a shared memory and one or more cache memories, similar to the configuration described for Figure 1.
  • FIG 3 an exemplary embodiment of the connection 300 between the processors 105, 110 and the DBSM 130 in accordance with the present invention is illustrated.
  • the connection between the DBSM 130 and the processors 105, 1 10 include a unidirectional address bus 305 for specifying a data read/write address and a bidirectional data bus 310 for transmitting and receiving data.
  • An interrupt signal (described in greater detail in Figure 4) is generated by the DBSM 130 and transmitted to the processors 105, 110 via their respective interrupt lines 315, 320. It is understood that any of a variety signals known to those skilled in the art may be used in place of interrupts.
  • FIG 4 a schematic diagram of the DBSM 130 in accordance with the present invention is illustrated.
  • the DBSM 130 comprises a first memory bank 405 and a second memory bank 410. On one side of the first memory bank 405 is a first multiplexer/switch 415, and on the other side is a second multiplexer/switch 420.
  • the first multiplexer/switch 415 is coupled to the first processor 105 (not shown in Fig.
  • the second multiplexer/switch 420 is coupled to the second processor 110 (not shown in Fig. 4). As illustrated, the first multiplexer/switch 415 directs address and data information via the unidirectional address bus 305 and the bidirectional data bus 310, respectively, to and from the first memory bank 405. The second multiplexer/switch 420 directs address and data information via the unidirectional address bus 305 and bidirectional data bus 310, respectively, to and from the second memory bank 410.
  • the first multiplexer/switch 415 and the second multiplexer/switch 420 are commonly known in the art and may be built using standard logical gates.
  • the switches 415, 420 may be implemented using a combination of one or more standard cells, such as the 74LS 138, the 74LS 153, and the like.
  • a control logic 425 directs the switches 415, 420 to send data and address information to either the first memory bank 405 or the second memory bank 410.
  • the first multiplexer/switch 415 directs address and data information to and from the first memory bank 405
  • the second multiplexer/switch 420 directs address and data information to and from the second memory bank 410.
  • the control logic 425 may "swap" memory banks by activating the switches 415, 420 such that the first multiplexer/switch 415 directs address and data information to and from the second memory bank 410, and the second multiplexer/switch 420 directs address and data information to and from first memory bank 405.
  • the DBSM 130 further comprises a first processor flag 430 and a second processor flag 435.
  • the first processor flag 430 indicates whether the first processor 105 is done using its associated memory bank. As illustrated, the associated memory bank for the first processor 105 is the first memory bank 405.
  • the second processor flag 435 indicates whether the second processor 110 is done using its associated memory bank. As illustrated, the associated memory bank for the second processor 1 10 is the second memory bank 410.
  • the first processor flag 430 receives a first signal 440 from a first address and data decoding logic 445
  • the second processor flag 435 receives a second signal 450 from a second address and data decoding logic 455.
  • the first signal 440 notifies the first processor flag 430 whether the first processor 105 is done using its associated memory bank.
  • the second signal 450 notifies the second processor flag 435 whether the second processor 110 is done using its associated memory bank.
  • the first address and data decoding logic 445 and the second address and data decoding logic 455 receive address and data information from the first processor 105 and second processor 1 10, respectively, via the unidirectional address bus 305 and the bidirectional data bus 310.
  • the address and data decoding logics 445, 455 notify the first and second processor flags 435, 440 that the processors 105, 1 10 are done using their associated memory banks. It is understood that any of a variety of signals known to those skilled in the art may be used to notify the address and data decoding logics 445, 455 that the processors 105, 1 10 are done. For example, as illustrated in Figure 4, the address and data decoding logics 445, 455 sends a signal if they receive a particular address and a particular data value from the processors 105, 110, respectively.
  • both flags 430, 435 indicate that both processors 105, 110 are done using their associated memory banks
  • the control logic 425 performs three tasks.
  • the control logic 425 instructs the switches 415, 420 to swap memory banks, sends a reset signal 460 to the processor flags 430, 435 resetting them to their original configuration, and sends an interrupt signal 465 to both processors 105, 1 10 indicating that the processors 105, 1 10 can start using the DBSM.
  • any of a variety of signals known to those skilled in the art may be used in place of interrupts.

Abstract

The present invention provides a dual bank shared data RAM (130) for efficient pipelined multiprocessor video (205, 210) and data processor. The dual bank memory device comprises two fast memories: a first memory (405) and a second memory (410). A first switch (415) operatively couples to the first memory (405) to a first processor (205). A second switch (420) operatively couples the second memory (410) to a second processor (210). The first switch (415) directs data and address information from the first processor (205) to the first memory (405) and directs data information from the first memory (405) to the first processor (205). The second switch (420) directs data and address information from the second processor (210) to the second memory (410) and directs data information from the second memory (410) to the second processor (210). The dual bank memory device further comprises a control logic (425). The control logic is operatively coupled to the first switch (415) and the second switch (420).

Description

DUAL BANK SHARED DATA RAM FOR EFFICIENT PIPELINED VIDEO AND DATA PROCESSING
BACKGROUND OF THE INVENTION
1. Field of the Invention The present invention relates to high performance multiprocessor design, and, more particularly, to dual bank shared data RAM for efficient pipelined video and data processing.
2. Description of the Related Art The performance of modern multiprocessor computer systems which may be configured in a variety of multiprocessor architectures is frequently limited by the data exchange delays between these processors. Data exchange delays are particularly troublesome in high performance applications, such as those needed for video and data processing, where processing speed is crucial. Even the most powerful processors can process data only as fast as the data can be accessed. Traditionally, data exchange has "been implemented in two ways. In one method, a FIFO (first-in-first-out) is used for individual processors having their own memories. Traditionally, the FIFO includes both logic elements and memory elements. The memory elements generally include a fast memory (hereinafter referred to as a "FIFO memory"), such as a fast static RAM. Suppose data needs to be transferred from a first processor to a second processor. In the FIFO method, the first processor will begin writing data to the FIFO memory. As the FIFO memory fills up, the logic elements of the FIFO generate an interrupt to the second processor and the second processor will begin reading data from the FIFO. In some instances, an additional step may be necessary to write the data to the second processor for further processing. Data exchange may also be implemented using a shared common memory. The shared common memory is generally implemented using some control logic and a dedicated datapath routing logic to logically connect the respective bus structures of two processors. A special mechanism, such as a semaphore, may be implemented to prevent bus contentions. Like the FIFO, data exchange between processors with a shared common memory requires at least one read and one write instruction from the shared common memory. Additional steps to write or read from the processors may also be necessary. The FIFO and shared common memory methods have several drawbacks. Each transfer of data from one processor to another processor requires at least two actions: a write to the FIFO or shared common memory and a read from the FIFO or shared common memory. Furthermore, if data needs to be processed, a processor may need an extra step to write the data to the processor RAM. These extra steps are time-consuming and may be particularly troublesome in high performance designs where fast data access speeds are crucial. Therefore, a need exists for an apparatus that provides efficient data exchange between processors. The data should be transferred fast enough to support a high performance design, such as needed for video processing. Duplication of data among processors should also be avoided. The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION In one aspect of the present invention, a dual bank memory device is provided. The dual bank memory device includes a first memory; a second memory; a first switch that operatively couples the first memory to a first processor, wherein the first switch is capable of operatively coupling the second memory to the first processor, wherein the first switch directs data and address information from the first processor to the first memory and directs data information from the first memory to the first processor, and wherein the first switch is capable of directing data and address information from the first processor to the second memory and directing data information from the second memory to the first processor; a second switch that operatively couples the second memory to a second processor, wherein the second switch is capable of operatively coupling the first memory to the second processor, wherein the second switch directs data and address information from the second processor to the second memory and directs data information from the second memory to the second processor, and wherein the second switch is capable of directing data and address information from the second processor to the first memory and directs data information from the first memory to the second processor; and a control logic operatively coupled to the first switch and the second switch, wherein the control logic instructs the first switch and the second switch to swap memories. In another aspect of the present invention, a method of acquiring data from a dual bank shared memory device is provided. The method includes transmitting address information from a first processor to a first memory bank, transmitting address information from a second processor to a second memory bank, transmitting data information from a first processor to a first memory bank, transmitting data information from a second processor to a second memory bank, transmitting data information from a first processor to a first memory bank, transmitting data information from a second processor to a second memory bank, and swapping the first memory and the second memory. In yet another aspect of the present invention, a multiprocessor architecture is provided. The multiprocessor architecture comprises a first processor; a second processor; one or more main memories operatively coupled to the first processor and the second processor; one or more cache memories coupled to the first processor and the second processor; a first memory bank; a second memory bank; a first switch that operatively couples the first memory bank to a first processor, wherein the first switch is capable of operatively coupling the second memory bank to the first processor, wherein the first switch directs data and address information from the first processor to the first memory bank and directs data information from the first memory bank to the first processor, and wherein the first switch is capable of directing data and address information from the first processor to the second memory bank and directing data information from the second memory bank to the first processor; a second switch operatively couples the second memory bank to a second processor, wherein the second switch is capable of operatively coupling the first memory bank to the second processor, wherein the second switch directs data and address information from the second processor to the second memory bank and directs data information from the second memory bank to the second processor, and wherein the second switch is capable of directing data and address information from the second processor to the first memory bank and directing data information from the first memory bank to the second processor; and a control logic operatively coupled to the first switch and the second switch, wherein the control logic instructs the first switch and the second switch to swap memories banks. These and other aspects, features and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments, which is to be read in connection with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS The invention may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which: FIG. 1 depicts a memory configuration of a multiprocessor architecture in accordance with one embodiment of the present invention; FIG. 2 depicts an alternate memory configuration of the multiprocessor architecture of FIG. 1; FIG. 3 depicts, in further detail, the connection of the DBSM to the processors, as described in FIG. 1 ; FIG. 4 depicts, in further detail, a schematic diagram of the DBSM architecture, as described in FIG. 1 ;
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS Referring now to Figure 1 , an exemplary embodiment of a memory configuration of a multiprocessor architecture 100 in accordance with the present invention is illustrated. As shown, the multiprocessor architecture 100 comprises a first processor 105 and a second processor 110 sharing a main memory 1 15. Although only two processors are shown in Figure 1 , it is known to those skilled in the art that a typical multiprocessor architecture may include any number of processors depending on the implementation. It is also understood that one or more of the processors may comprise its own memory without sharing the main memory 115. The main memory 1 15 is typically implemented using slower, cheaper dynamic random access memory ("DRAM") devices. The main memory 115 may include random access memory ("RAM"), read-only memory ("ROM"), or both. For example, a computer may boot up using the contents of the ROM and thereafter use the RAM for temporary storage of data associated with applications and the operating system. Whenever "main memory" is mentioned, it is contemplated that it may include any combination of the ROM and RAM. The first processor 105 and second processor 110 (collectively known as "processors") each comprise a bifurcated level 1 ("LI") instruction cache memory 120 and data cache memory 125 (collectively known as a "cache"). Although not illustrated in Figure 1, in other embodiments, a level 2 ("L2") cache may be implemented on the processors 105, 110 as necessary. It is understood that the multiprocessor architecture 100 may include one or more cache memories for further reducing latency between the main memory 1 15 and the processors 105, 110. The cache 120, 125 is implemented using faster random access memory devices, such as static random access memory devices ("SRAMs") so that accessing the cache 120, 125 takes much less time to complete than to access main memory. SRAMs typically require greater number of devices per bit of information stored, and thus are more expensive than
DRAM. To further reduce the memory latency period, in other embodiments, the cache 120,
125 may be located on the same chip as the processors 105, 110. A dual bank shared memory (hereinafter referred to as a "DBSM") 130 is shown operatively coupled to the first processor 105 and the second processor 110. The DBSM is preferably implemented using a fast memory, such as the memory used for the cache 120, 125. It is understood that additional DBSM memories may be coupled to additional processors in a multiprocessor architecture. For example, referring to Figure 1, a second DBSM (not shown) may be coupled to the second processor 110 and a third processor (not shown). Furthermore, in an alternate embodiment, the multiprocessor architecture 100 of Figure 1 may be implemented as a processor ring 200, as illustrated in Figure 2. As shown in Figure 2, four processors 205, 210, 215, 220 are coupled to each other via four respective DBSMs 130, 135, 140, 145. Although not shown, each processor 205, 210, 215, 220 may be operatively coupled to its own main memory or a shared memory and one or more cache memories, similar to the configuration described for Figure 1. Referring now to Figure 3, an exemplary embodiment of the connection 300 between the processors 105, 110 and the DBSM 130 in accordance with the present invention is illustrated. The connection between the DBSM 130 and the processors 105, 1 10 include a unidirectional address bus 305 for specifying a data read/write address and a bidirectional data bus 310 for transmitting and receiving data. An interrupt signal (described in greater detail in Figure 4) is generated by the DBSM 130 and transmitted to the processors 105, 110 via their respective interrupt lines 315, 320. It is understood that any of a variety signals known to those skilled in the art may be used in place of interrupts. Referring now to Figure 4, a schematic diagram of the DBSM 130 in accordance with the present invention is illustrated. The DBSM 130 comprises a first memory bank 405 and a second memory bank 410. On one side of the first memory bank 405 is a first multiplexer/switch 415, and on the other side is a second multiplexer/switch 420. The first multiplexer/switch 415 is coupled to the first processor 105 (not shown in Fig. 4) via the address bus 305 and the data bus 310. The second multiplexer/switch 420 is coupled to the second processor 110 (not shown in Fig. 4). As illustrated, the first multiplexer/switch 415 directs address and data information via the unidirectional address bus 305 and the bidirectional data bus 310, respectively, to and from the first memory bank 405. The second multiplexer/switch 420 directs address and data information via the unidirectional address bus 305 and bidirectional data bus 310, respectively, to and from the second memory bank 410. The first multiplexer/switch 415 and the second multiplexer/switch 420 (collectively referred to as "switches) are commonly known in the art and may be built using standard logical gates. In alternate embodiments, the switches 415, 420 may be implemented using a combination of one or more standard cells, such as the 74LS 138, the 74LS 153, and the like. A control logic 425 directs the switches 415, 420 to send data and address information to either the first memory bank 405 or the second memory bank 410. As illustrated, the first multiplexer/switch 415 directs address and data information to and from the first memory bank 405, and the second multiplexer/switch 420 directs address and data information to and from the second memory bank 410. The control logic 425 may "swap" memory banks by activating the switches 415, 420 such that the first multiplexer/switch 415 directs address and data information to and from the second memory bank 410, and the second multiplexer/switch 420 directs address and data information to and from first memory bank 405. The DBSM 130 further comprises a first processor flag 430 and a second processor flag 435. The first processor flag 430 indicates whether the first processor 105 is done using its associated memory bank. As illustrated, the associated memory bank for the first processor 105 is the first memory bank 405. The second processor flag 435 indicates whether the second processor 110 is done using its associated memory bank. As illustrated, the associated memory bank for the second processor 1 10 is the second memory bank 410. The first processor flag 430 receives a first signal 440 from a first address and data decoding logic 445, and the second processor flag 435 receives a second signal 450 from a second address and data decoding logic 455. The first signal 440 notifies the first processor flag 430 whether the first processor 105 is done using its associated memory bank. The second signal 450 notifies the second processor flag 435 whether the second processor 110 is done using its associated memory bank. The first address and data decoding logic 445 and the second address and data decoding logic 455 receive address and data information from the first processor 105 and second processor 1 10, respectively, via the unidirectional address bus 305 and the bidirectional data bus 310. When the first address and data decoding logic 445 and the second address and data decoding logic 455 receive a proper signal from the first processor 105 and the second processor 110, respectively, the address and data decoding logics 445, 455 notify the first and second processor flags 435, 440 that the processors 105, 1 10 are done using their associated memory banks. It is understood that any of a variety of signals known to those skilled in the art may be used to notify the address and data decoding logics 445, 455 that the processors 105, 1 10 are done. For example, as illustrated in Figure 4, the address and data decoding logics 445, 455 sends a signal if they receive a particular address and a particular data value from the processors 105, 110, respectively. Once both flags 430, 435 indicate that both processors 105, 110 are done using their associated memory banks, the control logic 425 performs three tasks. The control logic 425 instructs the switches 415, 420 to swap memory banks, sends a reset signal 460 to the processor flags 430, 435 resetting them to their original configuration, and sends an interrupt signal 465 to both processors 105, 1 10 indicating that the processors 105, 1 10 can start using the DBSM. As mentioned previously, it is understood that any of a variety of signals known to those skilled in the art may be used in place of interrupts. The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below.

Claims

WHAT IS CLAIMED IS: 1. A dual bank memory device comprising: a first memory; a second memory; a first switch that operatively couples the first memory to a first processor, wherein the first switch is capable of operatively coupling the second memory to the first processor, wherein the first switch directs data and address information from the first processor to the first memory and directs data information from the first memory to the first processor, and wherein the first switch is capable of directing data and address information from the first processor to the second memory and directing data information from the second memory to the first processor; a second switch that operatively couples the second memory to a second processor, wherein the second switch is capable of operatively coupling the first memory to the second processor, wherein the second switch directs data and address information from the second processor to the second memory and directs data information from the second memory to the second processor, and wherein the second switch is capable of directing data and address information from the second processor to the first memory and directs data information from the first memory to the second processor; and a control logic operatively coupled to the first switch and the second switch, wherein the control logic instructs the first switch and the second switch to swap memories.
2. The dual bank memory device of claim 1, wherein the first memory comprises at least one of a RAM or a ROM.
3. The dual memory bank memory device of claim 1, wherein the second memory comprises at least one of a RAM or a ROM.
4. The dual bank memory device of claim 1 , wherein the first switch comprises a one or more standard cells.
5. The dual bank memory device of claim 1, wherein the second switch comprises one or more standard cells.
6. The dual bank memory device of claim 1, wherein the address information is transmitted and received via an address bus.
7. The dual bank memory device of claim 6, wherein the address bus is a unidirectional address bus.
8. The dual bank memory device of claim 1 , wherein the data information is transmitted and received via a data bus.
9. The dual bank memory device of claim 8, wherein the data bus is a bidirectional address bus.
10. The dual bank memory device of claim 1 , further comprising: a first processor flag operatively coupled to a first processor and a first address and data decoder, wherein the first address and data decoder is operatively coupled to the control logic; and a second processor flag operatively coupled to a second processor and a second address and data decoder, wherein the second address and data decoder is operatively coupled to the control logic.
11. The dual bank memory device of claim 10, wherein the first address and data decoder receives address and data information from the first processor.
12. The dual bank memory device of claim 10, wherein the second address and data decoder receives address and data information from the second processor.
13. The dual bank memory device of claim 1, wherein the control logic generates a signal to the first processor and the second processor.
14. The dual bank memory device of claim 13, wherein the signal is an interrupt signal.
15. A method of acquiring data from a dual bank shared memory device comprising: transmitting address information from a first processor to a first memory bank; transmitting address information from a second processor to a second memory bank; transmitting data information from a first processor to a first memory bank; transmitting data information from a second processor to a second memory bank; transmitting data information from a first processor to a first memory bank; transmitting data information from a second processor to a second memory bank; and swapping the first memory bank and the second memory bank.
16. A multiprocessor architecture, comprising: a first processor; a second processor; one or more main memories operatively coupled to the first processor and • the second processor; one or more cache memories coupled to the first processor and the second processor; a first memory bank; a second memory bank; a first switch that operatively couples the first memory bank to a first processor, wherein the first switch is capable of operatively coupling the second memory bank to the first processor, wherein the first switch directs data and address information from the first processor to the first memory bank and directs data information from the first memory bank to the first processor, and wherein the first switch is capable of directing data and address information from the first processor to the second memory bank and directing data information from the second memory bank to the first processor; a second switch operatively couples the second memory bank to a second processor, wherein the second switch is capable of operatively coupling the first memory bank to the second processor, wherein the second switch directs data and address information from the second processor to the second memory bank and directs data information from the second memory bank to the second processor, and wherein the second switch is capable of directing data and address information from the second processor to the first memory bank and directing data information from the first memory bank to the second processor; and a control logic operatively coupled to the first switch and the second switch, wherein the control logic instructs the first switch and the second switch to swap memories banks.
17. The multiprocessor architecture of claim 16, wherein the one or more cache memories includes an LI cache.
18. The multiprocessor architecture of claim 17, wherein the LI cache includes an instruction cache memory and a data cache memory.
19. The multiprocessor architecture of claim 16, wherein at least one of the one or more main memories is a shared main memory.
PCT/US2003/025238 2003-08-13 2003-08-13 Dual bank shared data ram for efficient pipelined video and data processing WO2005020077A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/US2003/025238 WO2005020077A1 (en) 2003-08-13 2003-08-13 Dual bank shared data ram for efficient pipelined video and data processing
AU2003255280A AU2003255280A1 (en) 2003-08-13 2003-08-13 Dual bank shared data ram for efficient pipelined video and data processing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2003/025238 WO2005020077A1 (en) 2003-08-13 2003-08-13 Dual bank shared data ram for efficient pipelined video and data processing

Publications (1)

Publication Number Publication Date
WO2005020077A1 true WO2005020077A1 (en) 2005-03-03

Family

ID=34215305

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/025238 WO2005020077A1 (en) 2003-08-13 2003-08-13 Dual bank shared data ram for efficient pipelined video and data processing

Country Status (2)

Country Link
AU (1) AU2003255280A1 (en)
WO (1) WO2005020077A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7808560B2 (en) 2005-06-03 2010-10-05 Samsung Electronics Co., Ltd. Video processing apparatus and data processing method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5680641A (en) * 1995-08-16 1997-10-21 Sharp Microelectronics Technology, Inc. Multiple register bank system for concurrent I/O operation in a CPU datapath
US5845322A (en) * 1996-09-17 1998-12-01 Vlsi Technology, Inc. Modular scalable multi-processor architecture
US6029242A (en) * 1995-08-16 2000-02-22 Sharp Electronics Corporation Data processing system using a shared register bank and a plurality of processors

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5680641A (en) * 1995-08-16 1997-10-21 Sharp Microelectronics Technology, Inc. Multiple register bank system for concurrent I/O operation in a CPU datapath
US6029242A (en) * 1995-08-16 2000-02-22 Sharp Electronics Corporation Data processing system using a shared register bank and a plurality of processors
US5845322A (en) * 1996-09-17 1998-12-01 Vlsi Technology, Inc. Modular scalable multi-processor architecture

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7808560B2 (en) 2005-06-03 2010-10-05 Samsung Electronics Co., Ltd. Video processing apparatus and data processing method

Also Published As

Publication number Publication date
AU2003255280A1 (en) 2005-03-10

Similar Documents

Publication Publication Date Title
CA2043493C (en) Hierarchical integrated circuit cache memory
KR100244841B1 (en) High-speed, multiple-port, interleaved cache with arbitration of multiple access addresses
JP3065736B2 (en) Semiconductor storage device
AU640813B2 (en) A data processing system including a memory controller for direct or interleave memory accessing
US6151658A (en) Write-buffer FIFO architecture with random access snooping capability
JP2509766B2 (en) Cache memory exchange protocol
US20070255872A1 (en) Bus system and semiconductor integrated circuit
US6223260B1 (en) Multi-bus data processing system in which all data words in high level cache memories have any one of four states and all data words in low level cache memories have any one of three states
KR20010013743A (en) Method and system for storing and processing multiple memory addresses
US7899940B2 (en) Servicing commands
US4930106A (en) Dual cache RAM for rapid invalidation
JP2000512406A (en) Method and apparatus for caching system management mode information along with other information
JPH11203192A (en) Parallel processor and arithmetic processing method
EP0875030A2 (en) Multi-port cache memory with address conflict detection
JPH0812635B2 (en) Dynamically relocated memory bank queue
US5359557A (en) Dual-port array with storage redundancy having a cross-write operation
US7536516B2 (en) Shared memory device
US5185879A (en) Cache system and control method therefor
US20060294327A1 (en) Method, apparatus and system for optimizing interleaving between requests from the same stream
WO2005020077A1 (en) Dual bank shared data ram for efficient pipelined video and data processing
US7472212B2 (en) Multi CPU system
JP2813182B2 (en) Multiprocessor computer multifunction device
US6484238B1 (en) Apparatus and method for detecting snoop hits on victim lines issued to a higher level cache
JP4726187B2 (en) Semiconductor integrated circuit
JPH0916468A (en) Memory access system

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP