WO2005017869A1

WO2005017869A1 - Display device having reduced power consumption

Info

Publication number: WO2005017869A1
Application number: PCT/IB2004/051411
Authority: WO
Inventors: Andy Catalin Negoi; Bernard Pilloud
Original assignee: Koninklijke Philips Electronics N. V.
Priority date: 2003-08-18
Filing date: 2004-08-06
Publication date: 2005-02-24

Abstract

The present invention concerns generally passive matrix displays, in particular a device comprising a display arrangement (1) and a display driver circuit (2). The display arrangement (1) comprises a liquid crystal material between a first substrate provided with row electrodes (7) and a second substrate provided with column electrodes (6), in which overlapping parts of the row and column electrodes define pixels (8). The display driver circuit (2) comprises means (5) for driving the column electrodes (6) and means (4) for driving the row electrodes (7). The row electrodes (7) supply groups of p rows (p>=2) with row selection voltage levels (V3, VC, MV3) for selecting rows and the column voltage levels (V2, V1, VC, MV1, MV2) are provided by means (5) for driving the column electrodes (6). The column voltage levels (V2, V1, VC, MV1, MV2) to be supplied to the column electrodes (6) are selectable from p+l different column voltage levels (V2, V1, VC, MV1, MV2) depending on the image data to be displayed, wherein the column voltage levels (V2, V1, VC, MV1, MV2) are symmetrically distributed around a middle voltage level (VC). To provide a display device having a low power consumption it is proposed to connect the middle voltage level (VC) in dependency on a deviation from a predetermined value of the middle voltage level (VC) with a higher (Vsupplyl) or a lower voltage potential (VSS) until the predetermined value of the middle voltage level (VC) is reached or the middle voltage level (VC) stays within a tolerance range.

Description

Display device having reduced power consumption

The present invention concerns generally passive matrix displays, in particular a display device driven with the Multiple Row Addressing technique, wherein the display device comprises a display arrangement and a display driver circuit, the display arrangement comprises a liquid crystal material between a first substrate provided with row electrodes and a second substrate provided with column electrodes, in which overlapping parts of the row and column electrodes define pixels, and the display driver circuit comprises means for driving the column electrodes and means for driving the row electrodes; wherein the row electrodes supply groups of p rows (p>2) with row selection voltage levels for selecting rows and wherein the column voltage levels are provided by means for driving the column electrodes, the column voltage levels to be supplied to the column electrodes are selectable from p+1 different column voltage levels depending on the image data to be displayed; the column voltage levels are symmetrically distributed around a middle voltage level. The invention further concerns a method for driving the column electrodes of a display device with columns and rows, wherein at least p>2 rows are driven simultaneously and the column voltages to be supplied to the column electrodes are generated by a column voltage level generator in dependency on the image data to be displayed, which is generating p+1 different column voltage levels, wherein the column voltage levels are distributed around a middle voltage. The display technique will play an increasingly important role in the information and communication technique in the years to come. Being an interface between humans and the digital world, the display device is of crucial importance for the acceptance of contemporary information systems. Notably portable apparatus such as, for example, notebooks, telephones, digital cameras and personal digital assistants cannot be realized without utilizing displays. The passive matrix LCD technology is a very commonly used display technology; it is used, for example in PDA's and in mobile telephones. Passive matrix displays are usually based on the (S)TN (Super Twisted Nematic) effect. A passive matrix LCD consists of a number of substrates. The display is subdivided in the form of a matrix of rows and columns. The row electrodes and column electrodes are arranged on respective substrates and form a grid. A layer with liquid crystals is provided between said substrates. The intersections of these electrodes form pixels. These electrodes are supplied with voltages that orient the liquid crystal molecules of the driven pixels in an appropriate direction so that the driven pixel appears in a different brightness. Since the size of the displays becomes larger, the significance of the power consumption of the passive matrix LCDs increases all the time. Because such passive matrix displays are often used in portable apparatus, it is particularly important to realize low power consumption. In general a row electrode of passive matrix display devices is selected or activated by a row selection voltage for a row selection time slot, whereas the image data to be displayed are supplied via the column electrodes. There are different schemes for driving display devices. The most common driving scheme is the so called Alt & Pleshko driving scheme. Another more recent driving scheme is the so called multiple row addressing scheme (MRA). Here a group of p rows is simultaneously driven and the encoded image data is applied to the columns. This MRA technique enables a very good optical performance to be achieved in combination with low power consumption. According to said MRA technique a number of p rows are simultaneously driven. A set of orthogonal functions is then applied to the p simultaneously driven rows. A function for the column voltage for driving the corresponding column is calculated depending on said set of orthogonal functions and the image data to be displayed using a calculation rule. By using this calculation rule for driving the column, a calculated column voltage is selected -from a plurality of column voltage levels, said selected column voltage level being applied to the corresponding column so that the corresponding pixels are switched to a state depending on the image data that is supplied f om a memory. The Multiple Row Addressing technique has established itself as the method of choice to drive passive displays for high resolution e.g. more than 68 rows. In this MRA method, the display rows are driven with three equidistant voltage levels which represents the orthogonal functions and the columns with p+1 equidistant voltage levels, e.g. 6N, 4.5V, 3N, 1.5N, ON in a case p=4, whereas p is the number of rows selected simultaneously. The method of driving the voltages is symmetric and the rows and the columns share the middle voltage level called VC. The rows are used for selection and the columns carry the information to be displayed. Architectures used in the prior art use buffers for driving the column voltage levels. However the using of buffers in the column driver means that the buffers try to keep the voltage level on the driven outputs constant. To keep the voltage level constant they consume current all the time one take charge rom the output capacitor to the display. Also in the case when charge is brought f om the display to the output capacitor, the buffer discharges the capacitor and the charge is lost to ground. The amount of charge which gets lost is very significant.

Therefore it is an object of the present invention to provide a display device having lower power consumption with constant optical performance. This object will be solved by the features of the independent claims. The invention is based on the though, that the middle voltage level is sourcing and sinking the sum of the positive and the sum of the negative column level currents, which is very critical for a low power system, but the average is zero and this is used in the present invention. This is only possible, because of the symmetry of the column voltage levels. Because of that it is proved in practice that this middle voltage level has also the particularity to be relatively insensitive to a short-time DC inaccuracy, this means that it can vary by several percents up or down the ideal value for a short period without having any observable effect on the display. This means the middle voltage level has not to be as exact as the other column voltage levels. So the most sensitive column voltage levels are the column voltage levels directly below and above the middle voltage level VI and MV1, even lOmV deviation from the ideal value can give differences in contrast, and also the column voltage levels V2 and MV2 levels have to be within 40mV tolerance. A deviation of a few mV in VI, MV1, of a few tens of mV in V2 and MV2 and about 300mV in the middle voltage level do not have any impact on the quality of the displayed image, if this deviation is for a short time and is recovered by the charge brought from the display. As the middle voltage level can vary without optical quality degradation by more than 300mV over several row selection slots, another driving techniques for this middle voltage level could be used instead of using buffers trying to correct the voltage at the output continuously. The average current on this middle voltage level in time is zero because the driving method is symmetrical, so instantaneously the level could go around the middle voltage by the charge brought from and taken by the display itself. If everything is in a steady state, there would be no need to drive the capacitor at the output of the middle voltage level at all. Because in a startup phase of the driver circuit there is a need to charge the middle voltage level quickly and because there could be also an image that require to act on the middle voltage level to prevent to increase or discharge too much, which is statistically very seldom, the middle voltage level has to be controlled. Therefore it is proposed to drive the middle voltage level without using a buffer. The middle voltage level will be connected to a higher or a lower voltage potential in dependency on a deviation from a predetermined value of the middle voltage level until the predetermined value of the middle voltage level is reached or the current value of the middle voltage level stays within a range of tolerance. The result is a reduced current consumption of the whole LCD module, consisting of a display and a display driver, in a proportion of almost 50% (theoretic value) in the case of a heavy load pattern. In a heavy load pattern all columns have the same information (horizontal stripes), with p rows white and p rows black repeated. A checkerboard with the size of p pixels is also a heavy load pattern. The field of application of this inventive architecture of column voltage level generation is any column driver means using Multiple Row Addressing (of Multiple Line Selection) for passive grayscale or color liquid crystal displays or any other application needing multiple voltage levels at different current loads, obtained with a voltage multiplier from a low voltage input, e.g. from a battery operated devices, and buffers for the column voltage levels. The column voltage levels generation circuitry is part of the driver circuit and provides the high voltages necessary to drive the LCD cell. In a preferred embodiment of the invention the column voltage levels below and above the middle voltage are driven by using buffers. As stated above the column voltage levels around the middle voltage level are very sensitive, so the required accuracy can be provided only by using buffers. A buffer is an operational amplifier (OP-AMP) mounted in unity gain schematic having an inverting input directly connected to the output, hi general the function of a buffer is to take power from the power supply line and keep the output signal to a value defined by the input. In a further preferred embodiment of the invention the means for driving the column electrodes creating a plurality of partial voltages levels using a voltage divider unit, wherein the partial voltages levels are supplied to buffers for driving the column voltage levels below and above the middle voltage level. In a further preferred embodiment of the invention four threshold values are used for controlling the middle voltage level, wherein if the current value of the middle voltage is below a first threshold value, the middle voltage is connected to a power supply voltage, after passing a second threshold value it is disconnected from the supply voltage and if the middle voltage level is above a third threshold value the middle voltage level is connected with a ground potential until it has reached the fourth threshold value, wherein the middle voltage level is disconnected from ground potential. To use four threshold values is advantageous because by using only two thresholds for defining a tolerance range the middle voltage level has to be switches to a higher or a lower voltage potential very often. To compare the current value of the middle voltage level a first and second comparator are used. These comparators comparing the current value of the middle voltage level with the four threshold values. Due to efficiency only two comparators are arranged, wherein an input of each of the comparators is switchable to two different partial voltage levels. These partial voltage levels define the four threshold values. For connecting the middle voltage in dependency on the a deviation a first and a second switch is arranged, wherein the first switch connects the middle voltage level with a higher voltage potential and the second switch connects the middle voltage level with a lower voltage potential. By doing this a charge brought from the display could be stored in the capacitor at the output of the middle voltage level. As long as the charge is within the tolerance range between the first and the third threshold, the middle voltage level and its output capacitor is not connected to a lower voltage potential. Thus the charge is stored resulting in lower power consumption. In a preferred embodiment of the present invention only two rows are driven or selected by means for driving the row electrodes. Therefore only three different column voltage levels are required. For selecting the rows three different row selection voltages are required. The row selection voltages are created by using a row generation unit which provides the high row selection voltage levels. The middle voltage level is controlled without using a buffer, by connecting the middle voltage output with a higher or a lower voltage potential if the current value of the middle voltage is out of the tolerance range. In a preferred embodiment a column voltage level generator generates the required column voltages, whereas a reference voltages is used, which is supplied to a regulator, whereas the regulator is arranged for calibrating the highest column voltage level in order to compensate for technology variations, temperature and liquid crystal, etc. This will be achieved by changing the ratio of two resistors arranged at the output of the regulator. The reference voltage is internally generated. It is internally generated by a bandgap circuit, which depends on implementation, e.g. 1,4V. This makes the column voltage levels independent on the power supply level and noise. In a preferred embodiment the regulator, the buffers and comparators are supplied with two different power supply voltages, wherein these two power supply voltages are generated by using a charge pump, which uses external capacitors. So chip area is saved and the generated power supply voltages are very exact. The object of the present invention is also solved by a method for driving column electrodes of a display device with columns and rows, wherein at least p>2 rows are driven simultaneously and the column voltages to be supplied to the column electrodes are generated by a column voltage level generator in dependency on the image data to be displayed, which is generating p+1 different column voltage levels, wherein the column voltage levels are distributed around a middle voltage level, the middle voltage level is connected with a higher voltage potential or a lower voltage potential in dependency on the current value of the middle voltage level in respect to an upper and a lower threshold value. For a more complete description of the present invention and for further objects and advantages thereof, reference is made to the following description, taken in conjunction with the accompanying drawings, in which:

Fig. 1 shows an electric circuit diagram of a display device according the present invention; Fig. 2 shows a row and column voltage level generation unit known from the prior art; Fig. 3 shows an alternative row and column voltage level generation unit known from the prior art; Fig. 4 shows a column voltage level generation unit according the present invention for p=4; Fig. 5 shows a course of the middle voltage level within the range of tolerance; Fig. 6 shows a row and column voltage level generation unit according the present invention for p=2; Fig. 7 shows a row and column voltage level generation unit according the present invention for p=8; Fig. 8 shows an electric circuit diagram for supplying the row and column voltage levels to the row and column electrodes;

Figure 1 shows an electric circuit diagram of a display device comprises a display arrangement 1 and a display driver circuit 2. The display arrangement 1 comprises a matrix of pixels 8 defined by the areas of crossings of row or selection electrodes 7 and column or data electrodes 6. The display driver circuit 2 includes a row driver 4, which supplies row selection voltages or mutually orthogonal functions to the row electrodes 7. Further a column driver 5 is arranged within the display driver circuit 2. The column driver 5 supplies column voltage levels according to data to be displayed to the column electrodes 6. To this end, incoming data are first processed, if necessary, in a processor 3. Mutual synchronization between the row driver 4 and the column driver 5 takes place via control lines 9. Figure 2 shows an architecture used for driving the column and row voltage levels known in prior art. In the architecture the power supply voltage Vdd is supplied to a voltage doubler 21 and to a charge pump 22. The charge pump 22 creates a voltage V2, which is three times higher than the power supply voltage Ndd. This voltage level N2 is supplied to a voltage mirror 23 generating the voltage level V3 and the mirrored voltage level MV3. These voltage levels V3 and MN3 are used for selecting the rows of a display device. After doubling the power supply voltage Ndd in the doubler 21 the voltage level Nl is created. This voltage level Nl is supplied to a voltage dividing unit 26 making partial voltage levels, which are provided to the buffers 25 and 24. The buffers 24 and 25 are stabilizing or buffering the partial voltage level supplied from the voltage dividing unit 26 for providing the column voltage levels VC and MV1. The column voltage level MN2 is ground. In the following an example is given for the column and row voltage levels. Ndd=2,8N; N3=12N; N2=6V; VI =4,5 V; VC=3V; MV1=1,5V; MV2=0N and MV3=-6V. This example shows that the column and row voltage levels are symmetrically arranged around the middle voltage level NC, wherein they are further equidistant to each other. In this architecture a way to save power is provided by supplying the column voltage levels VI, VC, MV1, MV2 with a separate voltage doubler 21 supplying bias buffers 24 and 25 with the minimum required voltages, for example 0.5V to Vdd above the buffered output voltage level. The power lost because of the buffers 24 and 25 is then limited to the minimum. The voltage doubler 21 and charge pump 22 produce voltages having a low ripple, also accurate enough, but only if it uses high frequencies and integrated capacitors, in which case they are suited to work in a regulated way and directly supply column voltage levels for example with lOmV accuracy. To use on-chip capacitors within the charge pumps is problematic. It is disadvantageous that voltage doubler 21, charge pump 22 and the voltage mirror 23 are less efficient because they have high switching losses that increase with the frequency. Also, the integrated capacitors consume area on chip and this area is expensive in the submicron technologies. Therefore, a charge pump with external, large capacitors is more suited for a LCD display driver, because the switching frequency can be much lower. Such architecture is shown as example in the figure 3. Since the column voltage levels have the high ripple at the output, whereas this ripple is dependent on the load current of the charge pump, bias buffers 24 and 25 are required to obtain clean and accurate bias levels. Figure 3 shows an architecture known in the prior art using external capacitors 331. To provide the different column voltage levels V2, VI, VC, MV1, MV2 and the row selection voltage levels V3, MV3 a buffer 35, 36 and 37 is used per level, whereas MV2 is the ground potential Vss. The middle voltage level VC is used as well for the column voltage levels as for the row selection voltage levels. The advantage of this architecture is that the buffers 34 - 38 have a high Power Supply Rejection Ratio (PSRR), thus filtering out all ripples on the supply voltages. The row voltage level generation unit 32 generates the row voltages V3 and MV3 by using buffer 38. The buffer 38 gets the out signal V2 from buffer 34. The voltage mirror 39 works as mirror and charge pump, thereby producing the positive high row voltage level V3 and the negative row voltage level MV3. The PSRR (Power Supply Rejection Ratio) is the quantity measuring the ability of a buffer to keep the disturbances from the power supply lines away from the output signals. In this invention, this means that the power supplies Vsupplyl, Vsupply2 can be noisy because of the switching of the DC/DC converter or charge pump 332, the buffers will keep away this noise from the output signals which are the column and row voltage levels V3, V2, VI, VC, MV1, MV2 and MV3 to drive the display. This solution is very precise for all the column and row voltage levels.

By using the capacitors Cl, C2, C3 and C4, with a large value, e.g.100 times larger than the capacity of the display C_di_spi y, the peaks of charge/discharge display's current will be taken from these capacitors and the buffers 34, 35, 36, 37 will bring only the required charge back to restore the voltage level in a long time. Thus the buffers 34-37 are not required to settle very quickly, because they have high Power Supply Rejection Ratio in the operating frequency range and are stable with large external capacitors on the outputs. The problem of using buffers is that they always try to keep the voltage to the outputs constant and for this they will consume current every time one take charge from the output capacitors to give to the display. Also in the case, for example of the column voltage level VC, charge is brought from the display and the voltage increases, the buffer 36 will discharge the output capacitor. This charge is then lost to ground Vss by the buffer 36 instead of being stored into the output capacitor C3 for a later use. If this happens often, this charge which gets lost is very significant. Suppose that after one transition in the column voltage level which brings charge from the display, it follows another transition in which the display need charge: then the buffer will restore the voltage level by charging the output capacitor instead of finding this already charged with the charge of the display at a previous transition. The amount of charge from the capacitors C2, C3 and C4 which gets lost to ground potential Vss could be minimized by for example by relaxing the tolerance of the column voltage level and make the buffer weaker. The risk is in the actual state that the optical quality of the image is degraded and for same images the driving system is so weak that the buffers do not fulfil their task anymore, in the sense that they can not entirely restore the charge on the voltage level capacitors C1-C4. Any design is a compromise between optical quality and current consumption. This is the reason for which the invention proposes an improvement based on the symmetry of the load and column voltage levels. Figure 4 shows a column voltage level generating unit 41. Based on the thoughts made above the middle voltage level VC is driven without using a buffer. This could be done because the influence of an eventual deviation of each of the column voltage levels V2, VI, VC, MV1, MV2 do not have any impact on the quality of the displayed image, if this deviation is for a short time and is recovered by the charge brought from the display. Figure 4 shows an external generation unit 42 for supplying the power supplies Vsupplyl and Vsupply2. As explained in respect to figure 3, external capacitors 331 are used, so the charge pump 332 will filtering the noise from the power supplies Vsupplyl and Vsupply2. This embodiment shown in figure 4 is applicable for p=4 simultaneously driven rows. Therefore 5 different equidistant column voltage levels V2, VI, VC, MV1 and MV2 are required. The column voltage level MN2 is the system ground Vss, the level V2 is buffered as seen in the figure 4 by using a buffer 43. By the exact trimming of the ratio R2/R1, the level V2 can even be calibrated in order to compensate for the technology variations, temperature and characteristics of liquid crystal, etc. The column voltage level V2 is supplied to the voltage divider unit 26 including the resistors R3-R9, which supplies partial voltage levels to the buffer 44, 47 and to the comparators 45, 46. The problem remains for the inner column voltage levels VI, MN1 and NC. For Nl and MN1, the only alternative is to use buffers with low offset, because they need to be very precise due to the small deviations which are allowable without a degradation of the display quality. As the middle voltage level NC can vary without optical quality degradation by more than 300mN over several row selection time slots no buffer is required for driving the middle voltage level NC. The average current on this middle voltage level VC in time is zero because the driving method is symmetrical in the sense the upper column voltage levels VI, V2 source a current and the lower column voltage levels MV1, MV2 sink the same amount of current from the column voltage levels outputs. So the middle voltage level VC can go around by the charge brought and taken by the display itself, if everything is in a steady state. Therefore there is no need to drive the capacitor C3 at all. Only for a startup phase the middle voltage level VC should be charged quickly, so it has to be controlled in an easy way. To control the middle voltage level VC two comparators 45, 46 and 6 switches SI, S2, S3, S4, S5 and S6 are arranged, whereas the implemented switches are preferably MOS transistors. The principle is that when the middle voltage level VC is lower than a certain threshold, one comparator gives the order to charge quickly the capacitor C3 from the voltage Vsupplyl until middle voltage level VC enter in a very- narrow range around the theoretical predetermined value. Then, the middle voltage level VC is disconnected from the Vsupplyl by the comparator 46 and the middle voltage level VC will vary only because of the charge brought during the switching of the display, up and down by small steps. The steps are small because the capacitor C3 is 100 times larger than the total capacity of the display. The threshold values A, B, C, D are defined by the partial voltage values which are supplied to the inputs of the comparators 45, 46. Each comparator 45, 46 is connected with two different partial voltage values using a pair of switches SI, S2 and S3, S4. The other input of each comparator 45, 46 is connected to the output capacitor C3 and the middle voltage level VC. These inputs could be connected via the respective switches S5 or S6 with a lower (NSS) or a higher voltage potential (Vsupplyl). It is advantageous to connect the middle voltage level VC with the internal generated power supply Vsupplyl or the ground Vss. Taking charge and bringing it from other critical bias levels will have effects on the optical quality. Charge can be brought/taken only from/to Vsupplyl /Vss as they are strongly driven from powerful circuitry and this does not affect the other column voltage levels. In the figure 5 is illustrated how the middle voltage level VC will change in time and how the two comparators 45, 46 and the 6 switches SI, S2, S3, S4, S5 and S6 will act. The most of the time the middle voltage level VC will be within the third threshold value C = VC + 150m V and the first threshold value D = VC 150m V. When the comparators 45, 46 need to correct the instantaneous value of the middle voltage level VC, they will bring the level inside the second threshold value B = VC - 15mV and the fourth threshold value A = VC + 15mV. Over a long time, the average of the middle voltage level VC will be the theoretical predetermined value in the middle of the VI andMVl. It would be possible to use only two threshold values around the theoretical middle voltage value VC to correct the column voltage level, but then, when the middle voltage level VC is somewhere around one of the thresholds A, B, C, D then one of the comparators 45, 46 will switch on and off all the time, thus consuming current even more than a buffer. The four thresholds A, B, C, D as explained above are necessary in order to prevent a mode of continuous switching and because of the described method, the comparators 45, 46 will have to act on the switches SI, S2, S3, S4, S5 and S6 only very seldom, to correct a too large deviation from the theoretical value. Compared with the prior art, which loose current because the buffers tend to correct the middle voltage level VC continuously, the inventive comparators approach saves this current, resulting in 50% less current from the power supply battery. As a conclusion, the proposed architecture with two comparators saves all the current that a buffer would have to spend to correct continuously the middle voltage level VC. As they operate ON and OFF and the continuous switching is prevented by the exposed four thresholds A, B, C, D method, the system is stable and on a long time average it is even very accurate. Figure 6 shows an embodiment for p=2. The column voltage level generator 61 provides three different column voltage levels VI, VC and MV1, whereas the row voltage generator 62 generates the row selection voltages V2 and MV2. The column voltage level MN1 is ground potential NSS. La this embodiment only one buffer 63 is required for controlling the column voltage Nl . The middle voltage level VC is controlled via the switches SI and S2, which connect the middle voltages level VC with a higher or a lower voltage depending on the current value of the middle voltage level VC. To control the switches SI and S2 two comparators 64 and 65 are used as described above. A realisation using four threshold value as described for p=4 in figure 4 could be easily adapted for p=2. A further embodiment is shown in figure 7. This example is given for p=8, wherein 9 different column voltages V4, V3, V2, VI, VC, MV1, MV2, MV3, MN4 are required. The column voltage generator 71 generates the column voltages N3- MN3, whereas the row voltage generator 72 generates the row and column voltage levels N4 and MN4. In this embodiment the row voltage levels V4 and MV4 are the same as the highest and the lowest column voltage level. It is illustrated that the column voltage levels V2, VI, MV1 and MV2 are driven by using buffers 74, 75, 78 and 79. The middle voltage level VC is controlled via switches SI and S2 which are controlled from comparators 76 and 77 as described above. Due to the clearness the comparators 76 and 77 are provided only with two threshold values, whereas a providing of four threshold values as for p=4 is conceivable. Thus the invention refers to a display device to obtain middle voltage level VC using a set of two comparators and six switches, connected in such a way that the middle voltage level VC is brought within the tight threshold levels A and B (figure 5) whenever they tend to move out of the wider thresholds C and D. Additionally, the invention refers to a display device which generates all the bias or column voltage levels necessary to drive a passive LCD display with the Multiple Rows Addressing, or any other driving method presenting the feature that the DC bias levels are symmetrical towards a middle voltage and the current load is symmetrical and in which the VC level is set by two comparators working in the way described in the figure 5. The embodiment can be used in any display driver circuit used to build a LCD display with very low current consumption for use in portable devices. The column voltage level VC varies because of the switching of the display within the display driver in small steps. The invention exploits the symmetry of the driving scheme and the observation that a deviation of 300mV during several row selection time slots of the middle voltage level VC will not have any effect on the quality of the image. Because the average load current in the middle voltage level VC is zero, such a driving scheme is possible and it prevents the waste of current because of the continuous correction of the voltage level through a bias buffer. Because the current in the middle voltage level VC is instantaneously the sum of the other bias level currents, the current saved with the inventive method can be up to 50% lower than with a classical approach with buffers. Figure 8 shows a circuit diagram illustrating the providing of the generated row and column voltage level V3, N2, Nl, NC, MV1, MN2 and MN3 to the row electrodes 7 and the column electrodes 6. The switches in the row driver 4 and column driver 5 are controlled from a not shown controller. The controller is arranged within the display driver circuit 2. Dependent from the driving used scheme and the data to be displayed the switches are controlled, so as to provide the required voltage levels to the respective row electrodes 7 and the respective column electrodes 6.

Claims

CLAIMS:

1. Display device comprising a display arrangement (1) and a display driver circuit (2), the display arrangement (1) comprises a liquid crystal material between a first substrate provided with row electrodes (7) and a second substrate provided with column electrodes (6), in which overlapping parts of the row and column electrodes define pixels (8), and the display driver circuit (2) comprises means (5) for driving the column electrodes (6) with column voltage levels (V2, VI, VC, MVl, MV2) and means (4) for driving the row electrodes (7) with row selection voltage levels (V3, VC, MV3); the row electrodes (7) supply groups of p rows (p>2) with row selection voltages (V3, VC, MN3) for selecting rows and the column electrodes (6) supply columns with column voltages (N2, Nl, NC, MVl, MV2), the column voltages (V2, Nl, VC, MVl, MV2) to be supplied to the column electrodes (6) are selectable from p+1 different column voltage levels (V2, Nl, NC, MVl, MV2) depending on the image data to be displayed; the column voltage levels (V2, VI, VC, MVl, MV2) are symmetrically distributed around a middle voltage level (NC), wherein in dependency on a deviation from a predetermined value of the middle voltage level (VC), the middle voltage level (VC) is connectable with a higher (VI, V2) or a lower voltage potential (MVl, MV2) until the predetermined value of the middle voltage level (VC) is reached or the middle voltage level (VC) stays within a tolerance range (A, B).

2. Display arrangement as claimed in claim 1, wherein the column voltage levels below (MVl) and above (VI, V2) the middle voltage (VC) are driven by using buffers (43, 44, 47).

3. Display arrangement as claimed in claim 1, wherein the means (5) for driving the column electrodes (6) creating a plurality of partial voltages levels using a voltage divider unit (26), which are supplied to buffers (43, 44, 47).

4. Display arrangement as claimed in claim 1, wherein four threshold values (A, B, C, D) are used for controlling the middle voltage level (VC), wherein if the current value of the middle voltage (NC) is below a first threshold value (D), the middle voltage (NC) is connected to a supply voltage (Vsupplyl), after passing a second threshold value (B) it is disconnected from the supply voltage (Vsupplyl) and if the middle voltage level (NC) is above a third threshold value (C) the middle voltage level (VC) is connected with a ground potential (VSS) until it has reached the fourth threshold value (A), wherein the middle voltage level (VC) is disconnected from ground potential (VSS).

5. Display arrangement as claimed in claim 4, wherein for connecting or disconnecting the middle voltage level (VC) with the higher (Vsupplyl) and the lower potentials (NSS) a first and second switches (S6, S5) are arranged, which are controlled by a first and a second comparator (46, 45).

6. Display arrangement as claimed in claim 5, wherein an input of each of the first and the second comparator (46, 45) is connectable with two different partial voltage level provided by a voltage divider unit (26) via a pair of switches (SI, S2 and S3, S4), which are controlled depending from the current value of middle voltage level (NC), whereas the individual partial voltage levels defining the four threshold values (A, B, C, D).

7. Display arrangement as claimed in claim 1, wherein the number of simultaneously driven rows is p=2, wherein three different, equidistant column voltage levels (Nl, NC, MVl) are required for driving the column electrodes (6) and three different row selection voltage levels (V2, NC, MN2) are required for selecting the row electrodes (7), wherein the middle voltage level (NC) is controlled using two switches (SI and S2) which are controlled by two comparators (64, 65) in dependency on two threshold values.

8. Display arrangement as claimed in claim 1, wherein the number of simultaneously driven rows is p=8, whereas 9 different, equidistant column voltage levels (N4,N3, N2, VI, VC, MVl, MV2, MV3,MV4) are required for driving the column electrodes (6) and three different row selection voltage levels (N4, VC, MV4) are required for selecting the row electrodes (7), wherein the middle voltage is controlled using two switches (SI and S2) which are controlled by two comparators (76, 77) in dependency on two threshold values.

9. Display arrangement as claimed in claim 1 , wherein two supply voltages (Nsupplyl, Nsupply2) are created by using a charge pump (332), having external capacitors (331).

10. Method for driving column electrodes (6) of a display device with columns and rows, wherein at least p>2 rows are driven simultaneously and column voltages to be supplied to the column electrodes (6) are generated by a column voltage level generator (41) in dependency on the image data to be displayed, which is generating p+1 different column voltage levels (N2, VI, VC, MVl, MN2), wherein the column voltage levels (N2, VI, VC, MVl, MV2) are distributed around a middle voltage (NC), wherein the middle voltage level (NC) is connected with a higher voltage potential (Nsupplyl) or a lower voltage potential (NSS) in dependency on the current value of the middle voltage level (VC) in respect to an upper (A,C) and a lower threshold value (D,B).