WO2005008729A3 - Procede et appareil d'embrouillage de contenu de cellule dans un circuit integre - Google Patents

Procede et appareil d'embrouillage de contenu de cellule dans un circuit integre Download PDF

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Publication number
WO2005008729A3
WO2005008729A3 PCT/US2004/022146 US2004022146W WO2005008729A3 WO 2005008729 A3 WO2005008729 A3 WO 2005008729A3 US 2004022146 W US2004022146 W US 2004022146W WO 2005008729 A3 WO2005008729 A3 WO 2005008729A3
Authority
WO
WIPO (PCT)
Prior art keywords
scan chain
register
transmitted
configuration register
data
Prior art date
Application number
PCT/US2004/022146
Other languages
English (en)
Other versions
WO2005008729A2 (fr
Inventor
Alain Vergnes
Original Assignee
Atmel Corp
Alain Vergnes
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from FR0308405A external-priority patent/FR2857535A1/fr
Application filed by Atmel Corp, Alain Vergnes filed Critical Atmel Corp
Priority to EP04777926A priority Critical patent/EP1652217A4/fr
Publication of WO2005008729A2 publication Critical patent/WO2005008729A2/fr
Publication of WO2005008729A3 publication Critical patent/WO2005008729A3/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
    • G06F21/79—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318555—Control logic
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318572—Input/Output interfaces
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03828—Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties
    • H04L25/03866—Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties using scrambling

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Logic Circuits (AREA)
  • Storage Device Security (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

L'invention concerne un système permettant de procéder à l'embrouillage de données dans une cellule séquentielle. La cellule séquentielle est conçue pour recevoir les données d'un bus de données. Une unité d'embrouillage est raccordée à la cellule séquentielle et au bus de données. L'unité d'embrouillage est conçue pour recevoir une entrée d'unité d'embrouillage du bus de données et produire une sortie d'unité d'embrouillage différente de l'entrée d'unité d'embrouillage. La sortie d'unité d'embrouillage est transmise à la cellule séquentielle. Une unité de désembrouillage est raccordée à la cellule séquentielle et est conçue pour recevoir une entrée d'unité de désembrouillage de la cellule séquentielle et produire une sortie d'unité de désembrouillage différente de l'entrée d'unité de désembrouillage. La sortie d'unité de désembrouillage est égale à l'entrée d'unité d'embrouillage.
PCT/US2004/022146 2003-07-09 2004-07-08 Procede et appareil d'embrouillage de contenu de cellule dans un circuit integre WO2005008729A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP04777926A EP1652217A4 (fr) 2003-07-09 2004-07-08 Procede et appareil d'embrouillage de contenu de cellule dans un circuit integre

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
FR0308405A FR2857535A1 (fr) 2003-07-09 2003-07-09 Procede et systeme pour brouiller le contenu d'une cellule dans un circuit integre.
FR0308405 2003-07-09
US10/861,683 2004-06-04
US10/861,683 US20050033961A1 (en) 2003-07-09 2004-06-04 Method and apparatus for scrambling cell content in an integrated circuit

Publications (2)

Publication Number Publication Date
WO2005008729A2 WO2005008729A2 (fr) 2005-01-27
WO2005008729A3 true WO2005008729A3 (fr) 2007-03-15

Family

ID=34081982

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/022146 WO2005008729A2 (fr) 2003-07-09 2004-07-08 Procede et appareil d'embrouillage de contenu de cellule dans un circuit integre

Country Status (2)

Country Link
EP (1) EP1652217A4 (fr)
WO (1) WO2005008729A2 (fr)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5442628A (en) * 1993-11-15 1995-08-15 Motorola, Inc. Local area network data processing system containing a quad elastic buffer and layer management (ELM) integrated circuit and method of switching
US5745479A (en) * 1995-02-24 1998-04-28 3Com Corporation Error detection in a wireless LAN environment

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4465901A (en) * 1979-06-04 1984-08-14 Best Robert M Crypto microprocessor that executes enciphered programs

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5442628A (en) * 1993-11-15 1995-08-15 Motorola, Inc. Local area network data processing system containing a quad elastic buffer and layer management (ELM) integrated circuit and method of switching
US5745479A (en) * 1995-02-24 1998-04-28 3Com Corporation Error detection in a wireless LAN environment

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP1652217A4 *

Also Published As

Publication number Publication date
EP1652217A4 (fr) 2009-05-13
EP1652217A2 (fr) 2006-05-03
WO2005008729A2 (fr) 2005-01-27

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