WO2005006553A2

WO2005006553A2 - Inhibitable diode switch

Info

Publication number: WO2005006553A2
Application number: PCT/GB2004/002771
Authority: WO
Inventors: Richard Neville
Original assignee: Lc Industries Ltd
Priority date: 2003-07-09
Filing date: 2004-06-28
Publication date: 2005-01-20
Also published as: GB0315979D0; WO2005006553A3

Abstract

An inhibitable switching circuit comprising a back to back diode switch and an inhibit circuit connected to the back to back diode switch. The back to back diode switch comprises first and second diodes each having a first polarity region and a second polarity region, the first and second diodes being connected in series back to back with the first polarity region of the first diode connected to the first polarity region of the second diode. The back to back diode also comprises a first input terminal connected to the second polarity region of the first diode, an output terminal connected between the first and second diodes and a third terminal connected to the second polarity region of the second diode. The back to back diode switch is operable to generate a switching output at the output terminal in response to an input signal at the first terminal provided the input pulse duration is less than the storage and delay times of the first and second diodes. The inhibit circuit comprises an output connected to the third terminal of the back to back diode switch and at least a first input for receiving an inhibit circuit control signal, the inhibit circuit further comprising circuit means for selectively generating an inhibit signal on the inhibit circuit output in response to an appropriate input control signal, the inhibit signal acting to modify the output of the back to back diode switch.

Description

INHIBITABLE SWITCHING CIRCUIT

The present invention relates to an inhibitable switching circuit, and in particular to a switching circuit comprising a back to back diode switch. The inhibitable switching circuit of the present invention has particular application in the construction of logic gates.

The concept of a rapidly switching diode switch comprising a pair of diodes connected back to back (i.e. either cathodes connected together or anodes connected together) was first disclosed by D P Neville in British patent GB1417839. D P Neville was the first to realise that by applying a pulsed input signal to such a back to back diode switch, which is pulsed very rapidly with a pulse duration shorter than the storage or delay times of the diodes, an equally rapidly switching output can be obtained which follows the input signal. D P Neville realised that this switching action could be explained by applying an electrostatic model to the behaviour of the diodes as is discussed in detail in GB1417839 to which reference should be made.

D P Neville applied his invention to the construction of logic gates capable of extremely rapid switching and with lower power consumption (the switch is in fact powered by the input signal).

In addition to the logic gates proposed by D P Neville, back to back series connected diodes have been used with beneficial effects in other applications. For example, in Motorola Semiconductor Products Inc., 'The Effect of Emitter-Base Avalanching on High-Voltage Power Switching Transistors ', Application Note AN-80, 1981, Motorola™ placed the base- emitter junction of a power transistor under reverse bias during turn-off, causing it to go into breakdown and decrease its turn-off losses. By taking the junction into avalanche breakdown, large charge build-ups are removed very quickly, therefore reducing turn-off losses. In PCT application number PCT/GB87/00790 (publication number WO88/03726), Emco Display Technology Limited utilise a pair of back to back diodes to enhance the rising and falling edges of signals.

Surprisingly there has been no development of D P Neville's original concept of logic gates based on a rapidly switching back to back diode switch. This may be because GB1417839 does not disclose the means necessary for the convenient construction of more complex logic functions which are fundamental to modern electronics, such as NAND, NOR and XOR gates amongst others.

It is an object of the present invention to extend the teaching of GB1417839 to produce new and useful switching circuits.

According to the present invention, there is provided an inhibitable switching circuit comprising: a back to back diode switch; an inhibit circuit connected to the back to back diode switch; wherein: the back to back diode switch comprises: first and second diodes each having a first polarity region and a second polarity region, the first and second diodes being connected in series back to back with the first polarity region of the first diode connected to the first polarity region of the second diode; a first input terminal connected to the second polarity region of the first diode; an output terminal connected between the first and second diodes; a third terminal connected to the second polarity region of the second diode; wherein the back to back diode switch is operable to generate a switching output at said output terminal in response to an input signal at said first terminal provided the input pulse duration is less than the storage and delay times of the first and second diodes; and wherein the inhibit circuit comprises an output connected to the third terminal of the back to back diode switch and at least a first input for receiving an inhibit circuit control signal, the inhibit circuit further comprising circuit means for selectively generating an inhibit signal on said inhibit circuit output in response to an appropriate input control signal, said inhibit signal acting to modify the output of the back to back diode switch.

The inventors have realised that the present invention is advantageous in that by providing an input for selectively inhibiting the output of a switch disclosed in GB1417839, more additional circuits, including those with more complex logic functions, can be conveniently created.

The term diode is taken to refer to any two terminal, asymmetrically conducting device. It is anticipated that the present invention will most readily be constructed using semiconductor diodes, but the same principles could be applied to other electrostatic or electro-chemical (e.g. batteries) devices.

The invention will now be described with reference to the accompanying figures, in which:

Figure la is a circuit diagram of a first prior art switch;

Figure lb is a circuit diagram of a second prior art switch;

Figure 2 is a graph of the current- voltage characteristics of the switch of Figure 1;

Figure 3 is a graph of the switching characteristic of the switch of Figure 1;

Figure 4 is a circuit diagram of an AND or OR gate as disclosed in GB1417839;

Figure 5a is a circuit diagram of a general inhibit circuit according to the present invention, connected to a positive back to back diode switch;

Figure 5b is a circuit diagram of a general inhibit circuit according to the present invention, connected to a negative back to back diode switch;

Figure 6 is a circuit diagram of an inhibited OR gate incorporating the general inhibit circuit;

Figure 7 is a circuit diagram of an inhibited AND gate incorporating the general inhibit circuit;

Figure 8 is a circuit diagram of a synchronous invertor incorporating the general inhibit circuit;

Figure 9 is a circuit diagram of a synchronous invertor incorporating a first inhibit circuit;

Figure 10 is a circuit diagram of a NOR gate according to the present invention;

Figure 11 is a circuit diagram of a NAND gate according to the present invention;

Figure 12 is a circuit diagram of a XOR gate according to the present invention;

Figure 13 is a circuit diagram of a full adder according to the present invention;

Figure 14 is a logic representation of an RS flip-flop;

Figure 15a is a circuit diagram of an RS flip-flop according to the present invention;

Figure 15b is a further circuit diagram of an RS flip-flop according to the present invention;

Figure 16 is a circuit diagram of a second inhibit input circuit connected to a simple switch;

Figure 17 is a circuit diagram of a third inhibit input circuit connected to a simple switch;

Figures la and lb are circuit diagrams of a prior art logic switch as disclosed in GB1417839.

Figure la illustrates a 'positive' logic switch 1 comprising a first diode 2 under forward bias for a positive input voltage, in series with a second diode 3 under reverse bias for a positive input voltage. This is achieved by connecting a cathode of the first diode 2 to a cathode of the second diode 3, referred to as 'back to back diodes'. A simple 'negative' switch, as illustrated in Figure lb, has the orientation of the diodes reversed (diodes connected back to back with anodes connected together) and a negative input voltage. This simple switch will be referred to hereinafter as the "back to back diode switch".

The back to back diodes are made to act as a switch by applying a pulsed input signal, each pulse have a duration (or 'width') that is less than storage and delay times of the diodes used. Fundamental to the invention of GB1417839 is the realisation that, by applying the pulsed signal in such a manner, no substantial current can flow into the logic switch 1 (back to back diode switch). Rather, the characteristics are defined by electrostatic phenomena and, by employing electrostatic modelling not previously applied to diodes, D P Neville appreciated that such an unconventional application of a back to back diode arrangement yielded beneficial switching properties. In particular, a switch comprising back to back diodes switches extremely quickly, has a low power consumption and its pulsed input signal also serves as the power supply to the switch, negating the need for a separate voltage supply.

Referring again to Figures la and lb, the reverse biased diode 3 is doped in order to bring its reverse breakdown threshold voltage (hereinafter referred to as 'threshold voltage') into the range of a few volts, as opposed to a hundred volts or more for a typical diode. Such doping is merely to ensure that the switch operates within a convenient voltage range, namely that adopted for standard logic circuits. When the pulsed input signal Vin is applied across the two diodes 2 and 3, they behave as a capacitive potential divider if the magnitude of the voltage across the reverse biased diode 3 is less than its threshold value VTH- For instance if the diodes are similar, the voltage drop across each is substantially equivalent, and hence the magnitude of an output of the switch V_OUT, taken across the reverse biased diode 3, is approximately half that of the input pulse V^. Other than its magnitude, the output signal is substantially the same as the input signal.

However, when the input voltage V_IN is such that voltage across the reverse biased diode 3 is greater than its threshold value V_TH, the switch 1 will switch and the output Vout will be substantially equal to Vin (Vin minus a small voltage drop across the forward biased diode 2). This is explained in greater detail in relation to Figures 2 and 3. Illustrated in Figure 2 are the Current-Voltage characteristics of the positive back to back diode switch 1 (for an input pulse ranging from 0 to a positive voltage). Positive Current- Voltage values correspond to the characteristics of the forward biased diode, and the negative Current- Voltage values to the reverse biased diode 3. A solid line 4 corresponds to the DC, or 'conventional' operation of a diode, whereas a broken line 5 corresponds to the characteristics of the constituent diodes of the back to back diode switch with the aforementioned pulsed input, in line with an electrostatic appreciation. Thus the broken line represents a 'pseudo state', and is only appreciated if the operation of the back to back diode switch is considered to be of an electrostatic nature. The vertical scale of the pseudo state characteristic has been exaggerated for explanatory purposes.

It can be seen from Figure 2 that as the magnitude of the pulsed input is increased from zero, the voltage across the forward biased diode 2 and reverse biased diode 3 increases accordingly. The forward biased diode 2 and reverse biased diode 3 exhibit capacitive behaviour until a point where the voltage across the reverse bias diode 3 approaches its threshold voltage V_TH- At this point, avalanche multiplication begins in the reverse biased diode 3, and the back to back diode switch 1 begins to switch. Avalanche multiplication is much faster than the drifting of electrons (up to one thousand times faster), and thus the switching of this pulsed back to back diode switch is much faster than its DC counterparts. Avalanche multiplication in the reverse bias device causes a rapid alteration in the charge situation that existed between the two diodes prior to the input voltage equalling the threshold of the reverse biased device 3. The alteration causes the majority of the input voltage to be dropped across the reverse bias diode 3, leaving only a small forward voltage to be dropped across the forward biased diode 2.

Normally, a reverse bias diode that has begun avalanche multiplication will draw as much current as it can, eventually leading to avalanche breakdown. However, and crucial to the operation of the back to back diode switch 1, is the small forward voltage dropped across the forward biased diode 2, thus limiting the current supplied to the reverse bias diode 3. Such limitation prevents the reverse bias diode 3 from breaking down, and the current voltage characteristic of the back to back diode switch returns to that of DC state. Limiting the current to its leakage value reduces the power consumption of the switch. In short, the output of the device switches from half of the input voltage to the substantially the input voltage itself very quickly via avalanche multiplication.^' The back to back diode switch 1 utilises two limiting factors to achieve its unique switching properties: the current limiting effect of the forward biased diode after switching, and the fact that the output voltage is approximately equal to, and can never exceed, the input voltage. Figure 3 illustrates the switching characteristic of the back to back diode switch. It can be seen that the output voltage is approximately half of the input voltage until the voltage across the reverse bias diode 3, or the output voltage, approaches the reverse breakdown threshold voltage VTH of the reverse biased diode 3. At this point, avalanche multiplication begins, and the magnitude of the output voltage quickly switches to that of the input voltage.

Figure 4 illustrates an OR gate as disclosed in GB1417839. The addition of a further input, by way of an additional forward biased diode 6, allows the reverse biased diode 3 to breakdown upon sufficient voltage input from either or both inputs. Hence, an OR gate is created. GB1417839 discloses further simple logic circuits, such as an AND gate, and an asynchronous invertor.

Figures 5a and 5b illustrate a modification of the positive and negative back to back diode switches of Figures la and lb in accordance with the present invention. In each case the reverse biased diode 3 is no longer grounded, but is connected to an inhibit circuit 7 which provides an inhibit signal 8 to the reverse biased diode 3 in response to an input signal Vinhibit. The inhibit signal 8 prevents the reverse biased diode 3 from breaking down and, consequently, the switching of the back to back diode switch. In order to prevent switching regardless of the input signal Vin, the inhibit circuit 7 must be capable of generating an inhibit signal 8 comprising sufficient charge and voltage to counteract any effects produced on the reverse biased diode 3 by the input signal Vin. Examples of preferred and alternative inhibit circuits will be described further below with reference to Figures 9, 16 and 17.

A basic inhibited switching circuit according to the present invention as illustrated in Figures 5a and 5b have two inputs, Vin and Vinhibit. When an inhibit signal 8 is applied to the reverse biased diode 3 the switching action described above with reference to Figures la and lb is inhibited. Taking an input signal of '1' or 'high' to be one of sufficient magnitude to cause the switch 1 to switch, or in the case of the inhibit input Vinhibit to cause the inhibit circuit 7 to supply an inhibit signal 8 sufficient to prevent switching, a logic or truth table of an inhibited switch is illustrated in Table 1.

Table 1 - Truth Table For Inhibited Switch

Referring to Figure 6, this illustrates the prior art OR gate of Figure 4 modified in accordance with the present invention by provision of an inhibit circuit 7. Again the inhibit circuit 7 is operable to supply an inhibit signal 8 to the reverse biased diode 3 in response to an appropriate inhibit input signal Vinhibit. Thus, by including an inhibit signal 8 to the reverse bias diode 3 instead of grounding its anode, the output of these gates can be inhibited in an identical way to that of the basic back to back diode switch. There are now three inputs: Vinl, Vin2 and Vinhibit and Table 2 illustrates the associated logic table of the inhibited OR gate.

Table 2 - Truth Table For Inhibited OR gate Just as with the simple inhibited switch, if the inhibit signal 8 is made to be high the reverse biased diode 3 is unable to breakdown, and the output of the circuit is always low. From Table 2, it can be seen that if the inhibit input is low, the output of the OR gate is unaffected. Conversely, if the inhibit input is set to '1' or 'high', the output of the OR gate will not go high. Similarly the present invention can be applied to provide an inhibited and gate. For the creation of an AND gate, both inputs Vinl and Vin2 need to be high for the output of the gate to be high. It can be seen from the OR gate, that if either input is high, the output of the device will be also. However, if the reverse biased diode 3 is doubled in size, the charge situation is altered such that both inputs must be high in order for the device to give a high output - the reverse bias threshold of the diode has been doubled, and an AND gate has been created. Figure 7 schematically illustrates such an inhibited AND gate, where the reverse bias diode has been doubled in size 3a and an inhibit circuit 7 is provided to generate an inhibit signal 8 in response to an inhibit input signal Vinhibit. Table 3 below illustrates the associated logic table.

Table 3 - Truth Table For Inhibited AND gate

From Table 3, it can be seen that if the inhibit input is low, the output of the AND gate is unaffected. Conversely, if the inhibit input is set to '1' or 'high', the output of the AND gate will not go high.

The same method and apparatus used to inhibit the output of the AND and OR gates can be applied to any circuit incorporating the basic back to back diode switch, such as the asynchronous invertor disclosed in GB1417839, itself a variation of the OR gate and differing only in input signal methodology.

It will be appreciated from consideration of Tables 1-3 that the basic inhibited switch circuits of Figures 5-7 do not themselves have any obvious useful application in logic circuits. However, addition of an inhibit input to other switching circuits based on the basic back to back diode switch in accordance with the present invention can produce useful logic circuits not disclosed in GB1417839.

The beneficial use of the inhibit circuit 7 becomes more apparent when considering the construction of more complex logic gates such as NANDs and NORs, the building blocks for complex modern logic circuits, as well as the simple invertor. In all cases, an inhibit voltage input, preferably pulsed and identical to that used for signal inputs, is used to inhibit the switching of at least a pair of back to back diodes to yield devices with additional functionality. Hence all devices, as well as improved functionality, enjoy the same speed characteristics and low power consumption of the simple switch disclosed in GB1417839.

As a first example, GB1417839 discloses an asynchronous invertor, which introduces a delay in the output signal and changes its polarity. It is not a true invertor. Table 1 illustrates the logic table for an inhibited switch of Fig 5a. The circuit comprises a single 'data' input (Vin), an inhibit input (Vinhibit) and an output. It can be seen that the output signal is the inversion (or 'NOT') of the inhibit input when Vin is set to 'high'. Hence, if the inhibit signal Vinhibit is made to be a data signal, and Vin a clock pulse, a NOT gate, or synchronous invertor, is created: driven by the clock pulse, the data signal is inverted. Again, the pulse duration of the clock signal and data signal is shorter than the storage or delay times of the constituent diodes of the circuit. Figure 8 illustrates such a synchronous invertor, and Table 4 illustrates the associated truth table. Note that the case of the Clock signal being low is not considered. By its very nature, the clock signal is high whenever there may be a data input.

Clock (Vin of Data OUTPUT inhibited switch) (Vinhibit of inhibited switch) 0 1 1 0 Table 4 - Truth Table For Synchronous Invertor

A preferred embodiment of the asynchronous inverter, incorporating a preferred inhibit circuit 7a for generating the inhibit signal 8, is illustrated in Figure 9. The inhibit circuit 7a comprises a pair of back to back diodes in series, oriented in an opposite sense with respect to the positive back to back switch pair 2 and 3. Therefore, in the case as illustrated where the inhibit signal 8 is to be applied to a positive back to back diode switch (diodes 2 and 3), the circuit 7a generating the inhibit signal 8 comprises a first diode 9 and a second diode 10 whose anodes are connected together. The cathode of the reverse biased diode 10 is grounded, and a positive inhibit signal Vinhibit is supplied to the inhibit circuit 7a (applied across the diodes 9 and 10). The inhibit signal 8 is taken across the reverse biased diode 10.

The inhibit circuit 7a is very similar to the switch 1 itself, but switches at the reverse breakdown threshold of the reverse biased diode 9. The different orientation of the diodes ensures that upon switching of the circuit 7a generating the inhibit signal 8, charge inversion occurs at the inhibit input. Hence, by orienting the diodes of the inhibit circuit in this way and applying an inhibit signal Vinhibit equivalent to the clock signal applied to the back to back diode switch input, voltage and charge effects on the reverse biases diode 3 of the back to back diode switch 1 are equal and opposite and hence cancel, thereby preventing the reverse bias diode 3 from breaking down and the back to back diode switch from switching. Preferably, the input clock signal and Vinhibit are identical when the switch circuit is to be inhibited. When Vinhibit is zero, or insufficient in magnitude to cause reverse breakdown of the reverse biased diode 10 of the inhibit circuit 7a, the back to back diode switch's operation is unaffected.

It will be appreciated that the inhibit circuit 7a can also be implemented in the switch circuits of Figures 5 to 7. However, for other forms of logic gate providing more complex logic functions more sophisticated inhibit circuits are required as will be described below.

Figure 10 illustrates a NOR gate according to the present invention. This is a modification of the synclironous inverter of Figure 9 incorporating a modified inhibit circuit 7b in place of the inhibit circuit 7a. . In Figure 9, the inhibit circuit 7a generating the inhibit signal 8 is the inverse of the back to back diode switch itself (the diodes 9 and 10 of circuit 7a are connected anode to anode, compared with switch diodes 2 and 3 that are connected cathode to cathode).

Similarly, in the case of the NOR gate of Figure 10, an inhibit circuit 7b is formed by the inverse of an OR gate. Thus in place of the single forward biased diode 9 there are two parallel connected forward biased diodes 11 and 12 connected in series to a reverse biased diode 13 such that the anodes of the diodes 11 and 12 are connected to the anode of the diode 13. The cathode of the reverse biased diode 13 is connected to ground, and an output, i.e. the inhibit signal 8, is taken across the diode 13. The NOR gate thus has three inputs: an input to the back to back diode switch (i.e. the clock pulse), and inputs Vinl and Vin2 to diodes 11 and 12 of the inhibit circuit 7b. All inputs have a pulse duration that is shorter than the delay or storage times of the constituents diodes of the NOR circuit. It can be seen that as circuit 7b is effectively an OR gate, if either Vinl or Vin2 is 'high', an inhibit signal is provided to the back to back diodes switch to inhibit the switching action. A full truth table for the NOR gate is illustrated in Table 5.

Table 5 - Truth Table For NOR Gate

Hence if Vinl and Vin2 are 'data' inputs, the circuit functions as a NOR circuit when driven by a CLOCK pulse.

Figure 11 illustrates an NAND gate according to the present invention. As described previously, the only physical difference between an AND and an OR gate is the size of the reverse biased diode 3. In an AND gate, the reverse biased diode 3 is doubled in size such that it may only breakdown when two inputs are 'high'. Hence, the NAND circuit is physically identical to the NOR circuit, except for the fact that the reverse biased diode 13a is doubled in size. Other than a larger (double the size) diode 13a, the circuit is identical in terms of components and inputs to the NOR gate. Hence, a circuit 7c is formed by an inverse AND gate. If inputs Vinl and Vin2 are high, the output of the back to back diode switch is inhibited. If either inhibit circuit input (Vinl, Vin2) is low, the output of the back to back diode switch will not be inhibited. Table 6 illustrates the truth table for this NAND gate.

Hence if Vinl and Vin2 are 'data' inputs, the circuit functions as a NAND circuit when driven by a CLOCK pulse.

Figure 12 illustrates an XOR gate according to the present invention. The XOR gate is a combination of an inhibited OR gate 14 (including an inhibit circuit 7a as illustrated in Figure 9) which has inputs 15 and 16, and an uninhibited AND gate 17 (corresponding to the AND gate of Figure 7 but without an inhibit circuit - rather the reverse biased diode 3a is grounded) which has inputs 18 and 19. The AND gate 17 provides the Vinhibit input to the inhibit circuit 7a.

The XOR gate has inputs Vinl and Vin2 and output Vout which is the output of the OR gate 14. Vinl is supplied to input 18 of the AND gate 17 and to input 15 or the inhibited OR gate 14. Vin2 is supplied to input 19 of the AND gate 17 and to input 16 or the inhibited OR gate. If Vinl and Vin2 are both high, the AND gate 17 gives a high output Vinhibit which in turn activates the inhibit circuit 7a and inhibits the output of the OR gate 14 and hence of the XOR gate. Thus, if Vinl and Vin2 are high, the output from the XOR gate will always be low. However, if one of the inputs Vinl, Vin2 is low, the AND gate 17 is not activated, and will give a low output Vinhibit to the inhibit circuit 7a so that no inhibit signal 8 is supplied to the OR gate. Hence, if one of the inputs Vinl, Vin2 is low, the entire circuit now functions as an OR gate: an XOR gate has been created, whereby the output of the XOR circuit can only be high if only a single input, Vinl or Vin2, is high. Table 7 illustrates the truth table for the XOR circuit.

1 1 0 Table 7 - Truth Tab e For XOR Gate

An extension of the XOR gate is a full-adder, illustrated in Figure 13. The full-adder also comprises an inhibited OR gate 20 (including inhibit circuit 7a) and an AND gate 21 but differs from the XOR gate in that the inhibited OR gate 20 has three inputs 22, 23, 24 and the AND gate 21 has three inputs 25, 26, 27. Again the output of the AND gate 21 constitutes the inhibit signal Vinhibit which is supplied to the inhibit circuit 7a, but in addition provides a further output signal mentioned below. Crucially, the reverse biased diode 3a of the AND circuit 21 is double the size of the forward biased diodes so that a minimum of two inputs to the AND circuit need to be high for the reverse biased diode 3 a to breakdown, and for the AND circuit to give a high output.

The full adder has three inputs Vinl, Vin2 and Cin (carry in). Vinl is supplied to input 25 of the AND gate 21 and to input 22 or the inhibited OR gate 20. Vin2 is supplied to input 26 of the AND gate 21 and to input 23 or the inhibited OR gate 20. Cin is supplied to input 27 of AND gate 21 and input 24 of inhibited OR gate 20.

The full-adder has two outputs: Sum is the output of the inhibited OR gate 20 and Cout (carry out) is taken from the output of the AND circuit 21.

If any two of the full-adder inputs are high then a corresponding two of the AND gate inputs 25, 26, 27 and the OR gate inputs 22, 23 and 24 will also be high. The reverse biased diode 3 a of the AND gate 21 breaks downs and so that both Cout and Vinhibit are high. Vinhibit therefore inhibits the OR gate 20. As a result Cout is high and Sum is low. If only one or no inputs of the full-adder are high, the reverse biased diode 3 a of the AND circuit 21 does not breakdown, and does not initiate the inhibit function of the inhibited OR circuit 20. Hence with one or no inputs high, the full-adder merely functions as an OR gate: Cout is always low, Sum is the logic OR' of the full-adder inputs.

However, if all three of the inputs to the full-adder are high, the AND circuit still generates a high output Cout, and high Vinhibit supplied to the inhibit circuit 7a, but the inhibit signal 8 generated by the inhibit circuit 7a does not inhibit the OR gate 20 which generates a high SUM output. The inhibit signal 8 does not inhibit the OR gate in this condition due to three OR gate inputs 22, 23, 24 being high. That is, the charge situation is altered so as to 'override' the would-be inhibit effect of the inhibit signal 8 input. Thus, when all three full-adder inputs are high, the adder generates two high outputs, Sum and Cout. This behaviour is that of a full adder, and Table 8 illustrates the truth table for the full adder of Figure 16.

It will be appreciated that once a NAND or NOR gate is created, many more complex circuits may be created using these fundamental components. For example, a NOR based RS flip-flop can be created by interconnecting two of the NOR gates illustrated in Figure 10. Figure 14 illustrates a simple logic representation of an RS flip-flop. It can be seen that the output 'X' of a first NOR gate 28 is also one of the inputs of a second NOR gate 29, while the output 'Y' of the second NOR gate 29 is also one of the inputs of the first NOR 28 gate. The first NOR gate 28 has a second input 'A', and the second NOR gate 29 a second input 'B'.

Figures 15a and 15b illustrate the creation of an RS flip flop implementing two NOR gates according to the present invention. Figure 15a is a simple representation of how the NOR gates are interconnected, while Figure 15b is a more compact representation and efficient layout of the flip-flop. The devices illustrated in Figures 15a and 15b are functionally identical. Labelling of Figures 15a and 15b is consistent with Figure 14, but there is also a clock input 'CLOCK' and a ground connection present in these Figures. Each of the preferred embodiments of the invention described above has an inhibit circuit comprising two back to back diodes sized to correspond to the diodes of the circuit to be inhibited. It will be appreciated that the invention is not limited to this form of inhibit circuit and the skilled person could design other circuits or devices capable of generating the required inhibit signal. Two possible alternative inhibit circuits are illustrated in Figures 16 and 17.

Referring to Figure 16, the illustrated inhibit circuit 30 comprises two back to back pairs of diodes 31/32 and 33/34 respectively. The diodes of each pair are connected cathode to cathode in series, and the diode pair are connected in series with the inhibit input Vinhibit. The connection between the second pair of back to back diodes 33, 34 is grounded, and the inhibit signal 8 is output from the anode of diode 34. This inhibit circuit can be controlled by an appropriately varying Vinhibit to provide a varying inhibit signal 8 which could for instance be used to control the amplitude of the output of a back to back diode switch.

Referring now to Figure 17, the illustrated inhibit circuit comprises a single reverse biased diode 35. In this Vinhibit is a DC signal (rather than a pulse). The inhibit signal 8 is taken between the anode of the diode and ground. The inhibit signal is now a DC signal, as oppose to a pulse, which for instance can prevent switching of a back to back diode switch by offsetting the reverse biased diode of the switch. On the other hand if Vinhibit is zero the inhibit signal will be zero and the switch will be unaffected). It will also be appreciated that applying a DC input to the reverse biased diode a back to back diode switch after switching may be used to control the amplitude of the output of the switch.

All of the aforementioned circuits can be constructed in a conventional manner by a person of ordinary skill in the art. For example, the circuits according to the invention could be fabricated using industry standard BiCMOS processes. Similarly, the circuits according to the invention could be fabricated by any other process capable of fabricating p-n junctions or emitter based junctions on silicon.

Claims

1. An inhibitable switching circuit comprising: a back to back diode switch; an inhibit circuit connected to the back to back diode switch; wherein: the back to back diode switch comprises: first and second diodes each having a first polarity region and a second polarity region, the first and second diodes being connected in series back to back with the first polarity region of the first diode connected to the first polarity region of the second diode; a first input terminal connected to the second polarity region of the first diode; an output terminal connected between the first and second diodes; a third terminal connected to the second polarity region of the second diode; wherein the back to back diode switch is operable to generate a switching output at said output terminal in response to an input signal at said first terminal provided the input pulse duration is less than the storage and delay times of the first and second diodes; and wherein the inhibit circuit comprises an output connected to the third terminal of the back to back diode switch and at least a first input for receiving an inhibit circuit control signal, the inhibit circuit further comprising circuit means for selectively generating an inhibit signal on said inhibit circuit output in response to an appropriate input control signal, said inhibit signal acting to modify the output of the back to back diode switch.

2. A circuit according to claim 1, wherein the inhibit circuit means generates an inhibit signal which acts to inhibit the switching of the output of the back to back diode switch.

3. A circuit according to claim 2, wherein the inhibit circuit means comprises third and fourth diodes each having a first polarity region and a second polarity region, the third and fourth diodes being connected in series back to back with the second polarity region of the third diode connected to the second polarity region of the fourth diode, the first input of the inhibit circuit being connected to the third diode, the output of the inhibit circuit being connected between the third and fourth diodes, the fourth diode being connected to ground..

4. A circuit according to claim 3, further comprising means for supplying an input clock signal to the first terminal of the back to back diode switch and means for providing a inhibit circuit control signal comprising periodic pulses, wherein each pulse of the control signal has the same magnitude and duration as a clock signal pulse, such that the circuit operates as a synchronous inverter inverting each input pulse of the control signal at the output of the back to back diode switch.

5. A circuit according to claim 3, wherein the inhibit circuit further comprises a fifth diode having a first polarity region and a second polarity region, the fifth diode being connected together back to back with the third and fourth diodes such that the second polarity region of the fifth diode is connected to the second polarity regions of the third and fourth diodes, the output of the inhibit circuit being taken from the connection between the third, fourth and fifth diodes, a second input to the inhibit circuit is connected to the fifth diode, means for supplying an input clock signal to the first input terminal of the back to back diode switch, a second input of the inhibit circuit connected to the fifth diode, means for providing first and second inhibit control signals each comprising periodic pulses, wherein each pulse of the control signals has the same magnitude and duration as a clock signal pulse.

6. A circuit according to claim 5, wherein the third, fourth and fifth diodes are equally sized, such that the circuit operates as a logic NOR gate, providing the logical NOR of the first and second inhibit circuit control signals at the output of the back to back diode switch.

7. A circuit according to claim 5, wherein the third and fifth diodes are equally sized and the fourth diode is twice the size of each of the third and fifth diodes, such that the circuit operates as a logic NAND gate, providing the logical NAND of the first and second inhibit circuit control signals at the output of the back to back diode switch.

8. A circuit according to claim 3, further comprising a fifth diode with a first polarity region and a second polarity region connected to the back to back diode switch such that its first polarity region is connected to the first polarity region of the first diode and the first polarity region of the second diode, a second input terminal connected to the fifth diode such that taken together the first, second and fifth diodes operate as a logic OR gate, providing the logical OR of the first and second switch inputs, the input of the inhibit circuit comprising the output of sixth, seventh and eighth diodes each having a first polarity region and a second polarity region and connected together back to back such that the second polarity region of the sixth diode, the second polarity region of the seventh diode and the second polarity region of the eighth diode are all connected together, the eighth diode is twice the physical size of the sixth or seventh diode, a sixth diode input comiected to the sixth diode and a seventh diode input connected to the seventh diode, the first input to the inhibit circuit being taken from the connection between the sixth, seventh and eighth diodes, the eighth diode being connected to ground, the sixth and seventh diodes are connected to the first and second input terminals respectively, such that the circuit operates as a logic XOR gate, providing the logical XOR of the two input signals at the output of the circuit.

9. A circuit according to claim 3, further comprising fifth and sixth diodes each having first a polarity region and a second polarity region connected to the back to back diode switch such that the first polarity regions of the fifth and sixth diodes are connected to the first polarity regions of the first and second diodes, second and third input terminals connected to the fifth and sixth diodes respectively such that taken together the first, second, fifth and sixth diodes operate as a logic OR gate, providing the logical OR of the first, second and third inputs, the input of the inhibit circuit comprises the output of seventh, eighth, ninth and tenth diodes, each having a first polarity region and a second polarity region connected together back to back such that the second polarity regions of the seventh, eighth, ninth and tenth diodes are all connected together, the tenth diode being twice the physical size of each of the seventh, eighth or ninth diode, the input to the inhibit circuit is taken from the connection between the seventh, eighth, ninth and tenth diodes, a seventh diode input connected to the seventh diode, a eighth diode input connected to the eighth diode and a ninth diode input connected to the ninth diode, the tenth diode is connected to ground, seventh, eighth and ninth diodes are connected to the first, second and third input terminals respectively, a second output being taken from the connection of the eighth, ninth and tenth diodes, such that the circuit operates as a full adder circuit, operating on the three inputs, and providing a sum output on the output terminal of the circuit and a carry output on the connection between the eighth, ninth and tenth diodes.