WO2005006543A1

WO2005006543A1 - Systematic offset free operational amplifier and apparatus comprising such an operational amplifier

Info

Publication number: WO2005006543A1
Application number: PCT/IB2004/002233
Authority: WO
Inventors: Andrea Milanesi
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2003-07-10
Filing date: 2004-07-02
Publication date: 2005-01-20
Also published as: TW200518019A

Abstract

Apparatus (80) comprising an input stage (81) with an NMOS transistor doublet (N3, N4) having a first differential input (82.1, 82.2) for receiving input signals, and a PMOS transistor doublet (P1, P2) connected to the differential input (82.1, 82.2) for receiving input signals. The apparatus (80) further comprises a second stage (84) and current steering means (86) for balancing the current flow between the input stage (81) and the second stage (84) if an input voltage at the differential input (82.1, 82.2) reaches a lower or an upper supply rail.

Description

DESCRIPTION

SYSTEMATIC OFFSET FREE OPERATIONAL AMPLIFIER AND APPARATUS COMPRISING SUCH AN OPERATIONAL AMPLIFIER

Field of the invention

The present invention concerns operational amplifiers and systems, such as

LCD source drivers, based thereon.

Background of the invention

The liquid crystals (LC) of a liquid crystal display (LCD) are typically driven with an alternating driving voltage, referred to as LC voltage, whose peak-to-peak voltage is defined by a transmission-voltage curve 10, as depicted in Fig. 1. In this Figure, the transmittance vs. the LC voltage is depicted. The alternating LC voltage is used to avoid degeneration of the LCs. In order to obtain a desired gray level, the distance between the respective positive voltage peak 11 and the negative voltage peak 12 is to be kept at a constant voltage level referred to as VCOM. In Fig. 1 , the voltages applied on the LC are represented by the two arrows 11 and 12, the first arrow 11 pointing in the positive LC voltage direction and the second arrow 12 pointing in the negative LC voltage direction.

The LC voltage across the LC is subject to two different errors: - differential errors which may give as a result visible dim lines, - common mode errors, which usually result in flickering.

Fig. 2 shows the worst cases of four "pairs" of LC voltages that can occur in the source driver of an LCD, for a given offset. The driver output N has a positive differential error of 2*offset since both peaks 13 and 14 reach the respective maximum offset 17, and the driver output N+1 has a negative differential error of -2*offset since both peaks 15 and 16 reach the respective minimum offset 18. The total differential error between two adjacent LC lines N and N+1 , if the first line N is driven with YN and the second line N+1 is driven with Y_N+ι is:

4*θffS^βt (1 )

For these two driver outputs Y_N and Y ₊I the common voltage error is 0, because the average of the driving voltages 13 through 16 is equal to VCOM.

The driver outputs N+2 and N+3 do not have any differential error. The difference of the driving voltages 21 , 22 applied on the LC is equal to the difference of the two target voltages, they have, however, a common voltage error 25. The difference of the driving voltages 23, 24 is equal to the difference of the two target voltages, they have, however, a common voltage error 26. The driver output N+2 has a positive common error 25 of offset, and the driver output N+3 has a negative differential error 26 of - offset. The difference of the two common voltage errors 25 and 26 is:

YN_CO M_ERR- YN+I_COMM_ERR = 2^*offset (2)

For a given offset the maximum differential error voltage is twice the maximum common mode error.

The LC are far more sensible to differential voltages than to common mode voltages, so there is a need for a driving system that allows to provide precise differential LC voltages.

Liquid Crystals (LC) need to be driven with an alternate LC voltage, as explained above, that should have a low differential mode error. A very simple method to reduce differential mode errors is to drive the LC on both P and N sides with the same buffer. In an ideal case the buffer will have an offset, but this offset will be more or less constant along the output range. The voltage drop ΔV across the LC would be: ΔV - VgammaP ⁺ Voffset - (VgammaN ⁺ Voffset) ~ V_gammaP — V_garnrnaN (3)

with V_gamma_P. being the LC voltage at the P and N sides respectively. As one can derive from equation (3), one loses the dependence on the buffer offset, since the term +Vo fset - Votfeet is equal to zero. This strategy has been implemented on 6-bit drivers with rail-to-rail operational amplifiers. The drawback of this approach is, however, that close to the rails one of two input doublets of the source driver's input stage switches off, with the result of an even big differential error. On a 6-bit driver, the bit widths close to the rail are quite big. If the extra error does not exceed 1/3 of the bit width, on the LCD screen no visible effect will be seen.

The situation changes drastically with an 8-bit device. The bit width, in any part of the gamma curve (see Fig. 1), will be 4 times smaller. The precision of a traditional rail-to-rail operational amplifier is not enough for such an 8-bit device.

A standard input stage of a rail-to-rail amplifier 30 is depicted in Fig. 3. This Figure shows a common rail-to-rail input stage 30, composed by two transistor doublets. The first transistor doublet comprises two PMOS transistors P3, P4, and the second transistor doublet comprises two N OS transistors N1 , N2.

The input stage 31 has a differential input with negative and positive input terminals 32, 33. The outputs of the two transistor doublets are connected to the second stage 34 of the rail-to-rail amplifier 30. On the right hand side of

Fig. 3, the dynamic range of the two transistor doublets is illustrated. As one can see, only in the middle range 35 both transistor doublets are operable.

The saturation voltage Vsat indicated is the voltage drop needed by a current supply to work properly. VgsNMos and Vgs_PMos are the gate source voltages of the NMOS and PMOS transistors N1 through P4.

The total offset voltage present in the rail-to-rail amplifier 30, when all the devices are operable, is:

Noff_τoτ = Voffp + Noff _Ν + - K (4)

Where K is the offset contribution of the second stage 34 when one of the two transistor doublets N1 and N2, or P3 and P4 is switched off. GITIIST_STAGE = GITINMOS ⁺ mpMos ^ar|d GITINMOS ⁼ GTIPMOS is also considered in this equation (4), with Gm being the transconductance of the various suffixed elements. In this equation and in subsequent equations, the suffix N or NMOS refers to the NMOS transistors and the suffix P or PMOS refers to the PMOS transistors.

If one of the complementary transistor doublets of the input stage 31 switches off, the contribution to the offset of the 2nd stage 34 doubles, because the input transconductance GITIIST_STAGE halves. When one of the transistor doublets of the input stage 31 switches off and the Gm_NMos ≠ Gm Mos. if the offset contribution of the second stage 34 when the PMOS transistors N1 , N2 switch off is K, when the NMOS transistors P3, P4 switch off, the total offset is:

Voff_τoτ = Voffp + κ ^- (5) Gm_p

One now can calculate the maximum differential error Δerr :

Gm Gm

Δerr = Voff_P + K-^^ - (Noff_N + K) = Voff_p - Noff_N + K — 1 (6) Gm Gm_D

When both input MOS transistors work, the differential error is 0 if: Gmw = Gm_P, VoffN = Voffp. It is maximum when Voffw-vios = -VoffpMos, Gm_N ≠ Gm_P, and it is:

^Δerr _MAx = 2Voffp (7)

Prior art source drivers, as the one described in connection with Fig. 3, are not designed to provide the required precise differential LC voltages. Conventional amplifiers used in source drivers, for instance, do not provide for a constant offset over the whole input range.

The offset, as discussed so far was the Random Offset, but the Total Offset comprises two components:

Total Offset = Random Offset + Systematic offset

If the amplifier 30, for example, is well designed the systematic offset is negligible and the main offset component is the random offset. An exception may occur when one of the input doublets of the first stage 31 switches off. This may lead to a situation where the systematic offset is not negligible anymore and problems may be caused if the application is offset sensitive.

To better understand the way systematic offset is generated, in the following reference is made to a conventional circuit 40, depicted in Fig. 4. The circuit 40 comprises a folded cascode rail-to-rail operational amplifier when both input doublets are active. The Fig. 4 shows the currents balance in the different circuit branches. There are current generators depicted as 11 , 12, and 13. V s represent a level shifter needed to bias the output stage 41. In the present example, the output stage comprises the transistors P13 and N14. In a steady state the gate 42 of the transistor N14 will be at the same voltage as the gate 43 of the input stage mirror N11 , N12. The output current l_Nι₄ of the transistor N14 will be 3I * N where

with W being the width and L being the length of a transistor and with the suffixes indicating the respective transistors. The same happens to the upper side of the circuit where in a steady state the gate 44 of the transistor P13 will be at the same voltage as the gate 45 of the input stage mirror P5, P6. The output current l_P13 of the transistor P13 will be 3I ^* N where:

N ------ w ^{p 13} ^JP5-6 L P13 w P_t5-6

If all the device ratios are correct, when IN+ = IN- one has lpι₃ = I I4, the amplifier output current balance is correct and no systematic offset is present at the differential input IN+, IN-.

A different case is the one Fig. 5 shows, in which one of the input doublet of the circuit 50, namely the doublet N3, N4 is switched off, as schematically indicated by the two crossed lines. The case is the one in which the inputs IN+, IN- are close to the lower rail. Due to this, the NMOS doublet N3, N4 is switched off and in the upper current mirror P5, P6 a 21 current is flowing (instead of 31, in the previous case depicted in Fig, 4). If IN+ = IN- and the currents in the two branches of the input stage are perfectly symmetrical, as before seen in connection with Fig. 4, the gate 44 of P13 is at the same voltage as the gates 45 of the transistors P5, P6, hence l_Pι₃ = N*2I.

One has lpι₃ ≠ \HI and the output stage 41 is unbalanced. If a voltage VSY_S is applied between the inputs IN+ and IN-:

..- VIN+ + VSYS ^ Ipi3 - Iwi4

The voltage VSY_S applied to the differential input to balance the output stage current is called systematic offset.

A series of simulations of conventional circuits having an architecture similar to the ones depicted in Figures 4 and 5 reveal, that, due to the switching off of one of the input doublets, large offsets can be observed close to the rails. The simulations further reveal that the offset error gets larger the larger the voltage gets. This is caused by the fact that increasing the source drain voltage difference in a MOS device leads to a decrease of the drain output resistance. This in turn causes a drop the amplifier gain and a larger systematic offset.

Usually, a special circuit 61 is added at the input side of a driver 60 that maintains a constant input transconductance Gm. The special circuit 61 may comprise the transistors NA, PB, and PC, as illustrated in Fig. 6. The area ratio between PC and PB MOS, is 3, because to double the input transconductance of P1 , P2 transistors, one needs 4 times the drain current, due to the square root relation between transconductance (Gm) and bias current in MOS transistors (l_D):

Gm = .JμCox-- w — l_D

where μCox is the permeability of the oxide capacity, W is the width of the transistor and L is the length of the transistor. So, one needs to bias P1 , P2 input doublet with an 81 current when N3, N4 doublet is switched off.

One can notice that the output currents are more unbalanced than in the previous case (cf. Fig. 5). This means that one needs a larger input offset to regulate them; hence the operational amplifier will have an even larger systematic offset than before. This has been confirmed by respective simulations. The systematic offset worsens quite drastically if special circuit 61 is added at the input side.

As described above, the conventional circuits (cf. Figs. 4, 5 and 6) all have a systematic offset that close to the rails gets large. Such circuits are thus not well suited for applications where a constant offset is needed.

It is thus an objective of the present invention to improve amplifiers so that they have a constant offset over the whole input range.

It is another objective of the present invention to provide an amplifier that is better suited for being used in liquid crystal displays than conventional amplifiers.

In particular, the present invention is directed to an LCD source driver that substantially obviates the problems due to limitations and disadvantages of the related art.

SUMMARY OF THE INVENTION

These disadvantages of known systems, as described above, are reduced or removed with the invention as described and claimed herein.

An apparatus in accordance with the present invention is claimed in claim 1.

Various advantageous embodiments are claimed in claims 2 through 7.

Another apparatus in accordance with the present invention is claimed in claim

8.

Various advantageous apparatus are claimed in claims 9 and 10.

Additional features and advantages of the invention will be set forth in the description that follows, and in part will be apparent from the description.

Brief description of the drawings

For a more complete description of the present invention and for further objects and advantages thereof, reference is made to the following description, taken in conjunction with the accompanying drawings, in which:

FIG. 1 shows a typical Transmission Voltage Curve, as used in LCD displays; FIG. 2 shows the four driving voltages worst cases that can be present in a Source Driver of an LCD display; FIG. 3 is a block diagram of a conventional rail-to-rail input stage, as used in LCD displays; FIG. 4 is a block diagram of a conventional rail-to-rail operational amplifier, as used in LCD displays for example; FIG. 5 is a block diagram of the rail-to-rail operational amplifier of Fig. 4, where one of the input doublets is switched off; FIG. 6 is a block diagram of a conventional rail-to-rail operational amplifier with a special input circuit (constant input transconductance circuit), as used in LCD displays for example; FIG. 7 is a block diagram of a conventional LCD display; FIG. 8 is a schematic block diagram of a rail-to-rail input stage, according to the present invention, with first current steering means; FIG. 9 is a schematic block diagram of another rail-to-rail input stage, according to the present invention, with first and second current steering means; FIG. 10 is a schematic block diagram of yet another rail-to-rail input stage, according to the present invention, with first and second current steering means.

DESCRIPTION OF PREFERRED EMBODIMENTS

Before addressing detailed embodiments of the present invention, the typical block diagram of an LCD system is addressed.

Fig. 7 shows a typical block diagram of an LCD system. Low Voltage Differential Signaling (LVDS) is used as the interface between a host computer (not illustrated in Fig. 7) and a panel module 70. An LVDS receiver function 71 is typically integrated into a panel timing controller 72. A reduced swing differential signaling (RSDS) bus 73 is located between the panel timing controller 72 (TCON) serving as transmitting circuit and a source driver bank 74 serving as receiving circuit. RSDS is a trademark of National Semiconductor Corporation. The RSDS bus 73 is typically a differential bus that is eight pairs wide plus a clock pair and it may have a multidrop bus configuration. The source driver bank 74 comprises a plurality of RSDS source drivers 74.1. Typically, each source driver 74.1 of the source driver bank 74 serves n column electrodes (with n = 384 or 480, for example) of the display panel 76 by providing analog output signals. In the present example, each source driver 74.1 serves n=4 column electrodes only. There is a gate driver array 75 comprising an array of gate drivers 75.1. Several of the rows of the panel 76 are driven by any of these gate drivers 75.1. The gate drivers 75.1 are activated sequentially to turn on one row of pixels at a time, allowing analog voltages driven onto the columns to be applied to each row of pixels in series. The panel 76 may be a TFT-LCD panel with 640 pixels width and 480 lines (or rows) of pixels, for example. The source drivers 74.1 have interfaces using a differential clock signal (CLK+ and CLK-) received via the RSDS bus 73 to strobe the video data.

A TFT-LCD source driver 74.1 is a circuit that supplies LC voltages to LCD pixel columns. The function of a TFT-LCD source driver 74.1 is explained referring to Fig. 7. Digital video signals are inputted to the TFT-LCD source driver 74.1. In an active matrix type liquid crystal display panel 76 constituting a display apparatus 70, source lines 01 to ON and gate lines L1 to Livl are formed in an NxM matrix. At each intersection of the lines, a thin film transistor is disposed. The thin film transistors are not shown in Fig. 7. Voltages at the source lines 01 to ON are selectively supplied to pixel electrodes P via the thin film transistors. A gate driver 75.1 formed by a semiconductor integrated circuit delivers gate signals to the gate lines L1 to LM. In a horizontal scanning period, the source drivers 74.1 supply an alternating LC voltage (also referred to as reference voltage), which is generated in accordance with video data received via the differential bus 73. In other words, a source driver is a circuit that supplies video signals to an LCD pixel array. Since during production some of the columns of a display panel 76 may be defective, there are source driver banks 74 that comprises so-called repair buffers. In Fig. 7 one repair buffer 74.3 is shown. The display panel 76 comprises one column that is interrupted, as indicated by the circle 76.1. In order to be able to use this panel 76 despite the defect, the defective column, after it has been localized during testing, is repaired by connecting an output 74.4 of the repair buffer 74.3 to one section of the column and an input 74.5 of the repair buffer 74.3 of the output of the respective source driver 74.1 that drives the defective column. To allow a defective panel 76 to be used, typically a bunch of wirings are positioned at the edges of the panel and fuses are provided that can be activated by a laser beam. This allows a repair buffer to be connected to those columns that are found to be defective. A typical source driver bank 74 comprises up to four repair buffers.

According to the present invention, circuits are provided that do not suffer a systematic offset over the whole range of the differential input signal. These kind of circuits are very well suited for being used as repair buffers.

In the following sections, operational amplifiers are addressed which have a rail-to-rail input stage and, in accordance with the present invention, do not suffer a systematic offset on the whole input range.

In accordance with CMOS technology, the apparatus comprises a plurality of MOS transistors of both the NMOS and PMOS type. In the drawings and in the description, the NMOS transistors are designated with the prefix N and the PMOS transistors are designated with the prefix P. The present invention can also be realized using bipolar technology or field-effect transistors (FETs).

Figure 8 illustrates how to obtain a constant offset with a rail-to-rail input stage A first apparatus in accordance with the present invention is depicted in Figureδ. In this Figure, an input stage 80 of a source driver is depicted. The input stage 80 comprises an NMOS transistor doublet N3, N4 with a differential input 82.1 , 82.2 for receiving analog input signals ln+, In-. The input stage 80 furthermore comprises a PMOS transistor doublet P1, P2, as depicted in Fig. 8.. A first current generator l₂ is provided in order to bias the PMOS transistor doublet P1, P2, and a second current generator l₃ is provided in order to bias the NMOS transistor doublet N3, N4. The first current generator l₂ is connected to the source node 87.2 of the transistors P1 , P2, and the second current generator l₃ is connected to the source node 87.1 of the transistors N3, N4.

Fig. 8 shows a situation where the NMOS transistor doublet N3, N4 is switched off. Such a situation always occurs when the differential input signal reaches the lower supply rail. The drain nodes 85.1 through 85.4 of the four transistors N1 , N2, P3, P4 are connected to a second stage 84. The second stage 84 typically comprises an amplifier. According to the present invention, current steering means 86 are provided in order to steer the bias current of the switched off input stage doublet to the second stage 84 to preserve a correct current balance in all the branches of the second stage 84. In the present example, the current steering means 86 ensure that the current I flows through the connections 85.1 , 85.2 out of the second stage even if the NMOS transistor doublet N3, N4 is switched off. The current steering means 86 pull the current out of the second stage 84. As depicted in Fig. 8, the current steering means 86 steers the bias current l₃ of the switched off N3, N4 doublet into the original branches to maintain the optimal biasing of the second stage 84.

If one also wants to compensate/prevent a systematic offset if the differential input signal reaches the upper supply rail, a second current steering means would have to be added to the circuit 80 of Fig. 8. This second current steering means would ensure that the current I flows through the connections 85.3, 85.4 into the second stage even if the PNMOS transistor doublet P1, P2 is switched off.

This current steering means can be implemented in different manners. The current steering means 86 may comprise active devices or switches, for example.

A second apparatus 90 in accordance with the present invention is depicted in Figure 9. Current steering means 96.1 comprising two transistors NA and NB and current steering means 96.2 comprising two transistors PA and PB are added to the first stage 91. The gate 92.1 of the two transistors NA and NB is connected to a first reference voltage Vrefa and the gate 92.2 of the two transistors PA and PB is connected to a second reference voltage Vrefb (with lower supply rail < Vrefa < Vrefb < upper supply rail). When the differential input voltage at the input 93.1 , 93.2 is lower than the first reference voltage Vrefa, the NMOS input doublet N3, N4 switches off and the current steering means 96.1 pull the current l₃ (two times I) out of the second stage 94. This behavior is herein referred to as balancing the output currents. The schematics in Fig. 9 show the circuital embodiment for the lower rail and upper rail. The current steering means 96.2 are a complementary circuit to the current steering means 96.1 and are designed to correct the systematic offset when the differential input voltage at the input 93.1, 93.2 is close to the upper supply rail, that is above the second reference voltage Vrefb. The complementary circuit 96.2 is similar to the circuit 96.1. When the differential input voltage at the input 93.1 , 93.2 is greater than the second reference voltage Vrefb, the PMOS input doublet P1 , P2 switches off and the current steering means 96.2 push the current l₂ (two times I) into the second stage 94. Further details of the second embodiment are outlined in the following. The input stage 91 comprises, as mentioned above, the NMOS transistor doublet N3, N4 with a differential input 93.1, 93.2 for receiving input signals IN+, IN-. The input stage 91 furthermore comprises a PMOS transistor doublet P1 , P2 also being connected to the differential input 93.1 , 93.2 for receiving input signals IN+, IN-. A current generator l₂ provides a bias current for the transistor doublet N3, N4 and a current generator l₃ provides a bias current for the transistor doublet P1, P2. The first current generator l₂ is connected to the source node 97.2 of the transistors P1 , P2, and the second current generator l₃ is connected to the source node 97.1 of the transistors N3, N4. The drain nodes 95.1 through 95.4 of the four transistors N1 , N2, P3, P4 are connected to a second stage 94.

The output stage 92 comprises the transistors P5, P6, P7, P8, P13 and N9, N10, N11 , N12, N14. The output stage 92 comprises a class AB output section composed by the transistors P8, N10, P13, and N14. The transistors P8 and N10 serve as voltage level shifters for biasing properly the gates of the two output transistors P13 and N14, in order to control their steady state bias current. The transistors P5, P6, P7, P8 and the transistors N9, N10, N11 , N12 each are arranged as cascaded high compliance current mirrors.

Fig. 10 shows a third embodiment 100. The embodiment 100 is a full rail-to-rail implementation of the present invention and it comprises an input stage 101 followed by a second stage 104. The circuit 100 is more complex, but besides having a corrected systematic offset, provides a constant input transconductance Gm on the whole input range. Besides it has a smaller current consumption, than the circuit of Fig. 6. In this example the current consumption increases to 41 (the current flowing in the PD, PE current mirror) because one doubles the area of the input transistor P1 , P2 with the extra transistors PA, PB (which should be of the same dimension of PI, P2). In the circuit 60 of Fig. 6 the current consumption increases at least 81 (the current flowing in the mirror PB, PC) without taking into account the current increase of the unbalanced output stage, which could be not negligible.

Here the case is described where the NMOS input doublet is switched off: in the circuit 100, when the differential input voltage at the input nodes 103.1, 103.2 is lower than Vrefa, the input NMOS doublet N3, N4 switches off, as schematically indicated in Fig. 10. A first current generator l₂ is connected to the source node 107.2 of the transistors P1 , P2, and a second current generator l₃ is connected to the source node 107.1 of the transistors N3, N4. The bias current l₃ is steered in a second PMOS input doublet PA, PB, which bias the second stage nodes 105.1, 105.2 through the two NF, NG and NH, NI current mirrors. When the differential input voltage is greater than Vrefb, the input PMOS doublet P1 , P2 switches off. The bias current l₂ is in this case steered in a second NMOS input doublet NA, NB, which bias the second stage nodes 105.3, 105.4 through the two PF, PG and PH, PI current mirrors. The two current steering means comprise the following transistors NC, PD, PE, NF, NG, NH, NI and PC, ND, NE, PF, PG, PH, PI, respectively.

If P1=P2=PA=PB, the input transconductance Gm stays constant. Of course the input transconductance Gm of the PMOS doublet P1, P2 should be designed equal to the one of the NMOS input N3, N4. A complementary case happens when the input voltage is close to the upper rail. When it exceeds Vrefb, the input doublet P1 , P2 switches off and the current l₂ it is steered into PC, which provides the current to NA, NB through the current mirror NI, NH as described in the previous case. NA and NB now steer the bias current in 105.1 , 105.2 nodes by means of the PF, PG and PH, PI current mirrors, maintaining the current balance in the circuit. As Before, it is preferred to have a constant Gm N3=N4=NA=NB.

Current steering means are provided that, according to the present invention, steer the bias currents (l₂ and/or l₃) in order to balance the current flow between the input stage and the second stage if an input voltage at the differential input reaches a lower supply rail or an upper supply rail.

According to the present invention, the current steering means comprise at least one transistor doublet (e.g. NA, NB; PA, PB; PD, PE; ND, NE), which are connectable to a reference voltage node (e.g., Vrefa; Vrefb) in order to initiate the steering of the bias current. The result of various simulations of the circuits shown in Figs. 8, 9, and 11 confirm that the systematic offset close to the rail completely disappears. Simulation results show that the circuit 100, after the current steering means have been added shows no systematic offset close to the upper and lower supply rails.

As explained above, and as can be derived from the Figures, the invention can be used in repair buffers, as employed in LCD display systems. An apparatus, according to the present invention, is well suited for being used in thin film transistor liquid crystal display (TFT-LCD) source drivers, for example, since these drivers require repair buffers with a high precision differential voltage in order to drive the flat display to avoid visual defects or artifacts.

The inventive circuitry is well suited for use in source driver for display applications with present (VGA to UXGA) and future display resolutions.

The present invention allows the design of an operational amplifier without systematic offset over the whole input/output range. An apparatus, according to the present invention, provides a high precision differential voltage. Since the systematic offset becomes more prominent the smaller the signal swing of the differential input signal gets, the current steering means are well suited for employment in low voltage supply rail-to-rail applications. Typical examples of low voltage supply rail-to-rail applications are portable applications where due to the limited capacity of the supply domain there is a tendency to operate at low supply voltages.

It is appreciated that various features of the invention which are, for clarity, described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features of the invention which are, for brevity, described in the context of a single embodiment may also be provided separately or in any suitable subcombination.

In the drawings and specification there has been set forth preferred embodiments of the invention and, although specific terms are used, the description thus given uses terminology in a generic and descriptive sense only and not for purposes of limitation.

Claims

1. Apparatus (70; 80; 90; 100) comprising an input stage (81; 91; 101) with a differential input (82.1 , 82.2; 93.1 , 93.2; 103.1 , 103.2) for receiving input signals and a second stage (84; 94; 104), said input stage (81; 91; 101) comprising: - an NMOS transistor doublet (N3, N4) being arranged such that their source nodes (87.1; 97.1 ; 107.1) are connected to a common current generator (l₃) for providing a first bias current (l₃) and their drain nodes (85.1, 85.2; 95.1, 95.2; 105.1, 105.2) are separately connectable to the second stage (84; 94; 104), - a PMOS transistor doublet (P3, P4) being arranged such that their source nodes (87.2; 97.2; 107.2) are connected to a common current generator (l₂) for providing a second bias current (l₂) and their drain nodes (85.3, 85.4; 95.3, 95.4; 105.3, 105.4) are separately connectable to the second stage (84; 94; 104), and - first current steering means (86; 96.1) for steering the first bias current (l₃) in order to balance the current flow between the input stage (81 ; 91 ; 101) and the second stage (84; 94; 104) if an input voltage at the differential input (82.1 , 82.2; 93.1 , 93.2; 103.1 , 103.2) reaches a lower supply rail, and/or - second current steering means (96.2) for steering the second bias current (l₂) in order to balance the current flow between the input stage (81 ; 91 ; 101) and the second stage (84; 94; 104) if an input voltage at the differential input (82.1 , 82.2; 93.1 , 93.2; 103.1 , 103.2) reaches an upper supply rail.

2. The apparatus (70; 80; 90; 100) of claim 1 , wherein the first current steering means (86; 96.1) pull currents out of the second stage (84; 94; 104) if the NMOS transistor doublet (N3, N4) is switched off.

3. The apparatus (70; 80; 90; 100) of claim 1 or 2, wherein the second current steering means (96.2) push currents into the second stage (84; 94; 104) if the PMOS transistor doublet (P1 , P2) is switched off.

4. The apparatus (70; 80; 90; 100) of claim 1, 2 or 3, wherein - the NMOS transistor doublet (N3, N4) comprises two NMOS transistors, each having a gate, whereby the gate of the first of the two NMOS transistors is connectable to a first input node (IN+; 82.2; 93.2; 103.2) of the differential input and the gate of the second of the two NMOS transistors is connectable to a second input node (IN-; 82.1 ; 93.1 ; 103.1), - the PMOS transistor doublet (P1 , P2) comprises two PMOS transistors, each having a gate, whereby the gate of the first of the two PMOS transistors is connectable to the first input node (IN+; 82.2; 93.2; 103.2) and the gate of the second of the two PMOS transistors is connectable to the second input node (IN-; 82.1 ; 93.1 ; 103.1).

5. The apparatus (70; 80; 90; 100) of claims 1 , 2, 3 or 4, wherein said current steering means comprise at least one transistor doublet NB; PA, PB PD, PE; ND, NE), said at least one transistor doublet (NA, NB; PA, PB PD, PE; ND, NE) being connectable to a reference voltage node (Vrefa^' Vrefb) in order to initiate the steering of the bias current.

6. The apparatus (/O; 80; 90; 100) of claim 1 , wherein the input stage (81 ; 91 ; 101) is a rail-to-rail input stage.

7. The apparatus (100) of claim 1 , 2, or 3, wherein the first current steering means and the second current steering means provide for a constant input transconductance (Gm) on the whole input signal range.

8. Apparatus comprising a source driver bank (74) with at least one apparatus (74.3) according to one of the previous claims, and further comprising a bus (73) for receiving input signals.

9. The apparatus of claim 8, further comprising a gate driver bank (75), an LCD panel (76), and wiring (74.4, 74.5) that is connectable to said at least one apparatus (74.3).

10. The apparatus of claim 8 or 9 being part of a panel module (70).