WO2005001930A1

WO2005001930A1 - Integrated circuit with an integrated heat sink

Info

Publication number: WO2005001930A1
Application number: PCT/IB2004/051001
Authority: WO
Inventors: Guoqiao Tao; Frederikus G. Kuper
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2003-06-27
Filing date: 2004-06-24
Publication date: 2005-01-06

Abstract

An integrated circuit comprising an integrated heat sink. The integrated heat sink comprises a global thermally conducting layer consisting of an electrically isolating material and/or a local thermally conducting structure covering at least a portion of a heat source in said integrated circuit, said structure extending towards regions of lower power dissipation within said integrated circuit.

Description

Integrated circuit with an integrated heat sink

The present invention relates to an integrated circuit (IC or chip) comprising an electronic device. Up to now, the development of ICs has been concentrated on more functionality and higher integration density of the devices on the ICs. As the integration density increases, chips are consuming more and more power. Whereas, thermal properties became more and more important in packaging technology, there has been a little attention paid to the thermal performance of the IC by itself. For example, analogue electronic devices such as resistors are extensively used in analogue ICs and in ICs comprising both analogue and digital elements (mixed elements). In Fig. 11 a typical resistor layout 1100 is schematically shown in a plan view, section (A), and a cross sectional view, section (B). In common practice resistors 1100 are made ofpolycrystalline salicided (self aligned suicide) layers 1116 and/or unsalicided (suicide) layers 1114, hereinafter referred to as poly layer 1118, laminated onto an electrically isolating layer of SiO₂ 1112, hereinafter also referred to as LOCOS (local oxidation of silicon). The LOCOS layer is formed on a silicon substrate (wafer, not shown) in a commonly known oxidation layering process. In advanced processes the LOCOS layer may be replaced by a trench isolation layer, hereinafter also referred to as STI (shallow isolation layer). Depending on the application such resistors consume a certain amount of power and, thus, produce heat (power dissipation) at localized spots (heat sources) during operation. In Fig. 11 section (C), a corresponding temperature profile 1130 across the resistor 1100 at maximum power supply is illustrated, whereupon the highest temperature can be found in the middle of the resistor 1100 and the highest temperature gradient can be found near the salicided-unsalicided poly layer interface. However, the reliability and lifetime of such a resistor 1100 is very much depending on both the absolute temperature and the temperature gradient: on the one hand, when the absolute temperature is too high the resistance value can deviate dramatically from its designed value due to the temperature dependence of the resistor. On the other hand, if the resulting temperature gradient in the area of the resistor is too high the salicided part of the poly layer may be degraded causing a permanent (non-reversible) change of the total resistance. Both may result in performance degradation of the circuit, malfunctioning, and even shorter lifetime of the chip. Similar effects apply to other integrated analogue devices such capacitors, or inductors or the like. Integrated digital or active devices such as diodes, transistors or any other heat sources within the chip are concerned by this problem as well. According to current IC design the maximum power dissipation per unit area therefore usually is limited in order to reduce the risk of damages. However, this is at the expense of circuit integration density.

An object of the present invention is to provide an integrated circuit allowing for high integration density without the risk of a thermal impact on the function of the IC. According to a first aspect of the present invention this object is achieved by an integrated circuit comprising an integrated heat sink. Due to the arrangement of electronic devices in common IC designs the power dissipation and, hence, the internal temperature distribution is not homogeneous. In an IC according to the present invention the integrated heat sink internally dissipates heat locally generated by such electronic devices (heat sources) by dispersing the thermal energy across the heat sink. The layout of the chip and the heat sink is designed in such a way that a predetermined amount of thermal energy is collected at the location of the heat source. To this end, the heat sink may comprise an integrated local thermally conducting structure, an integrated global thermally conducting layer made of electrically isolating material, or a combination thereof. Integrated local thermally conducting structure in this regard denotes one or several sections consisting of a material with better thermal conductivity than the surrounding materials. These sections can be implemented for example in the form of a sheet and/or in the form a grid. These sections approximate (or cover) a single electronic device, one or more portions thereof, or a plurality of electronic devices which are, for example, arranged in a common area or which constitute a functional entity, whereas, the integrated global layer covers the entire chip. The bigger the solid angle of the heat source covered by the local structure or the global layer, i.e. the closer the approximation and/or the bigger the surface of the structure/layer facing the heat source, the more heat is collected. Therefore, the global thermally conducting layer and the thermal conducting structure, if its material is not electroconductive, preferably should be connected directly to the electronic device. If the material of the thermally conducting structure is electroconductive, an intermediate electrically insulating layer should be provided. The layout of the chip according to the present invention is further designed in such a way that the collected thermal energy is dispersed to regions of lower power dissipation within the IC. In case of the integrated local thermally conducting structure this is achieved either by an extension of this structure towards regions of lower power dissipation, by thermally connecting the structure to a metallic wire of the IC, by thermally connecting the structure to the silicon substrate (wafer) of the IC, or by any combination of these solutions. It is a fact, that the larger the extension of the structure, i.e. the larger the volume and the surface of the heat sink the more homogeneous the temperature distribution will be. By connecting the structure to a metallic wire, advantage is taken of the good thermal conductivity and the large extension of the wiring within the chip, which wiring by this means is integrated in the heat sink. By connecting the structure to the waver of the IC advantage is taken of the good thermal conductivity and the extension of the silicon substrate. By this means, the heat will be transported essentially across the entire chip. Likewise, the global thermally conducting layer due to its extensions spreads the heat essentially across the entire chip. As a result, in an IC according to the present invention temperature is distributed more homogeneous and the absolute temperature and the temperature gradient in the area of the electronic device is reduced. This means that the integration density and/or the local power dissipation can be increased without bearing the risk of damages to the IC. Furthermore, reliability and lifetime of such an IC can be improved. According to a preferred embodiment of the present invention said thermally conducting structure comprises a metal layer. According to another preferred embodiment of the present invention said thermally conducting structure comprises a silicon layer. According to another preferred embodiments of the present invention said thermally conducting structure and/or said global thermally conducting layer comprise Al₂O₃. According to another preferred embodiments of the present invention said thermally conducting structure and/or said global thermally conducting layer comprise diamond. The above and other objects, features and advantages of the present invention will become apparent from the following description of preferred embodiments thereof taken into conjunction with the accompanying drawings in which Fig. 1 sections (A) and (B) show a plan view and a cross sectional view of a resistor in an IC according to a first embodiment of the present invention and section (C) shows a temperature distribution thereof; Fig. 2 sections (A) and (B) show a plan view and a cross sectional view of a resistor in an IC according to a second embodiment of the present invention and section (C) shows a temperature distribution thereof; Fig. 3 sections (A) and (B) show a plan view and a cross sectional view of a resistor in an IC according to a third embodiment of the present invention and section (C) shows a temperature distribution thereof; Fig. 4 sections (A), (B), and (C) show a plan view and two cross sectional views of a resistor in an IC according to a fourth embodiment of the present invention and section (D) shows a temperature distribution thereof; Fig. 5 sections (A), (B), and (C) show a plan view and two cross sectional views of a resistor in an IC according to a fifth embodiment of the present invention and section (D) shows a temperature distribution thereof; Fig. 6 sections (A) and (B) show a plan view and a cross sectional view of a resistor in an IC according to a sixth embodiment of the present invention and section (C) shows a temperature distribution thereof; Fig. 7 sections (A) and (B) show a plan view and a cross sectional view of a resistor in an IC according to a seventh embodiment of the present invention and section (C) shows a temperature distribution thereof; Fig. 8 sections (A) and (B) show a plan view and a cross sectional view of a resistor in an IC according to an eighth embodiment of the present invention and section (C) shows a temperature distribution thereof; and Fig. 9 sections (A) and (B) show a plan view and a cross sectional view of a resistor in an IC according to a ninth embodiment of the present invention and section (C) shows a temperature distribution thereof; and Fig. 10 sections (A) and (B) show a plan view and a cross sectional view of a resistor in an IC according to a tenth embodiment of the present invention and section (C) shows a temperature distribution thereof; and Fig. 1 1 sections (A) and (B) show a plan view and a cross sectional view of a resistor in a state of the art IC and section (C) shows a temperature distribution thereof.

The resistor 100 shown in Fig .1 sections (A) and (B) is made of a polycrystalline layer 118, that can be a salicided 116 and/or unsalicided layer 114 laminated onto an electrically isolating LOCOS/STI layer 112. In order to protect the polysilicon from silicidation a protection mask against silicidation is used. The LOCOS/STI layer 112 is formed on a silicon wafer (not shown). The poly layer is electrically connected via metal wires 120 and 122. This arrangement is embedded in an insulating inter layer dielectric (ILD) filling the interspace between the electrically active layers and wires. The ILD is typically made of SiO₂ which is easy to process but has a low thermal conductivity. The layout, so far, is identical in all embodiments described below unless differences are explicitly indicated. In this embodiment the polysilicon resistor is formed at the same time with the polysilicon gates in a complementary metal oxide semiconductor (CMOS) process. The polysilicon resistor can be doped with an n-type doping atom like As, P or Sb, or a p-type doping atom like B or In. The polysilicon resistor can comprise more than one polysilicon layer. The polysilicon layers are usually doped as high as possible with e.g. As doping atoms. The type of doping atom, the concentration of doping atoms and the polysilicon grain sizes determine the resistivity of the polysilicon resistor. They are also responsible for the variation in resistance as a function of temperature. When the temperature increases, the mobility drastically decreases. The resistance value of the polysilicon resistor is therefore temperature dependent. For example, a resistor of 52 Ohm, with a width and length of 20 and 6.35 μm respectively and a maximum current allowed of 20 mA generates a power dissipation density of 0.16 mW/μm². The self- heating due to such power dissipation density can go easily up to 100 degrees above the ambient temperature. It has been observed that the sheet resistance of a p-type polysilicon resistor increased significantly (up to about 30%) after a lifetime DHTL test. According to the first embodiment of the present invention the integrated heat sink is implemented in a conventional semiconductor process (without additional cost) by a local thermally conducting structure consisting of two metal sections 124 and 126. This structure is provided in the nearest metal wire layer, whereby each metal section 124, 126 can be seen as extension of the metal wires 120, 122. In other words, the metal sections 124, 126 are thermally connected to the corresponding wires 120 and 122, respectively. Both metal sections cover a portion of the poly layer 118 of the resistor 100. These sections can for example be implemented in the form of a continuous sheet of metal and/or in the form a grid of metal lines. Heat generated by the resistor 100 is conducted via a short distance 128 through the isolating ILD towards the metal sections 124, 126. Since the thermal conductivity of metal is much higher than that of the surrounding SiO₂ material the collected thermal energy is instantly spread over the entire metal layers thereby reducing the local temperature. According to this embodiment the metal sections 124, 126 extend into the direction perpendicular to the resistor 100 in order to enlarge the volume and the surface of the heat sink. Due to the thermal connection to the wires 120, 122 the energy is transported via these wires towards an extended region defined by the entire wiring of the chip (not shown). The resulting temperature distribution is shown in section (C) of Fig. 1, wherein a solid line 130 indicates the temperature distribution across the resistor 100 without heat sink (compare Fig. 9 (C)) and a dashed line 132 indicates the temperature distribution with the heat sink shown in sections (A) and (B). In the areas covered by the metal sections 124, 126 both the absolute temperature and the temperature gradient (at the salicided/unsalicided interface) decreases. As a result, also the absolute temperature in the middle of the resistor 100 decreases as indicated by arrow 134. Hence, the heat sink according to this embodiment is a simple way to improve the performance and reliability of the resistor. According to the second embodiment of the present invention shown in Fig. 2 a thermally conducting structure is provided having a single metal section 224, only. Correspondingly, the metal section 224 is thermally connected with a single wire 220 and covers an asymmetrical portion of the poly layer 218 on the left hand side, only. In the resulting temperature distribution shown in section (C) of Fig. 2, dashed line 232 indicates the resulting temperature distribution. The temperature distribution is asymmetrical due to the asymmetrical portion of the resistor covered by the metal section 224. However, again both the absolute temperature and the temperature gradient decreases compared with the temperature distribution without heat sink. The layout according to a third embodiment of the present invention is shown in Fig. 3. According to this embodiment a thermally conducting structure with a single metal section 324 is provided covering the center portion of the poly layer 318. The difference to the former embodiments is that this metal section 324 is not thermally connected to any of the metal wires 320, 322. Thereby, no advantage is taken of the good thermal conductivity of the metallic wires. Nevertheless, according to the resulting temperature distribution (dashed line 332) shown in section (C) of Fig. 3 the absolute temperature in the middle of the resistor can be reduced more effectively compared to the first embodiment, see arrow 334. However, this is at the expense of a higher temperature gradient at the salicided/unsalicided poly interface. According to a forth embodiment of the present invention shown in Fig. 4, the efficiency of the heat sink according to Fig. 3 can be improved by thermally connecting the metal layer 424 to the silicon substrate 440 as shown in section (C) of Fig. 4. Thereby, advantage is taken of the good thermal conductivity of the silicon substrate. A connection between the metal layer 424 and the substrate 440 can be facilitated for example by using the nearest thermal conducting structure in the present layout such as local interconnect layers (LIL) 436, 438 on the silicone substrate 440 parallel to the resistor 400. These LILs typically are metal layers. An additional advantage of this embodiment is that the surface of the local structure facing the heat source 500 is considerably enlarged compared with the embodiment according to Fig. 3 by integrating the LILs 436, 438 as part of the local structure of the heat sink. Therefore, more thermal energy can be collected. The comparison with the resulting temperature distribution in Fig. 3 (C) shows that the absolute temperature and the temperature gradient again could be reduced, see dashed line 432 and arrow 434 in section (D) of Fig. 4. The fifth embodiment of the present invention shown in Fig. 5, solely utilizes the nearest thermal conducting LIL structure in the present layout 536, 538 parallel to the resistor 540 being connected to the silicone substrate. Since there is no metal section covering the resistor 500 the total surface of the local structure facing the heat source is reduced compared to that shown in Fig. 4. However, a reasonable efficiency can be obtained with a heat sink according to this embodiment, see Fig. 5 section (D). Figs. 6 and 7 show two embodiments of the present invention wherein the local thermally conducting structure of the heat sink comprises a poly layer section 642, 744, respectively. The salicided/unsalicided poly layer material has a better thermal conductivity than SiO₂. In one case, Fig. 6, the poly layer section 642 is arranged above the resistor/heat source 600 within the inter layer dielectric (not shown). In the other case, Fig. 7, the poly layer section 744 is arranged below the resistor/heat source 700 within the LOCOS/STI layer. In both cases the poly layers are very close to the heat source in order to increase the solid angle and to reduce the thickness of the thermally insulating SiO₂ layer filling the interspace. Since salicide and/or suicide is not electrically isolating the additional poly layers can, however, not directly be laminated onto the resistor. Although the poly layers sections 642, 744 are much closer to the heat source the cooling effect (absolute temperature reduction as well as temperature gradient reduction) is not better than that obtained in the embodiments using local metal structures, see Fig. 6 and 7 section (C) because the thermal conductivity of the poly layer material is not as good as that of metal. Any combinations of the local thermally conducting structures described above are possible provided the electrical properties of the layout are not affected. One example is shown in Fig. 8 combining a heat sink comprising one central metal section 824 according to the third embodiment of the invention with a heat sink comprising one additional poly layer section 844 according to the seventh embodiment of the invention. Further, the usage of materials is not limited to metal, salicide, or suicide. Any thermally conducting material may be applied. Preferably, Al₂O₃ or diamond may be applied which can be directly connected to the heat source due to its electrically isolating properties and which are excellent thermal conductors. The thermal conducting structures are not limited to the sections and shapes shown with reference to the above embodiments. Depending on the layout of the chip the section(s) defined by the local thermally conducting layers may be increased and/or may additionally extend in any other direction within the chip in order to enlarge the volume and surface of the heat sink. Further, the number of sections belonging to the local thermally conducting layers can be increased. According to the embodiments of the invention shown in Figs. 9 and 10, the integrated circuit comprises an integrated heat sink with a global thermally conducting layer consisting of an electrically isolating material. In case of the embodiment according to Fig. 9 this global layer 950 replaces the LOCOS/STI layer 950. In case of the embodiment according to Fig. 10 the global layer 1060 replaces the interlayer dielectric. Whereas both ILD and LOCOS commonly consist of SiO₂, for layers 950, 1060 according to the present invention thermally conducting materials, such as Al₂O₃ or diamond are applied. These materials are also electrically isolating but compared to SiO₂ they have excellent thermal conducting properties. Since these integrated global layers are electrically isolating they can be attached directly to a large surface of the heat source 900, 1000, respectively. This means provides for an optimum collection of thermal energy. Furthermore, since these integrated global layers 950, 1060 cover the entire chip a very good dispersion of the collected energy over the entire chip is achieved. According to the embodiment shown in Fig. 9 the layer 950 is attached directly to the silicon substrate 940 which is a good thermal conductor by itself, thereby further improving the dispersion of the thermal energy. Therefore, in both embodiments excellent thermal performance can be expected, as can be seen in sections (C) of Figs. 9 and 10. The application of such materials is not limited to the layers as described in connection with Figs. 9 or 10. They can be used as field oxide, Shallow trench oxide, interlayer dielectric, gate dielectric, or inter-metal dielectrics as well. Further, ICs according to this invention may have several global thermally conducting layers as integrated heat sinks. And global thermally conducting layers can be combined with any local thermally conducting structure as described above. The heat sinks according to this invention is applicable to any kind of heat sources within an integrated circuit such as integrated analogue devices (resistors, capacitors, and inductors) and integrated digital (active) devices (diodes, transistors) or the like.

Claims

CLAIMS:

1. An integrated circuit comprising an integrated heat sink.

2. An integrated circuit according to claim 1, wherein said integrated heat sink comprises a global thermally conducting layer consisting of an electrically isolating material.

3. An integrated circuit according to claim 1 or 2, wherein said integrated heat sink comprises a local thermally conducting structure covering at least a portion of a heat source in said integrated circuit, said structure extending towards regions of lower power dissipation within said integrated circuit.

4. An integrated circuit according to anyone of the claims 1 to 3, wherein said integrated heat sink comprises a local thermally conducting structure covering at least a portion of a heat source in said integrated circuit, said structure being thermally connected to a metallic wire of said integrated circuit.

5. An integrated circuit according to anyone of the claims 1 to 3, wherein said integrated heat sink comprises a local thermally conducting structure covering at least a portion of a heat source in said integrated circuit, said structure being thermally connected to a silicon substrate of said integrated circuit.

6. An integrated circuit as claimed in claims 3 to 5, wherein the heat source is a polysilicon resistor.

7. An integrated circuit as claimed in claims 3 to 5, wherein the heat source is a field effect transistor.

8. An integrated circuit as claimed in claims 3 to 5, wherein the heat source is a bipolar transistor.

9. An integrated circuit as claimed in claim 4, 6, 7 or 8, wherein the metallic wire is the first metallization layer on top of the heat source.

10. An integrated circuit as claimed in anyone of the preceding claims, characterized in that the integrated circuit comprises MOS transistors.

11. An integrated circuit according to anyone of claims 3 to 5, wherein said local thermally conducting structure comprises a metal section.

12. An integrated circuit according to anyone of claims 3 to 5, wherein said local thermally conducting structure comprises a silicon section.

13. An integrated circuit according to anyone of claims 3 to 5, wherein said local thermally conducting structure comprises an Al₂O₃ section.

14. An integrated circuit according to anyone of claims 3 to 5, wherein said local thermally conducting structure comprises a diamond section.

15. An integrated circuit according to claim 2, wherein said global thermally conducting layer consists of Al₂O₃.

16. An integrated circuit according to claim 2, wherein said global thermally conducting layer consists of diamond.