WO2004109710A1

WO2004109710A1 - Virtual grounding type non-volatile memory enabling test depending on adjacent cell state

Info

Publication number: WO2004109710A1
Application number: PCT/JP2003/007103
Authority: WO
Inventors: Kazuhiro Kurihara
Original assignee: Fujitsu Limited
Priority date: 2003-06-05
Filing date: 2003-06-05
Publication date: 2004-12-16
Also published as: JPWO2004109710A1

Abstract

It is possible to improve throughput of the operation test step. A drain current detection circuit (12) is connected to a first bit line (BL1) connected to a selection cell transistor (MSO). In the configuration for detecting a drain current (Id) of the selection cell transistor, a current circuit (10) is provided for virtually increasing/decreasing the drawing current (Id) detected by the drain current detection circuit. Accordingly, during an operation test, it is possible to virtually reproduce the drain current state depending on the data pattern by the current circuit without writing a predetermined data pattern into the adjacent cell transistors (MC1, MC2). Consequently, it is possible to perform the operation test depending on the data pattern without writing any data pattern.

Description

Description: Virtually grounded non-volatile memory enabling test depending on the state of adjacent cells

The present invention relates to a virtual ground type nonvolatile semiconductor memory, and more particularly, to a virtual ground type nonvolatile memory which enables an operation test depending on the state of an adjacent cell. Background art

The flash memory, which is one of the non-volatile semiconductor memories, includes a memory cell type having a conductive floating gate surrounded by an oxide film between a control gate and a semiconductor substrate. There is a type of memory cell in which an oxide film, a nitride film, an oxide film, or the like is formed between the gate and the semiconductor substrate, and a nitride film as an insulating film is used as a trap layer. In the former type, the threshold voltage of the cell transistor is raised by injecting electrons into the floating gate (data “0”), and the threshold voltage of the cell transistor is lowered by extracting the injected electrons (data “ 1)). A state where the threshold voltage is high and a state where the threshold voltage is low are detected based on the magnitude of the drain current of the cell transistor. In the latter type, charges (for example, electrons) are trapped in a trap layer (or trap gate) made of an insulating film to change the threshold of a cell transistor, and data “0” and “1” are stored. Since the trap layer is insulative, charges cannot move within the trap layer. Therefore, charges can be stored at both ends of the trap layer, and four states of “0 0”, “0 1”, “1 0”, and “1 1 J”, that is, 2-bit information can be stored. The latter type is described, for example, in Patent Document 1 below.

In the above non-volatile memory, a memory having a virtual ground structure in which cell transistors that contact each other share a bit line to increase the memory capacity has been proposed (for example, Patent Document 2 below). . In this virtual ground type cell array, a bit line is connected to the drain and source of each cell transistor, and cell transistors adjacent in the word line direction share the bit line. So a cell When performing a read operation by selecting a transistor, a drain current detection circuit is connected to the bit line on the drain side of the selected cell transistor, the bit line on the source side is grounded, and an adjacent cell sharing the bit line on the drain side The bit line on the source side of the transistor is set to the precharge voltage. In other words, the source and drain of the adjacent transistor are set to substantially the same potential so that no drain current is generated in the adjacent transistor, and the drain current of the selected cell transistor is all supplied to the drain current detection circuit via the bit line. So that Therefore, in the virtual ground type memory, the source side bit line of the adjacent cell transistor is controlled in addition to the drain side bit line and the source side bit line of the selected cell transistor.

[Patent Document 1]

WO99 / 07000 `` Two Bit Non-Volatile Electrically Erasable and Programmable Semiconductor Memory Cell Utilizing Asymmetrical Charge mppingJ

[Patent Document 2]

Japanese Patent Application Laid-Open Publication No. 2000-220228, for example, FIGS.

However, when the threshold voltage of the P-contact cell transistor is low, the drain current of the selected cell transistor varies depending on the threshold voltage state of the cell transistor further adjacent to the adjacent cell transistor. That is, the drain current of the selected cell transistor varies depending on the state (data pattern) of the adjacent cell transistor, and the data read margin of the selected cell transistor becomes smaller. Such read characteristics depending on the data pattern of the adjacent cell transistor are referred to as pattern sensitivity in this specification.

In a memory having such pattern sensitivity, in a read operation test, it is required to write data to an adjacent cell transistor and perform a read operation in a state of all data patterns. However, in order to bring adjacent cell transistors into the state of all data patterns, it is necessary to repeat writing and erasing operations, and the operation test process at the time of shipment becomes enormous, and the throughput of the operation test process increases. become worse.

Also, the memory cells of the non-volatile memory may have a floating gate during the erasing step. By extracting electrons in the auto-trap gate, the threshold direct voltage is reduced. However, if electrons are extracted too much in this erasing process, the cell transistor will be in an over-erased state with a negative threshold voltage. In the over-erased state, the non-selected cell transistors in which the word lines are not driven are turned on to generate a slight drain current. When the drain current due to this over-erase cell overlaps with the drain current of the selected cell transistor on the same column, the drain current detected by the read circuit increases, and the read margin decreases.

It is necessary to conduct a test to determine whether or not the memory operates normally in the over-erased state in such a memory that has the possibility of entering the over-erased state. However, in order to reproduce the over-erased cell on the same column, it is necessary to perform the test while performing the erase operation. As with the pattern sensitivity, the test process at the time of shipment becomes enormous, and The throughput of the test process is reduced. Disclosure of the invention

Therefore, an object of the present invention is to provide a non-volatile memory capable of performing an operation in a state of the data pattern without writing a data pattern corresponding to the pattern sensitivity to the adjacent cell transistor.

It is another object of the present invention to provide a nonvolatile memory capable of performing an operation test depending on an over-erased state without setting cell transistors on the same column in an over-erased state.

In order to achieve the above object, one aspect of the present invention is a nonvolatile memory, comprising: a plurality of cell transistors having first and second source and drain; and a word line connected to the plurality of cell transistors. And a plurality of bit lines commonly connected to the first and second sources and drains of cell transistors adjacent in the direction of the word line, and a first bit line connected to the first source and drain of the selected cell transistor. A drain current detection circuit for detecting the drain current of the selected cell transistor flowing through the bit line of the selected cell transistor; and setting the second bit line connected to the second source / drain of the selected cell transistor to the first potential, A third bit line connected to an adjacent cell transistor sharing the first bit line with the selected cell transistor. A bit line potential control circuit for setting the potential to 2 and a current circuit for virtually increasing or decreasing the drain current detected by the drain current detection circuit.

According to the aspect of the invention described above, in the configuration in which the drain current detection circuit is connected to the first bit line connected to the selected cell transistor and detects the drain current of the selected cell transistor, the drain current detection circuit detects the drain current. A current circuit that virtually increases or decreases the drain current to be applied is provided, so that during the operation test, the state of the drain current depending on the data pattern is virtually determined by the current circuit without writing a predetermined data pattern to the adjacent cell transistor. Can be reproduced. Therefore, a dynamic test depending on a data pattern can be performed without writing a data pattern.

Similarly, by virtually increasing the detected drain current by the current circuit, it is possible to virtually reproduce the state in which the cell transistor in the same column as the selected cell transistor is in the over-erased state. The process throughput can be improved.

In a preferred embodiment according to the above aspect of the present invention, the current circuit is connected to the drain current detection circuit, and the current circuit increases a drain current detected by the drain current detection circuit in response to a test signal. Or reduced. In still another preferred embodiment, further, a reference sensor transistor, a reference detection circuit connected to the reference cell transistor for detecting a drain current of the reference transistor, the drain current detection circuit, and a reference detection circuit And a sense circuit for comparing the output of the circuit to detect stored data. The current circuit is further connected to a reference detection circuit, and the current circuit responds to a test signal, and the reference detection circuit It is characterized in that the detected drain current is increased or decreased.

In order to achieve the above object, according to a second aspect of the present invention, in the nonvolatile memory according to the first aspect, after the cell transistor is set to a predetermined data storage state, the drain detection circuit performs detection. A non-volatile memory operation test method, wherein a read operation of a selected cell transistor is performed in a state where a drain current to be generated is virtually increased or decreased. According to the second aspect, the throughput of the test process can be improved. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a diagram illustrating the operation of a nonvolatile memory cell having a trap layer. FIG. 2 is a diagram showing a virtual ground type memory cell array structure.

FIG. 3 is a diagram showing a virtual ground type memory cell array structure.

FIG. 4 is a diagram showing a virtual ground type memory cell array structure.

FIG. 5 is a diagram showing a virtual ground type memory cell array structure.

FIG. 6 is a diagram showing a circuit for controlling the potential of the bit line of the nonvolatile memory of the virtual ground type.

FIG. 7 is a diagram showing a read circuit of a virtual ground type nonvolatile memory.

FIG. 8 is a diagram for explaining pattern sensitivity.

FIG. 9 is a diagram showing a memory circuit example (1) according to the present embodiment.

FIG. 10 is a diagram for explaining the state (Β).

FIG. 11 is a diagram showing a memory circuit example (2) in the present embodiment.

FIG. 12 is a diagram showing a memory circuit example (3) according to the present embodiment.

FIG. 13 is a diagram for explaining the state (C).

FIG. 14 is a diagram showing a memory circuit example (4) according to the present embodiment.

FIG. 15 is a diagram illustrating a test circuit according to the present embodiment.

FIG. 16 is a flowchart of the test process in the present embodiment. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the scope of protection of the present invention is not limited to the following embodiments, but extends to the inventions described in the claims and their equivalents.

Hereinafter, an embodiment of the present invention will be described using a flash memory type having a trap gate as an example. However, as described later, the present embodiment can be applied to a type having a floating gate.

FIG. 1 is a diagram for explaining the operation of a nonvolatile memory cell having a trap gate. You. A cell transistor of a memory cell having a trap gate has first and second source / drains SD1 and SD2 provided on the surface of a semiconductor substrate, and a silicon oxide film and a silicon nitride film are provided on a channel region sandwiched between them. A film, a silicon oxide film, and a conductive control gate are sequentially formed. The silicon nitride film serves as a trap gate, and can accumulate electric charges (eg, electrons) in regions at both ends thereof. One of the first and second source / drain regions SD1 and SD2 operates as a source and the other as a drain in one operation, and operates as a drain and the other as a source in another operation.

In the write operation A of FIG. 1, for example, 9 V is applied to the control gate, 5 V is applied to the first source-drain SD1, and 0 V is applied to the second source-drain SD2 and the substrate, for example, so that Hot electrons generated at the trap gate are trapped. By this channel hot electron injection, electrons (black circles in the figure) are injected into the right end of the trap gate. In the erasing operation B, for example, 16 V is applied to the control gate and 6 V is applied to the first source and drain SD1, respectively, and the second source and drain SD2 are set in a floating state, and the first source is drained. 'Inject holes generated by band-to-band tunnel current flowing from drain SD1 into the substrate into the trap gate. As a result, the electrons trapped in the trap gate are neutralized, and the electrons at the right end of the trap gate disappear.

Then, in the read operation C, a voltage in a direction opposite to that of the write operation is applied between the first and second sources and drains. This is a so-called reverse read. For example, 0 V, for example, is applied to the first source / drain SD1, and 1.5V, for example, is applied to the second source / drain SD2, and, for example, 5 V is applied to the control gate. At this time, if electrons are trapped at the right end of the trap gate, no channel is formed and the drain current Id does not flow, but if electrons are not trapped, a channel is formed and the drain current Id d flows. By detecting the presence or absence of the drain current Id via the bit line connected to the second source / drain SD2, data of the cell transistor can be read.

When electrons are stored at the left end of the trap layer, the relationship between the first and second source-drain SD1 and SD2 in FIG. 1 is reversed. As described above, a nonvolatile memory having an insulating trap layer can store 2-bit data in a cell, and is expected as a multi-bit memory cell. On the other hand, a cell structure having an insulating trap layer has an advantage that the manufacturing process is simpler than a cell structure having a conductive floating gate.

2 to 5 are diagrams respectively showing a virtual ground type memory cell array structure. 2 to 5, in the memory cell array, a plurality of cell transistors MC are arranged in a row, and a plurality of lead lines WL0 to WL2 arranged in a row direction serve as control gates of each senole transistor. Also serves as. In addition, adjacent cell transistors MC 0 to MC 4 in the row direction share bit lines BL 0 to BL 5.

Fig. 2 shows a state in which no electrons are trapped in the trap gates of all the cell transistors MC, a state in which the threshold voltage is low, and a state of data "1, 1". In this case, in the read operation, a drain current is generated in any direction between the first and second sources and drains of the cell transistor. FIG. 3 shows a state in which electrons are trapped at the left end of the trap gates of all the cell transistors MC, and a state of data “0, 1”. In this case, in the read operation, the drain current in the left direction is not generated due to the effect of the trapped electrons, but the drain current in the right direction is generated. FIG. 4 shows a state in which electrons are trapped at the right end of the trap gates of all the cell transistors MC, and a state of data “1, 0”. In this case, in the read operation, the rightward drain current is not generated due to the effect of the trapped electrons, but the leftward drain current is generated. FIG. 5 shows a state where electrons are trapped at both ends of the trap gates of all the cell transistors MC, and a state of data “0, ◦”. In this case, neither a left nor right drain current is generated in the read operation. These states can be detected by detecting the magnitude of the drain current generated on the bit lines on both sides of the transistor.

In a virtual ground type nonvolatile memory, in a read operation, a drain current of a cell transistor is detected via a bit line connected to a selected cell transistor. In addition, since the program verify operation and the erase verify operation are substantially the same as the read operation, the drain current of the cell transistor is similarly set via the bit line. Is detected. In these cases, since the bit line is shared with the adjacent cell transistor, it is necessary to prevent the drain current from being generated in the adjacent cell transistor. Therefore, it is necessary to appropriately control the potential of the bit lines on both sides of the selected cell transistor and the potential of the other bit line of the P-connected cell transistor.

FIG. 6 is a diagram showing a circuit for controlling the potential of the bit line of the nonvolatile memory of the virtual ground type. FIG. 6 shows two memory cell arrays MCAO and MCA1. Accordingly, in addition to local bit lines BLO to BL3 in each memory cell array, global bit lines GBL0 to GBL3 shared by a plurality of memory cell arrays MCAO and MCA1 are provided. Local bit lines BLO ~: BL3 is connected to global bit lines GBL0 to GBL3 via local column select transistors QO0 to QO3 and Q10 to Q13, respectively. The global bit lines GB L0 to GBL 3 are connected to the bit line potential control circuit group 10 via global column selection transistors C S0 to C S3.

The bit line potential control circuit group 10 in FIG. 6 includes a drain current detection circuit 12, a precharge voltage generation circuit 14, and a ground GND, and further includes a global bit line selected by a global column selection transistor. It has a transistor group Qa, Qb, and Qc connected to one of the drain current detection circuit 12, the precharge voltage generation circuit 14, and the ground GND. Therefore, a connection point between the drain current detection circuit 12 and the transistor Qa corresponds to a data bus common to a plurality of global bit lines.

The read operation will be described by taking as an example a case where the state on the left side of the trap gate of the cell transistor MC0 in the memory cell array MCAO is read. To read the state on the left side of the trap gate of the cell transistor MC0, drive the read line W00 to 5 ¥, set the other word lines to the ground level, and drain the local bit line BL1 in the cell array to the drain current. Connect to the detection circuit 12, connect the local bit line BLO to ground GND, and connect the local bit line BL 2 of the adjacent cell transistor MC 1 to the precharge voltage generation circuit 14. Therefore, the local bit line BL 1 is connected to the local column select transistor QO 1, the global bit line GBL 1, the global column select transistor CS 1, and the transistor Q a 1 and is connected to the drain current detection circuit 12. The local bit line BLO is connected to the ground GND via a local column select transistor Q 00, a global bit line GBL 0, a global column select transistor CS 0, and a transistor Q c 0. Further, the local bit line BL 2 is similarly connected to the precharge circuit 14.

The bit line BL1 connected to the drain current detection circuit 12 has a drain voltage Vd of, for example, about 1.5 V, and the bit line BL2 connected to the precharge voltage generation circuit 14 has the same configuration. Of the precharge voltage. Therefore, there is almost no potential difference between the source and the drain of the adjacent cell transistor MC1, and almost no drain current is generated. Therefore, the drain current of the selected cell transistor M C0 mainly flows through the bit line B L1, and the drain current is detected by the drain current detection circuit 12.

FIG. 7 is a diagram showing a read circuit of a virtual, ground-type nonvolatile memory. The verify circuit at the time of erasing or programming has the same configuration. In FIG. 7, the cell array MCA on the core side is shown on the left side, and the cell array RMCA on the reference side is shown on the right side. Then, the bit / line BL 1 in the cell array MC A on the core side is connected to the drain current detection circuit 12 via three transistors QO 1, CS l and Q a 1, and similarly, the reference ^ f The reference bit and line RBL 1 in the rule cell / array RMC A are also connected to the reference side drain current detection circuit 12 R via three transistors RQ 1, RQ 2 and RQ a.

The drain current detection circuit 12 is a circuit that converts the drain current Id flowing through the bit line BL1 into a voltage Vcore, and includes a load transistor N1 connected to the power supply voltage Vdd, and an inverter 16. A transistor N2 whose source potential is fed back to the gate, and a voltage Vcore is generated according to the supplied drain current Id. In other words, the larger the drain current Id, the lower the voltage Vcore. Similarly, the reference-side drain current detection circuit 12 R is also a circuit that converts the reference drain current I rd flowing through the reference bit line RBL 1 into a voltage Vref, and includes a load transistor Nl 1 and a transistor N 1 And 2. The reference cell transistor RMCO is, for example, programmed to a threshold voltage state intermediate between the threshold voltage states that the core side transistor MC0 can assume, and the reference side transistor having a current between the core side possible drain currents. Generates drain current Ird. Therefore, an intermediate potential of the voltage Vcore that can be taken on the core side is generated as the reference voltage Vref. Then, the magnitude relationship between the core-side voltage Vcore and the reference voltage Vref is detected by the sense amplifier SA, and the output signal UT is generated. This output OUT is output to the outside as a data output signal. FIG. 8 is a diagram for explaining pattern sensitivity. FIG. 8 shows three states (A), (B), and (C), all of which are states in which whether or not a force is trapped on the left side of the trap gate of the cell transistor MC0 is read. Therefore, in any case, the bit line BL 1 is connected to the drain current detection circuit 12 to be at the drain voltage Vd, the bit line BL 0 is connected to the ground (V s = GND), and the bit line BL 2 is It is connected to the charge voltage generation circuit 14 and is set to the precharge voltage Vp.

State (A) is a case where the threshold voltage Vth of the adjacent cell transistor MC1 is high. In this case, even if the word line WL is driven to a predetermined voltage, the adjacent cell transistor MC1 does not conduct, and the drain current Ipd does not flow. Therefore, the drain current Id flowing through the bit line BL1 is the same as the drain current Ids flowing through the selected cell transistor MC0 (Id = Ids).

State (B) is a case where the threshold voltage Vth of the adjacent cell transistor MC1 is low and a case where the threshold voltage Vth of the adjacent cell transistor MC2 is high. In this case, when the word line WL is driven, the adjacent cell transistor MC1 is turned on, and the adjacent cell transistor MC2 is not turned on. At this time, when the drain current Ids occurs in the selected cell transistor MC0, the voltage Vd of the bit line BL1 becomes lower than the precharge voltage Vp, and the adjacent cell transistor between the bit line BL1 and the bit line BL2 A slight drain current Id is generated in MC1. Although the drain current Ipd of this adjacent transistor MC1 is smaller than the drain current Ids of the selected cell transistor MC0, the drain current Id flowing through the bit line BL1 due to the generation of the drain current Ipd becomes Id = Ids− It becomes smaller with Ipd. That is, in the erased state (data “1”) in which the threshold voltage of the selected cell transistor MC 0 is low, the drain current Ids of the selected transistor MC 0 does not change, and the drain current Ipd of the adjacent cell transistor MC 1 does not change. Due to the occurrence, the drain current Id flowing through the drain current detection circuit 12 is substantially reduced, and the detection margin of the state is reduced. On the other hand, in the programmed state (data “0”) in which the threshold voltage of MC 0 of the selected cell transistor is high, only a small drain current Ids is generated in the selected transistor MC 0, but the drain current of the adjacent sensing transistor MC 1 is reduced. Since the drain current Id flowing through the drain current detection circuit 12 is further reduced by Ipd, the detection margin in that state is increased.

State (C) is a case where the threshold voltage Vth of the adjacent cell transistor MC1 is low, and a case where the threshold voltage Vth of the adjacent cell transistor MC2 is also low. In this case, when the word line WL is driven, the adjacent cell transistor MC1 is turned on, and the adjacent cell transistor MC2 is turned on. Due to the generation of the drain current IpO of the adjacent cell transistor MC2, the voltage difference between the drain voltage Vd of the bit line BL1 and the precharge voltage Vp of the bit line BL2 is Vd-Vp. (B) A smaller force \ or Vd> Vp. Therefore, the drain current Ipd of the adjacent cell transistor MC1 between the bit line BL1 and the bit line BL2 becomes a force \ smaller than the state (B) or the direction from the bit line BL1 to BL2. Alternatively, when the drain current Ids does not occur in the selected cell transistor MC0, the drain current Ipd of the adjacent cell transistor MC1 is in the direction from the bit line BL1 to BL2. Due to the generation of the small drain current Ipd or the reverse drain current Ipd, the drain current Id flowing from the drain current detection circuit 12 to the bit line BL 1 is larger than the state (B) because Id = Ids−Idd. Or greater than the drain current Ids of the selected cell transistor MC0, such as Id = Ids + Ipd.

That is, in the erased state (data “1”) in which the threshold voltage of the selected cell transistor MC 0 is low, the drain current Ids of the adjacent transistor MC 1 is not changed even if the drain current Ids of the selected transistor MC 0 is unchanged. Since the drain current Id flowing through the drain current detection circuit 12 is substantially increased by decreasing the current or flowing in the direction opposite to the arrow in the figure, the detection margin in that state is increased. Meanwhile, election In the program state (data “0”) in which the threshold voltage of the selection cell transistor MC O is high (data “0”), the drain current Id flowing through the drain current detection circuit 12 is larger than the slight drain current Ids of the selection transistor MC 0 Therefore, the detection margin of the state becomes small.

In other words, in state (B), the state of data “1” (small Vth, large drain current Ids) of the selected cell transistor becomes difficult to read, and in state (C), data “0” of the selected cell transistor. (Vth large, drain current Ids small) makes the state difficult to read. As described above, the data read margin of the selected cell transistor varies depending on the data pattern of the adjacent cell transistors MC 1 and MC 2. If there is such a data pattern dependency, it is necessary to check in the operation test whether or not the power operates normally when the detection margin is small.

The state (C) in FIG. 8 is similar to the case where the sensing transistor in the same column as the selected cell transistor is in the over-erased state (threshold voltage Vth <0). In other words, if an unselected cell transistor in the same column as the selected cell transistor becomes over-erased, a drain current will be generated even if the word line is not driven, so the drain current Id flowing through the drain current detection circuit 12 Becomes larger than the drain current Ids of the selected cell transistor MCO. This is the same state as state (C).

It is desirable to perform an operation test while reproducing a state where the detection margin is small as described above.To reproduce such a state, a detection margin must be added to the cell transistor adjacent to the selected cell transistor to be tested. It is necessary to write a data pattern to make it smaller. Such a writing process results in a significant reduction in experimental throughput. Therefore, in the present embodiment, a virtual current circuit that virtually increases or decreases the drain current detected by the drain current detection circuit is provided so that the above-described state where the detection margin is small can be virtually reproduced.

FIG. 9 is a diagram showing a memory circuit example (1) according to the present embodiment. This is a circuit that reproduces the state (B) in FIG. 8, and a downward current circuit 10 is provided in a reference-side drain current detection circuit 12R. This current circuit 10 increases the reference current Ir flowing through the reference-side drain current detection circuit 12 R (Ir = Id + I0), and as a result, the detection drain flowing through the core-side drain current detection circuit 12 The state (B) in which the in-current Ic is substantially reduced is reproduced. In the state of FIG. 9, when the read test of the selected cell transistor MC0 is performed, the threshold voltage of the adjacent cell transistor MC1 is high and the drain current Ipd is zero (Ipd = 0). Even in such a state, by adding the current circuit 10 to the reference side, the state (B) in which the detection drain current Ic flowing through the drain current detection circuit 12 on the core side is substantially reduced can be reproduced.

FIG. 10 is a diagram for explaining the state (B). In FIG. 10, the horizontal axis represents the word / 锒 voltage V WL, and the vertical axis represents the detected drain currents Ic and Ir flowing through the drain current detection circuit. When the threshold voltage of the selected cell transistor is low and the data is “1”, the detected drain current Icl is larger than the selected word line voltage VWLS. On the other hand, when the threshold voltage of the selected cell transistor is high (data 0), the detected drain current IcO is small relative to the selected word line voltage VWLS. In this case, the reference drain current Ir on the reference side is set between the detection drain currents Icl and IcO in the above two states.

In Fig. 9, by adding the current circuit 10 to the reference-side drain current detection circuit 12R, the reference-side detected drain current Ir shifts to the left as indicated by the dashed arrow, and increases to Ir = ld + I0. I do. This means that the current difference from the detected drain current Icl of data “1” becomes smaller, which is substantially the same as the case where the detected drain current Icl of data “1” is reduced. As described above, by adding the current circuit 10 of FIG. 9, the detection margin of the data “1” can be virtually reduced. FIG. 11 is a diagram showing a memory circuit example (2) according to the present embodiment. This is also a circuit that reproduces the state (B) in FIG. 8, and an upward current circuit 10 is provided in the drain current detection circuit 12 on the core side. In this case, even if the threshold direct voltage of the adjacent cell transistor MC 1 is high and the drain current Ipd does not occur there, the addition of the current circuit 10 allows the detection drain flowing through the core side drain current detection circuit 12 to be detected. The current Ic is smaller by 10 than the drain current Id of the bit line BL1. That is, as shown by the arrow of the real if spring in the state (B) of FIG. 10, the state where the detected drain currents Icl and IcO on the core side are reduced is reproduced by the current circuit of FIG. 11. That is, the detection margin of data “1” can be reduced. FIG. 12 is a diagram showing a memory circuit example (3) in the present embodiment. This is a circuit that reproduces the state (C) in FIG. 8, and a downward current circuit 10 is provided in the drain current detection circuit 12 on the core side. The current circuit 10 increases the detected drain current Ic flowing through the core-side drain current detection circuit 12 (Ic == ld + I0), and as a result, reproduces the state (C). In the state of FIG. 12 as well, the threshold voltage of the adjacent cell transistor MC1 is high and the drain current Ipd is zero (lpd = 0) when performing the read test of the selected cell transistor MC0. Even in such a state, by adding the current circuit 10 to the core-side drain current circuit 12, the state (C) in which the detected drain current Ic flowing there is added can be reproduced.

FIG. 13 is a diagram illustrating the state (C). In FIG. 13 as well as in FIG. 10, the horizontal axis shows the lead line voltage VWL, and the vertical axis shows the detected drain currents Ic and Ir flowing through the drain current detection circuit. The addition of the current circuit 10 to the core-side drain detection circuit 12 as shown in FIG. 12 means that the detected drain currents Icl and IcO are increased, and the solid line arrows in FIG. The state as shown is reproduced. That is, the current circuit 10 shown in FIG. 12 reproduces a state in which the detection margin of the data “0” becomes small. .

FIG. 14 is a diagram showing a memory circuit example (4) according to the present embodiment. This is also a circuit that reproduces the state (C) in FIG. 8, and an upward current circuit 10 is provided in the drain current detection circuit 12 R on the reference side. This current circuit 10 reduces the reference current Ir flowing through the reference side drain current detection circuit 12 R (Ir = Id−10), and as a result, the detection drain current flowing through the core side drain current detection circuit 12 R Reproduce the state (C) in which Ic is substantially increased. In the state shown in FIG. 14, the threshold voltage of the adjacent cell transistor MC1 is high and the drain current Ipd there is zero (lpd = 0) when performing the read test of the selected cell transistor MC0. Even in such a state, by adding the current circuit 10 to the reference side, the state (C) in which the current Ic flowing through the drain current detection circuit 12 on the core side substantially increases can be reproduced. In other words, a state in which the detection margin of data “0” is reduced is reproduced. Referring again to FIG. 13, the detection margin of data “0” is reduced by reducing the reference current Ir, as indicated by the dashed arrow in the figure. As described above, in the operation test process, even if the threshold voltage of the adjacent cell transistor MC1 is high, the detection margin of the data "1" in the state (B) is small by adding the current circuit of Figs. The state can be reproduced, and by adding the current circuits shown in Figs. 12 and 14, it is possible to reproduce the state where the detection margin of data "0" in state (C) is small.

FIG. 15 is a diagram illustrating a test circuit according to the present embodiment. In this example, in response to the test control signals INc and INr generated by the test circuit 21, the current circuits I0c and IOr are connected to the output terminals of the core or reference drain current detection circuits 12 and 12R. Is done. The output terminals of the drain current detection circuits 12 and 12R correspond to the data bus DATABn on the core side and the data bus DATABREF on the reference side, as is clear from the circuit of FIG.

In FIG. 15, a test command CMD is supplied to the command decoder 20 from the outside, and the reproduction state of the test mode is indicated. The output of the command decoder 20 indicates the decoded reproduction state, and the test circuit 21 controls the test in the reproduced state. To reproduce the state (B), the test circuit 21 sets the test control signal INr to the H level to control the transistor Q22 to the conductive state, and adds the current circuit IOr to detect the detection drain current Ir on the reference side. Increase. Conversely, if the state (C) is to be reproduced, the test circuit 21 sets the test control signal INc to the H level to control the transistor Q20 to be in the conductive state, and the current circuit IOc is added to the control circuit 21 to adjust the current. Increase the side drain current Ic.

In FIG. 15, if the current direction of the current circuits I0c and IOr is upward, the test control signal INc becomes H level when the state (B) is reproduced, and the core-side detected drain current Ic is reduced. At the time of reproduction of (C), the test control signal INr becomes H level, and the detected drain current Ir on the reference side decreases.

FIG. 16 is a flowchart of the test process in the present embodiment. In the case of a nonvolatile memory having a trap gate, two bits of information can be stored in one memory cell. The threshold voltage is high in the programmed state (data “0 J”) in which electrons are trapped, and low in the erase state (data “1”) in which electrons are not trapped. When the 2-bit information is “0, 0”, the drain current is the highest. The drain current is the largest when “1, 1” is small, and when “1, 0” or “0, 1”, the drain current is “0, 0” or “1, 1”. And the detection margin of the read operation becomes smaller. Therefore, in the case of such data “1, 0” and “0, 1”, an operation test particularly depending on the above data pattern is required. In the test process of the present embodiment, first, all cells are in an erased state (data “1, 1J”), and a read operation test is performed in that state (S10). A program is performed so as to obtain "1, 0" (S12), and a read operation test is performed by adding current 10 to the core-side detected drain current while reproducing, for example, the state (C) (S14). A read operation test is performed by adding the current 10 to the reference-side detected drain current while reproducing, for example, the state (B) (S16).

Next, all cells are programmed so that the data becomes “0, 1” (S18), and a read operation test is performed by adding current 10 to the detected drain current on the core side and reproducing, for example, state (C). (S20), and further, a current 10 is added to the detected drain current on the reference side, and a read operation test is performed while reproducing, for example, the state (B) (S22). Finally, all the cells are programmed so as to become data "0, 0" (S24), and a read operation test is performed (S28).

According to the above operation test procedure, while the same data is programmed in all cells, it is determined whether or not the read operation can be performed normally even in a state where the detection margin is small depending on the data pattern of the adjacent cell transistor. You can check. The above-mentioned states (B) and (C), in which the detection margin is reduced depending on the data pattern, can be reproduced by controlling whether or not the current circuit is connected by the test circuit. Since there is no need to write the data, the throughput of the operation test process can be improved.

Further, the state (C) is the same as the state where an overerased cell transistor exists in the same column as the selected cell transistor. This is because the presence of an over-erased cell transistor causes a leak current even in a non-selected state, and increases the drain current flowing through the bit line. Therefore, in the operation test process, by performing the read operation test with the current 10 added to the core side, the over-erased cells exist substantially or virtually without setting the unselected cell transistors to the over-erased state. You The operation test can be performed in a state where

Further, in the above embodiment, the non-volatile memory having a trap gate has been described as an example. However, in a non-volatile memory having a conductive floating gate, a similar current circuit is provided to reduce the detection drain current. By increasing or decreasing, the test can be performed by reproducing the state where the inspection margin is small.

The above-described read operation can be similarly applied to a program verify operation and an erase verify operation, which are the same operations as the read operation. Industrial potential

As described above, according to the present invention, it is possible to reproduce a state in which the detection margin is reduced without writing predetermined data to the adjacent cell transistor, so that the throughput of the dynamic fm test can be improved.

Claims

The scope of the claims

1. A plurality of cell transistors having first and second source 'drains, a plurality of lead lines connected to the cell transistors, and first and second sources of cell transistors adjacent in the lead line direction. A plurality of bit lines commonly connected to the drain, and a first source of the selected cell transistor.A drain current for detecting the drain current of the selected cell transistor flowing through the first bit line connected to the drain A detection circuit and a second bit line connected to a ^second source / drain of the selected cell transistor are set to a first potential, and the selected bit line is shared with the selected cell transistor. A bit line potential control circuit for setting the third bit line connected to the adjacent cell transistor to the second potential to a second potential, before the drain current detection circuit detects the potential. A current circuit for virtually increasing or decreasing the drain current.

2. In Claim 1,

A nonvolatile memory, wherein the current circuit is connected to the drain current detection circuit, and the current circuit increases or decreases a drain current detected by the drain current detection circuit in response to an operation test signal. .

3. The reference detecting circuit according to claim 1, wherein the reference detecting circuit is connected to a star and detects a drain current of the reference cell transistor; and a sense detects stored data by comparing outputs of the drain current detecting circuit and the reference detecting circuit. And a circuit,

Further, the current circuit is connected to a reference detection circuit, and the current circuit increases or decreases a drain current detected by the reference detection circuit in response to an operation test signal. memory.

4. In claim 1,

The current circuit responds to an operation test signal to the drain current detection circuit. A non-volatile memory, which is connected to increase or decrease the detected drain current.

5. In claim 1,

A non-volatile memory, characterized in that the cell transistor has a trap gate of an insulating film, and stores a state of trapping or not trapping electric charges at least at both ends of the trap gate.

6. In Claim 1,

The nonvolatile memory according to claim 1, wherein the cell transistor has a conductive floating gate, and stores a state of whether or not charge is injected into the floating gate.

7. A plurality of cell transistors having first and second sources and drains, a plurality of lead lines connected to the cell transistors,

First and second sources of the cell transistors adjacent in the word line direction; a plurality of bit lines commonly connected to the drain;

A drain current detection circuit for detecting a drain current of the selected cell transistor flowing through a first bit line connected to the first source / drain of the selected cell transistor;

Neighboring cell transistors sharing the second source ■ a ^second bit line connected to the drain and to the first potential, the said selected cell transistor a first bit line of the selected cell transistor A bit line potential control circuit for setting a third bit line connected to the second potential to a second potential;

A current test circuit for virtually increasing or decreasing the drain current detected by the drain current detection circuit.

After setting the cell transistor in a predetermined data storage state, a read operation test of the selected cell transistor is performed in a state where the drain current detected by the drain detection circuit is virtually increased or decreased by the current circuit. Have a process A non-volatile memory operation test method,

8. In Claim 7,

In the operation test step, the current circuit is connected to the drain current circuit in response to an operation test signal.

9. In Claim 7,

The nonvolatile memory further includes: a reference cell transistor; a reference detection circuit connected to the reference cell transistor for detecting a drain current of the reference cell transistor; a drain current detection circuit and a reference A sense circuit that compares the output of the detection circuit to detect the stored data.

An operation test method for a nonvolatile memory, wherein in the operation test step, the current circuit is connected to the reference detection circuit in response to an operation test signal.

10. In claim 7,

An operation test method for a nonvolatile memory, wherein the operation test step is performed after the same data is programmed in the plurality of cell transistors.