WO2004102976A1

WO2004102976A1 - Image processing device

Info

Publication number: WO2004102976A1
Application number: PCT/JP2004/003667
Authority: WO
Inventors: Yukio Koyanagi
Original assignee: Neuro Solution Corp.
Priority date: 2003-05-13
Filing date: 2004-03-18
Publication date: 2004-11-25
Also published as: JP2004349737A; TW200501756A

Abstract

An image processing device has an interpolating section (2) for creating pixel data on each interpolated pixel by interpolation using a sampling function with finite supports and a YC separating circuit (3) for separating the luminance signal and the color signal from the interpolated composite video signal by carrying out a predetermined calculation of data on adjacent pixels of the interpolated pixel on an adjacent line. Therefore, for even the interpolated-pixel composite signal, the phase of the color signal of one line is opposite to that of the adjacent line. As a result, after the image is converted to a high definition one, YC separation is carried out. The R, G, and B signals are not subjected to interpolation, but only one composite signal is subjected to interpolation. Memories for interpolating pixels can be reduced.

Description

Image processing device

Technical field

The present invention relates to an image processing apparatus, and in particular, to increase the resolution by increasing the number of pixels constituting a color image by interpolation processing, and to increase the definition of the image.

It is suitable for use in an apparatus having a function of

Itoda 1

book

Background art

Generally, a color video signal is composed of a color signal (C signal) and a luminance signal (Y signal).

) Are frequency-multiplexed and are called composite video signals. In the case of the NTSSC signal, as shown in FIG. 1, the chrominance signal is orthogonally modulated with a 3.58 MHz reference signal called a color subcarrier (color subcarrier) and multiplexed with a luminance signal. The phase of the color subcarrier is opposite between both lines and between frames as shown in FIG. When multiplexing a luminance signal with a chrominance signal, a burst signal serving as a phase reference during color demodulation is also multiplexed.

Video signal processing on the receiver side is performed separately for the chrominance signal and the luminance signal, converted to RGB signals, and output to the display device. That is, on the receiver side, the color signal band is extracted from the frequency band characteristics of the composite video signal, and color demodulation is performed on the axes of two color difference signals (R-Y signal and B-Y signal). Then, a G-Y signal is generated by matrix synthesis from the demodulated R-Y and B-Y signals. Further, a luminance signal is added to these three color difference signals to generate an R signal, a G signal, and a B signal. In order to perform the above-mentioned video signal processing on the receiver side, Jitter · It is necessary to separate the chrominance signal component and the luminance signal component from the video signal. This separation is commonly called YC separation. The methods of YC separation are roughly classified into three types: one-dimensional YC separation, two-dimensional YC separation, and three-dimensional YC separation. FIG. 3 is a diagram showing the configuration of these three types of YC separation circuits.

In the one-dimensional YC separation, as shown in Fig. 3 (a), focusing on the fact that the color signal is near 3.58 MHz, extracting the color signal with a bandpass filter that passes the color signal band, This is a method of using other signals as luminance signals.

The two-dimensional YC separation utilizes the fact that the phase of a single subcarrier is inverted every line due to frequency interleaving. That is, as shown in FIG. 3 (b), a signal of one line is subtracted from a signal of a certain line to extract a color signal, and further, a color signal is extracted by a band pass filter of 3.58 MHz.

The three-dimensional YC separation further utilizes the fact that the phase of the color subcarrier is inverted for each frame. That is, as shown in Fig. 3 (c), the three-dimensional YC separation circuit combines the time-direction filter that subtracts the signal between two frames to extract the color signal and the one-dimensional and two-dimensional filters described above. Be composed.

By the way, in recent years, there has been a strong demand for higher definition television images, and as a method for improving image quality, a method has been provided in which the number of scanning lines and the number of horizontal pixels are increased. I have.

For example, the current NTSC video signal uses a 2: 1 interlaced scan, so the vertical resolution is about 300 lines. However, the number of scanning lines of a CRT used in a general television receiver is 525, and the resolution is reduced by the interless scanning. Therefore, by increasing the number of pixels in the vertical direction by field interpolation using a field buffer to make the scanning non-interlaced, the vertical resolution is improved. Techniques for increasing the degree are known.

Some CRTs used in high-definition television receivers have the number of vertical pixels set to about twice as large as the CRT of a normal television receiver. In a television receiver of this type, a method is known in which the number of pixels in the scanning line direction is doubled by interpolation to increase the resolution in the horizontal direction.

However, if the number of pixels is interpolated to improve the quality of the television image as described above, the positional correlation of the color subcarriers between the lines will be out of order, and the phase will be inverted every line. The YC separation method (two-dimensional YC separation and three-dimensional YC separation) that takes advantage of this fact cannot be used. Therefore, conventionally, the YC separation processing had to be performed before the interpolation processing for high definition was performed.

However, when performing high-definition images after performing YC separation, it is necessary to perform interpolation processing on each of the R, G, and B signals generated after YC separation. Normally, a large-capacity memory is required to interpolate the number of pixels, but since this memory must be prepared for each of the R, G, and B signals, the circuit scale is extremely large. There was a problem of growing. Disclosure of the invention

The present invention has been made to solve such a problem, and an object of the present invention is to make it possible to achieve high definition of an image with a relatively simple circuit configuration.

In order to solve the above problem, an image processing apparatus of the present invention performs an interpolation operation using a finite number of sample functions using each pixel data of a target pixel and a plurality of peripheral pixels around the target pixel. By doing so, the pixel of interest and this Interpolation processing means for obtaining an interpolated composite video signal comprising pixel data of interpolation pixels on a straight line connecting to each of the four peripheral pixels arranged at the closest position in the diagonal direction of the pixel; and the interpolation processing means By performing the first operation on the pixel data adjacent between the lines using the pixel data of each interpolated pixel obtained by the above, the luminance signal and the chrominance signal are obtained from the interpolated composite video signal. YC separating means for separating the above. In another aspect of the present invention, the YC separation unit performs a second operation on pixel data adjacent in the line direction using the pixel data after the first operation has been performed, Means for adjusting the phase of the color signal separated from the interpolated composite video signal.

As described above, according to the present invention, the pixel value of the interpolation pixel on a straight line connecting the target pixel and each of the four peripheral pixels arranged at the closest position in the oblique direction to the target pixel is calculated as follows. Using the pixel values of the pixels, the values are obtained according to an interpolation operation using a finite number of sampling functions, and then the luminance signal and the chrominance signal are separated. It is only necessary to perform interpolation processing on one composite video signal instead of on the video signal, and it is possible to reduce the memory to be prepared for interpolation of the number of pixels. As a result, the circuit scale of the image processing apparatus can be reduced, and higher definition of an image can be achieved with a simpler circuit configuration than in the past. , Brief description of drawings

FIG. 1 is a diagram showing a waveform of a composite video signal.

FIG. 2 is a diagram showing the phase of a color subcarrier in a composite video signal.

Figure 3 is a diagram showing the configuration of three types of YC separation circuits according to the conventional method. • FIG. 4 is a block diagram illustrating a configuration example of a main part of the image processing apparatus according to the present embodiment.

FIG. 5 is a diagram showing the relationship between the arrangement of each pixel included in the three scanning lines forming the original image and the four interpolated pixels obtained by the interpolation processing in the present embodiment.

FIG. 6 is a diagram showing a sampling function used for the interpolation processing of the present embodiment. FIG. 7 is a diagram illustrating a configuration example of the interpolation processing unit according to the present embodiment that performs the interpolation calculation illustrated in FIG.

FIG. 8 is a diagram showing the relationship between each pixel constituting the composite video signal input to the interpolation processing unit and the phase of the color signal.

FIG. 9 is a diagram showing the relationship between each pixel constituting the high-definition composite video signal output from the interpolation processing unit and the phase of the color signal.

FIG. 10 is a diagram showing the phase of a color signal extracted from a high-definition composite video signal.

FIG. 11 is a diagram showing the adjusted phase of the color signal extracted from the high-definition composite video signal.

FIG. 12 is a diagram showing the relationship between the arrangement of each pixel included in the three scanning lines constituting the original image and the four interpolation pixels obtained by another interpolation processing in the present embodiment.

FIG. 13 is a diagram illustrating a configuration example of a pixel value extraction unit included in the interpolation processing unit according to the present embodiment that performs the interpolation calculation illustrated in FIG.

FIG. 14 is a diagram illustrating a configuration example of a pixel value calculation unit included in the interpolation processing unit according to the present embodiment that performs the interpolation calculation illustrated in FIG. BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a block diagram illustrating a configuration example of a main part of the image processing apparatus according to the present embodiment. As shown in FIG. 4, the image processing apparatus according to the present embodiment includes an AZD converter 1, an interpolation processing unit 2, and a YC separation circuit 3.

The A / D converter 1 converts analog composite video signals (excluding sync and burst signals) to digital data. The input composite video signal is generated, for example, by detecting an image signal by image intermediate frequency processing. The digital composite video signal output from the A / D converter 1 is input to the interpolation processing unit 2.

The interpolation processing unit 2 calculates the pixel value (pixel data) of the interpolated pixel on a straight line connecting the two adjacent pixels arranged diagonally closest to each other with respect to the pixel of interest and the two adjacent pixels. Interpolation calculation is performed to find the average of each pixel value in the pixel. At this time, the interpolation position of each interpolated pixel is set to the position of 1 Z 4 of the distance from the pixel of interest to each neighboring pixel, and four interpolation pixels are generated around the pixel of interest, and instead of the pixel of interest and the neighboring pixels, Outputs the pixel data of the interpolation pixel.

The YC separation circuit 3 uses the pixel data of each interpolated pixel output from the interpolation processing unit 2 to obtain a luminance signal (Y signal) and a chrominance signal (C signal) in a frequency-in-leave relationship. The luminance signal and the chrominance signal are separated from the interpolated composite video signal. Specifically, the signal of a certain line generated by interpolation is added to the signal of the previous line, and the resulting signal is subtracted from the signal of the certain line to obtain a color signal. · Extract luminance signal by subtracting from video signal.

The details of the interpolation processing unit 2 will be described below. For example, in the NTSC system, when the sampling frequency is 14.318 MHz, the horizontal Since approximately 63 S, which is one line period, is divisible by 9 10 clocks, the pixels are arranged in a line along the vertical direction.

FIG. 5 is a diagram showing the relationship between the arrangement of each pixel included in the three scanning lines forming the original image and the four interpolated pixels obtained by the interpolation processing in the present embodiment. The horizontal direction shown in FIG. 5 is the line direction along each scanning line corresponding to the input signal. In addition, the points indicated by “letters” indicate pixels of the original image that are regularly arranged in the vertical and horizontal directions along each scanning line, and the points indicated by “〇” indicate the vicinity of the pixel of interest. Indicates interpolation pixels obtained by the interpolation processing.

The pixel values a 0, a 1, a 2, and a 3 of the four interpolation pixels Q 0, Q 1, Q 2, and Q 3 arranged on the diagonal line around the pixel of interest P are arranged on the diagonal line. The calculation is based on the pixel values of the three pixels arranged side by side (the pixel of interest and its two neighboring pixels). For example, when obtaining the pixel value a 0 of the interpolation pixel Q 0, each pixel of the pixel of interest P arranged on the diagonal line including the interpolation pixel Q 0 and the neighboring pixels P 0 and P 3 located closest to the pixel of interest P Use the values a, b, and e.

Specifically, the position of the interpolated pixel Q 0 is set at the position of 14 on the line connecting the target pixel P and the diagonal pixel P 0, and the pixel value a 0 of the interpolated pixel Q 0 is obtained by the following operation .

a 0 = (8 a + b-e) / 8

Similarly, the pixel values a l, a 2, and a 3 of the other three interpolation pixels Q l, Q 2, and Q 3 are calculated as follows.

a l = (8 a + c-d) / 8

a 2 = (8 a + d-c) / 8

a 3 = (8 a + e-b) / 8

Here, the coefficients {8, 1, 1 1 included in the interpolation calculations of the above equations (1) to (4) } The meaning of the numeric sequence that forms {} will be explained. This sequence constitutes half of the digital basic function consisting of the sequence {-1, 1, 8, 8, 1, -1}. When a convolution operation is performed while oversampling the numerical sequence of the digital basic function, a function as shown in FIG. 6 is obtained.

The function shown in Fig. 6 is a sampling function, which is differentiable only once in the entire region, and converges to 0 at finite sample positions t1 and t2. In this way, a case where the value of a function has a finite value other than 0 in a local region and becomes 0 in other regions is called a finite base. Instead of the conventional sampling function that converges at the sampling position ± ∞, the interpolation operation is performed using a finite number of sampling functions as shown in Fig. 6, so that only a finite number of discrete data is used and the censoring error It is possible to obtain an accurate interpolated value without causing any distortion, and to minimize distortion of the output waveform.

As described here, the numerical sequence forming the coefficients {8, 1, -1} included in the interpolation arithmetic expressions (1) to (4) for the interpolation pixels Q0 to Q3 is the above-mentioned finite sample It is the basis of the transformation function. Therefore, it can be said that the interpolation calculations shown in the above equations (1) to (4) interpolate the number of pixels without distortion using a finite number of sampling functions.

FIG. 7 is a diagram showing an example of a hardware configuration for executing the interpolation calculations of the above equations (1) to (4). The interpolation processing unit 2 shown in Fig. 7 has six D-type flip-flops 10 to 15, four adders 20 to 23, four subtractors 30 to 33, and two lines. It is configured to include memories 50 and 52 and an eightfold multiplier 40.

As described above, in the NTSC system, one horizontal line corresponds to 910 clocks, and one horizontal line is composed of 910 pixels. 14.3 18 Each pixel data input to the interpolation processing unit 2 in synchronization with the clock signal CK1 corresponding to the sampling frequency of 18 MHz — In the evening, three D-type flip-flops 10 to 12, two line memories 50 and 52, and two D-type flip-flops 13 and 14 are sequentially input and held.

Each of the two line memories 50 and 52 has a capacity smaller by one pixel than the number of pixel data corresponding to one horizontal line. For example, assuming that one byte of pixel data is input corresponding to each pixel, a shift register having a capacity of 910 bytes = 909 bytes is provided. Each of the D-type flip-flops 10 to 14 holds input pixel data of one pixel.

Consider the case where the pixel data along the three horizontal lines shown in FIG. 5 are sequentially input, and the pixel data (pixel value e) corresponding to the pixel P 3 is output from the D-type flip-flop 10. The pixel data (pixel value d) of pixel P 2 input with a delay of two pixels is shifted from the D-type flip-flop 12 by the pixel data of pixel P (pixel value d) input with a delay of (910 + 1) pixels. a) is the pixel data (pixel value c) of the pixel P 1 input with a delay of (910 x 2) pixels from the line memory 50, and (910 x 2 + 2) pixels from the line memory 52. The pixel data (pixel value b) of the pixel P0 input with a partial delay is output from the D-type flip-flop 14 respectively.

Therefore, by combining the adder 20, the subtractor 30 and the multiplier 40, the output value of the line memory 50 is multiplied by 8 (8 a) and the output value of the D-type flip-flop 14 ( b) is subtracted from the output value (e) of the D-type flip-flop 10 to obtain the pixel value a 0 of the interpolated pixel Q 0 shown in the above equation (1).

Similarly, a value obtained by multiplying the output value of the line memory 50 by 8 (8a) and the output value of the line memory 52 (c ) And the output value of D-type flip-flop 12 By subtracting d), the pixel value a1 of the interpolated pixel Q1 shown in the above equation (2) is obtained.

Also, by combining the adder 22, the subtracter 32 and the multiplier 40, the output value of the line memory 50 is multiplied by 8 (8 a) and the output value of the D-type flip-flop 12 (d) By subtracting the output value (c) of the line memory 52 from the result of adding the above, the pixel value a2 of the interpolated pixel Q2 shown in the above equation (3) is obtained.

Further, a combination of the adder 23, the subtractor 33, and the multiplier 40, the output value of the line memory 50 multiplied by 8 (8a) and the output value of the D-type flip-flop 10 (e ) Is subtracted from the output value (b) of the D-type flip-flop 14 to obtain the pixel value a3 of the interpolated pixel Q3 shown in the above equation (4).

In this way, the interpolation values a 0, a 1, a 2, and a 3 corresponding to the four interpolation pixels Q 0 to Q 3 are output from the four subtractors 30 to 33, respectively. After these values are temporarily held in the D-type flip-flop 15, they are output as four interpolation results by the interpolation processing unit 2. The contents of the interpolation processing unit 2 are disclosed in Japanese Patent Application Laid-Open No. 2000-148610 filed by the present inventors.

Next, the operation of the YC separation circuit 3 will be described in detail. FIG. 8 is a diagram showing the relationship between each pixel constituting the composite video signal input to the interpolation processing unit 2 and the phase of the color signal. Incidentally, FIG. 8 shows the relationship between the case sampling frequency f _s of the image in the NTSC system is 4 times the frequency f _sc of Karasabukiya Ria (f _s = 4 f _sc).

As shown in FIG. 8, the color signal returns to its original state in four pixels (four clocks), and the phase shifts by 90 degrees for each pixel. As described above, one horizontal line is composed of 910 pixels. Therefore, the order of the color signal The phases are reversed between the lines as shown in Figure 8. The two-dimensional YC separation described above uses the fact that the phase of the color signal is inverted for each line in this way, and subtracts the signal one line before from the signal on a certain line to obtain the color signal. Has been taken out.

FIG. 9 is a diagram showing the relationship between each pixel constituting the high-definition composite video signal output from the interpolation processing unit 2 and the phase of the color signal. As described above, in the interpolation processing unit 2, with respect to the target pixel P shown in FIG. 8, the pixel values a0 to a3 of the four interpolation pixels Q0 to Q3 shown in FIG. It is calculated by 4). At this time, for example, when the phases of the color signals at the three pixels P, P 0, and P 3 used to obtain the pixel value a 0 of one interpolated pixel Q 0 are vector-combined according to the coefficient of equation (1), The phase of the color signal at the pixel Q 0 is as shown by the arrow in FIG. Similarly, the phases of the color signals at the other three interpolation pixels Q1 to Q3 are as shown by arrows in FIG.

When the calculations of the above equations (1) to (4) are executed by sequentially focusing on all the pixels, the phase of the color signal at each of the interpolation pixels, which has been quadrupled, becomes as shown in FIG. Become. As can be seen from FIG. 9, when the image is quadrupled in accordance with the interpolation method according to the present embodiment, the phase of the resulting high-definition composite video signal is well-aligned, and the phase of the color signal constituting the video signal before interpolation becomes clear. Similarly to the above, the phase of the color signal is reversed between the lines. Therefore, even after the image has been refined by the interpolation processing, the color signal can be extracted by calculating the signal of a certain line and the signal of the previous line.

For example, the extraction of the color signal at the interpolation pixel Q 0 generated from the pixel of interest P is performed by the pixel value a 0 of the interpolation pixel Q 0 and the pixel value a 2 ′ of the interpolation pixel Q 2 ′ one line before. And using

a 0 "= a 0-(a 0 + a 2 ') / 2.0. 6 6 6 · · · (5) where a 0" is the color signal at the interpolation pixel Q 0 This is a pixel value having only components. Also, the division by 2.06 16 takes into account that the vector direction of the color signal is deviated from vertical or horizontal ({(8 ² + (1 + 1) ² ) ^1/2 } / 4 = 2.06 6 16) As shown in this equation (5), the pixel value a 0 of a certain line is added to the pixel value a 2 'of the previous line, and 2. A luminance signal is obtained by dividing by 0 6 16. By subtracting this luminance signal component from the pixel value a 0 of the pixel Q 0 of interest, the color signal of the pixel of interest Q 0 can be separated. Similarly, color signals are separated from the other interpolation pixels Q 1 to Q 3 by the following equations (6) to (8).

a 1 "= a 1-(a 1 + a 3 ') / 2.0 6 1 6

a 2 "= a 2-(a 2 + a 0 ') / 2.0 6 1 6

a 3 "= a 3-(a 3 + a 1 ') / 2.0 6 1 6

FIG. 10 shows the phase of the color signal extracted from the high-definition composite video signal as described above. As shown in Fig. 10, the phase of the extracted color signal is shifted from the vertical or horizontal direction, and the correlation with the phase of the burst signal cannot be correctly obtained. Therefore, it is necessary to adjust the phase of the color signal to the phase of the burst signal. This adjustment can be performed in the subsequent stage (not shown) of the YC separation circuit 3, but can also be performed in the YC separation circuit 3.

FIG. 11 is a diagram showing the adjusted phase of the color signal when the phase of the color signal is adjusted by the YC separation circuit 3. For example, the phase adjustment of the color signal at the interpolation pixel Q 0 generated from the pixel of interest P is performed by comparing the pixel value a 0 of the interpolation pixel Q 0 with the pixel value a 1 of the interpolation pixel Q 1 adjacent to the next pixel. Using a 0 "'= (a 0" + a 1 ") / 2 (9)

The calculation is performed by: Similarly, the phase adjustment of the color signal at the interpolated pixel Q 3 located on the diagonal of the interpolated pixel Q 0 is performed by the pixel value a 3 "of the interpolated pixel Q 3 and the pixel value a 2 "and

a 3 '"= (a 2" + a 3 ") / 2… (1 0)

The calculation is performed by: As described above, it is preferable to form the pixel values after the phase adjustment diagonally, since the color signal components are arranged evenly.

Although an example in which color signals are generated at two interpolation pixels Q 0 and Q 3 has been described here, color signals at two interpolation pixels Q 1 and Q 2 on different diagonals are generated. May be. Alternatively, all the color signals at the four interpolation pixels Q 0, Q 1, Q 2, and Q 3 may be generated.

As described above in detail, in the present embodiment, the image is made high-definition by the interpolation calculation of the above equations (1) to (4). Therefore, the high-definition composite video signal after interpolation is also obtained before interpolation. Similarly to the above, the phase of the color signal can be made to be opposite between the lines. Therefore, as shown in FIG. 4, the interpolation processing unit 2 is arranged in the preceding stage of the YC separation circuit 3, and the YC separation can be performed after the image is made high definition.

This eliminates the need to perform interpolation processing on each of the R, G, and B signals as in the conventional case where high-definition processing is performed on the image after YC separation. It is only necessary to perform the interpolation processing for this. Therefore, the number of memories to be prepared for the interpolation of the number of pixels can be reduced, and the circuit scale can be reduced.

In the above embodiment, the color signal is extracted by calculating the signals of the adjacent lines constituting the high-definition composite video signal, and the luminance signal is obtained by subtracting the color signal from the high-definition composite video signal. We have explained the example of how to obtain it, but on the contrary, On the other hand, the luminance signal is extracted by performing the operation of the second term on the right side of equations (5) to (8), and the color signal is obtained by subtracting the luminance signal from the high-definition composite video signal. Is also good.

Also, in the above embodiment, as an example of the interpolation processing unit 2, the interpolation operation disclosed in Japanese Patent Application Laid-Open No. 2000-148061 shown in FIGS. 5 and 7 has been described. The present invention is not limited to this. For example, this is also good after applying the interpolation operation disclosed in Japanese Patent Laid-Open No. 2000-38021 filed by the present inventor.

FIGS. 12 to 14 are diagrams for explaining the interpolation process disclosed in Japanese Patent Application Laid-Open No. 2000-38021. Among them, FIG. 12 is a diagram showing the relationship between the arrangement of each pixel constituting the original image and the interpolated pixels obtained by the interpolation processing. Again, the horizontal direction shown in Fig. 12 is the line direction along each scanning line corresponding to the input signal, and the points indicated by "parables" are the vertical and horizontal directions along each scanning line. The pixels of the original image that are regularly arranged are shown in Fig. 7, and points indicated by "〇" indicate the interpolated pixels obtained by the interpolation process around the target pixel.

In the example shown in Figure 12, three pixels along each of three adjacent scan lines, i.e., three pixels in each of the horizontal and vertical directions, for a total of nine pixels P1 to P9 Based on the values a to i, four new interpolated pixels Q1 to Q4 are generated around a center pixel P5 at the center of these nine pixels P1 to P9, and these interpolated pixels Q1 to Q4 are generated. The pixel values A1 to A4 of 4 are calculated by the following equations (11) to (14).

A 1-{8 e + (a + b + d)-(f + h + i)} / 8---(11) A 2 = {8 e + (b + c + f)-. (D + g + h)} / 8 · ■ · (12) A 3 = {8 e + (d + g + h)-(b + c + f)} / 8---(13) A 4 = {8 e + (f + h + i)-(a + b + d)} / 8---(14) Here, a new pixel generated on a straight line connecting the central pixel P 5 and the lower right pixel P 1 at a quarter of the distance from the central pixel P 5 to the pixel P 1 is Q 1 The new pixel generated on the straight line connecting the central pixel P5 and the lower left pixel P3 at the position 14 of the distance from the central pixel P5 to the pixel P3 is Q2, and the central pixel P A new pixel generated on the straight line connecting 5 and the pixel P 7 on the upper right and at a position of 1 Z 4 from the center pixel P 5 to the pixel P 7 is Q 3, the center pixel P 5 and its A new pixel generated on the line connecting the upper left pixel P 9 and the position 1 Z 4 at the distance from the center pixel P 5 to the pixel P 9 is defined as Q 4.

FIG. 13 is a diagram showing a detailed configuration of the pixel value extraction unit 100 that extracts the pixel values a to i of the nine pixels P 1 to P 9 described above. As shown in FIG. 13, the pixel value extraction unit 100 is configured to include six D-type flip-flops 110 to 115 and two line memories 12 0 and 12 1. ing.

The pixel value extraction unit 100 stores a pixel value of each pixel included in the scanning line corresponding to the input signal as data of a predetermined number of bits (pixel data) as a clock corresponding to a predetermined sampling frequency. Input in synchronization with signal CK1. Each input pixel data is composed of two cascade-connected D-type flip-flops 110, 111, a cascade-connected line memory 120, and two D-type flip-flops 1 1, 2, 1 1 and 3 respectively.

The pixel data of each pixel output from the line memory 120 is input to the cascade-connected line memory 121 and D-type flip-flops 114, 115. Each of the line memories 12 0 and 12 1 is a first-in first-out memory that stores the pixel values of each pixel corresponding to one scanning line of the input signal in the input order, and stores the pixel data of each input pixel. Output at the timing delayed by one scan line.

Therefore, in FIG. 12, the pixel P arranged at the upper left of the central pixel P 5 Considering the point in time when the pixel data (pixel value i) corresponding to 9 is input to the pixel value extraction unit 100, the pixel data (pixel value h) of the pixel P8 input one pixel ahead is D The pixel data (pixel value g) of the pixel P7 output from the type flip-flop 110 and input two pixels ahead is output from the D-type flip-flop 111.

Further, the pixel data (pixel value f) of the pixel P 6 input one scan line ahead is output from the line memory 120, and the pixel of the central pixel P 5 input one scan line and one pixel ahead The data (pixel value e) is output from the D-type flip-flop 112, and the pixel data of the pixel P4 (pixel value d) input one scanning line and two pixels ahead is converted to the D-type flip-flop 111. Output from 3.

Further, the pixel data (pixel value c) of the pixel P3 input two scanning lines ahead is output from the line memory 121, and the pixel P2 pixel input two pixels ahead and one pixel ahead is input. The data (pixel value b) is output from the D-type flip-flop 114, and the pixel data (pixel value a) of the pixel P1 (pixel value a) input two scan lines and two pixels ahead is converted to the D-type flip-flop 11 Output from 5.

In this way, the pixel value extraction unit 100 outputs the pixel data & to i corresponding to the nine pixels P1 to P9 shown in FIG. 12 in parallel. FIG. 14 shows a detailed configuration of a pixel value calculation unit 200 that calculates pixel values A 1 to A 4 in four interpolation pixels Q 1 to Q 4 from nine pixel values a to i. FIG. As shown in Fig. 14, the pixel value calculation unit 200 is composed of 12 adders 13 0-: 14 1, 4 subtracters 15 0-15 3, and 8 times It is configured to include a multiplier 160 for performing multiplication and four dividers 170 to 173 for performing a division process of dividing an input value by 8.

The arithmetic processing of the pixel value A 1 is performed by adding an adder 13 0, 13 2, 13 4, 13 7, 13 8, a subtractor 15 0, a multiplier 16 0, and a divider 17 0. It is performed using. Specifically, three pixel values a are obtained by two adders 1 30 and 1 3 4. , B, and d are added, and three pixel values f, h, and i are added by the other two adders 13 2 and 13 7.

By inputting these two addition results to the subtractor 150, the output value (a + b + d), which is the addition result output from the adder 134, is added to the adder 133 The result of subtracting the output value (f + h + i), which is the addition result output from, is output.

Further, by adding the multiplication result (8 e) of the multiplier 160 to this output value by the adder 1 38, the addition result {8 e + (a + b + d)-(f + h + i)} is output. Further, the pixel value A 1 shown in the equation (11) is calculated by performing the division process with the divisor 8 by the divider 170 connected in the subsequent stage, and the calculation result is output from the divider 170 Is output.

The arithmetic processing of the pixel value A 2 is performed by adding an adder 13 1, 13 3, 13 5, 13 6, 13 9, a subtractor 15 1, a multiplier 16 0, and a divider 17 1 It is performed using and. Specifically, three pixel values b, c, and f are added by two adders 13 1 and 13 5, and three pixel values are added by the other two adders 13 3 and 1 36. Pixel values d, g, and h are added.

By inputting these two addition results to the subtractor 15 1, the output value (b + c + f) which is the addition result output from the adder 135 is added to the adder 1 36 The result of subtracting the output value (d + g + h), which is the addition result output from, is output.

Further, by adding the multiplication result (8 e) of the multiplier 16 0 to the output value by the adder 1 39, the addition result {8 e + (b + c + f) — (d + g + h)} is output. Further, the pixel value A 2 shown in equation (12) is calculated by performing a division process with a divisor of 8 by a divider 17 1 connected to the subsequent stage, and this calculation result is output from the divider 17 1 Is output.

The arithmetic processing of the pixel value A 3 is performed by the adders 13 1, 13 3, 13 5, 1 This is performed using 36, 140, a subtractor 152, a multiplier 160, and a divider 1772. Specifically, three pixel values d, g, and h are added by two adders 13 3 and 1 36, and three pixel values are added by the other two adders 13 1 and 1 35. Pixel values b, c, and f are added.

By inputting these two addition results to the subtractor 15 2, the output value (d + g + h) output from the adder 13 6 is calculated from the output value (d + g + h). The result of subtracting the output value (b + c + i), which is the addition result output from, is output.

Further, by adding the multiplication result (8e) of the multiplier 160 to the output value by the adder 140, the addition result (8e + (d + g + h)-(b + c + f)} is output. Further, the pixel value A3 shown in the equation (13) is calculated by performing the division process with the divisor 8 by the divider 172 connected at the subsequent stage, and the calculation result is output from the divider 172. Is output. The arithmetic processing of the pixel value A 4 is performed by adding the adders 13 0, 13 2, 13 4, 13 7, 14 1, the subtractor 15 3, the multiplier 16 0, and the divider 17 3 It is performed using and. Specifically, three pixel values f, h, and i are added by two adders 1332 and 137, and three pixel values are added by the other two adders 1330 and 1334. Pixel values a, b, and d are added.

By inputting these two addition results to the subtractor 15 3, the output value (f + h + i) which is the addition result output from the adder 13 7 is obtained. The result of subtracting the output value (a + b + d), which is the addition result output from, is output.

Further, by adding the multiplication result (8 e) of the multiplier 16 0 to this output value by the adder 14 1, the addition result {8 e + (f + h + i) 1 (a + b + d)} is output. Further, by performing a division process with a divisor of 8 by a divider 17 3 connected to the subsequent stage, the image shown in Expression (14) is obtained. The prime value A 4 is calculated, and the calculation result is output from the divider 173. The coefficients included in equations (11) to (14) described above also consist of a sequence of {8, 1, -1} numerical values, which is the basis of the finite-level sampling function shown in Fig. 6. Things. Therefore, it can be said that the interpolation calculations shown in the above equations (11) to (: 14) also interpolate the number of pixels without distortion using a finite number of sampling functions.

Therefore, even when the interpolation processing unit 2 enhances the image by the interpolation calculation of the equations (11) to (14), the phase of the color signal of the high-definition composite video signal after the interpolation is linear. The phase can be reversed between the images, and the YC separation can be performed after the image has been refined. Therefore, the memory to be prepared for interpolation of the number of pixels can be reduced to one for the composite video signal, and the circuit scale can be reduced.

In the above-mentioned Japanese Patent Application Laid-Open No. 2000-308021, in addition to the above equations (11) to (14), the following equations (15) to (18) or Equations (19)-(22) are also disclosed. In the present embodiment, interpolation may be performed by these calculations.

A 1 = {10 e + (a + b + d) — (c + f + g + h + i)} / 8--(15)

A 2 = {1 0 e + (b + c + f) — (a + d + g + h + i)} / 8 · • (16)

A 3 = {10 e + (d + g + h)-(a + b + c + f + i)} / 8

A 4 = {10 e + (f + h + i)-(a + b + c + d + g)} / 8--(18)

A 1 = {10 e + 2 b + 2 d-(c + f + g + h)} / 10 (19) A 2 = (10 .e + 2 b + 2 f-(a + d + h + i)} / 10---(20) A 3 = {10 e + 2 d + 2 h-(a + b + f + i)} / 10 (21) A 4 = {10 e + 2 f + 2 h-(b + c + d + g)} / 10---(22) In the above embodiment, the NTSC system is used as an example of an image signal. As described above, the present invention can be similarly applied to other signal standards such as the PAL system and the SECAM system.

Further, in the above-described embodiment, an example has been described in which the technique of YC separation is realized by a hardware configuration. However, it is also possible to realize the technique by DSP ゃ software or the like. For example, when realized by software, the YC separation device of this embodiment is actually configured with a computer CPU or MPU, RAM, ROM, etc., and is stored in RAM or ROM. It can be realized by running a program.

Therefore, the present invention can be realized by recording a program that causes a computer to perform the functions of the above-described embodiment on a recording medium such as a CD-ROM and reading it into the computer. As a recording medium for recording the above program, a flexible disk, a disk, a magnetic tape, an optical disk, a magneto-optical disk, a DVD, a nonvolatile memory card, and the like can be used in addition to the CD-ROM. In addition, it can be realized by downloading the above program to a computer via a network such as an Internet network.

Further, in order to realize the function of YC separation according to the above-described embodiment in a network environment, all or some of the programs may be executed by another computer.

Further, not only the functions of the above-described embodiment are realized by executing the supplied program by the computer, but also the operating system (OS) or other application software on which the program runs on the computer. If the functions of the above embodiment are realized in cooperation with Such a program is also included in the present invention when the functions of the above-described embodiments are realized by a user's function expansion board or function expansion unit. In addition, each of the above embodiments is merely an example of a specific embodiment for carrying out the present invention, and the technical scope of the present invention should not be interpreted in a limited manner. That is, the present invention can be embodied in various forms without departing from its spirit or its main features. Industrial applicability

INDUSTRIAL APPLICABILITY The present invention is useful for a device having a function of increasing the resolution by increasing the number of pixels constituting a color image by interpolation processing and increasing the definition of the image.

Claims

The scope of the claims

1. Using the pixel data of the target pixel and a plurality of peripheral pixels surrounding the target pixel, an interpolation operation using a finite number of sampling functions is performed to obtain the latest pixel in the diagonal direction between the target pixel and the target pixel. Interpolation processing means for obtaining an interpolated composite video signal comprising pixel data of an interpolated pixel on a straight line connecting each of the four peripheral pixels arranged at the tangent position;

Using the pixel data of each interpolated pixel obtained by the interpolation processing means, a first operation is performed on pixel data adjacent between lines to obtain a luminance signal from the interpolated composite video signal. An image processing apparatus comprising: a YC separation unit that separates a color signal from a color signal.

2. The YC separation unit performs the second operation on the pixel data adjacent in the line direction using the pixel data after the first operation, thereby obtaining the interpolated composite. · The image processing apparatus according to claim 1, further comprising means for adjusting a phase of a color signal separated from a video signal.