WO2004095579A1

WO2004095579A1 - Method of producing semiconductor integrated circuit device on soi substrate

Info

Publication number: WO2004095579A1
Application number: PCT/JP2003/005200
Authority: WO
Inventors: Jun Sakuma
Original assignee: Fujitsu Limited
Priority date: 2003-04-23
Filing date: 2003-04-23
Publication date: 2004-11-04

Abstract

A method of producing a semiconductor integrated circuit device comprising the steps of recognizing defects present on a substrate surface, covering the substrate surface including the defects with a layer, and patterning the layer in an element region defined on the substrate to form an element region pattern corresponding to the element region, the element region pattern forming step being implemented with the defects-containing regions excluded.

Description

Method of manufacturing semiconductor integrated circuit device on SOI substrate

The present invention generally relates to a semiconductor device, and more particularly to a method for manufacturing a semiconductor device on a SOI substrate. Background art

An SOI (silicon-on-insulator) substrate is a substrate in which a single-crystal Si layer that constitutes an active layer such as a channel layer is formed on an insulating film, achieving ideal element isolation and suppressing the short channel effect. It has various favorable features such as suppression of CMOS latch-up, suppression of soft errors, and suppression of parasitic capacitance, and is considered to be important as a substrate for future low power consumption ultra-high speed semiconductor circuit devices. .

An SOI substrate is formed by a process of bonding an Si substrate on which an SiO ₂ film is formed or by a process of implanting oxygen atoms into the Si substrate. Technologies that can do this are being developed.

FIG. 1 shows a cross-sectional view of a typical SOI substrate 10.

Referring to FIG. 1, SOI substrate 1 0 is formed on S i substrate 1 1 which carries the S io ₂ film 1 1 A thickness of a few hundred nanometers, the S i O ₂ film 1 1 On A, a single-crystal Si film 12 having a thickness of several tens to several hundreds of nanometers is formed.

FIG. 2 shows an example of a semiconductor integrated circuit device in which semiconductor elements are formed on the SOI substrate 10 of FIG.

Referring to FIG. 2, the single crystal Si film 12 is patterned in device regions 12A to 12D, and a MOS transistor is provided in each of the device regions 12A to 12D. Is formed. The element content Hanaremizo formed between adjacent element regions 1 2 A to 1 2 D is filled by S i 0 ₂ film 1 1 B.

In the semiconductor integrated circuit device having such a configuration, almost ideal element separation can be realized as described above, and the junction capacitance in each of the element regions 12A to 12D is lower than that by S i 0 ₂ It can be seen that it is reduced by the effect of forming the film 11A. On the other hand, such an SOI substrate cannot be formed simply by polishing a Si balta wafer, and the Si 0 ₂ film 11 A and the high-quality Si single crystal film 1 are formed on the Si substrate 11. It has a multilayer structure in which 2 are laminated. Therefore, as shown in FIG. 3, a defect 12 X or 12 Y may be formed due to damage or a defect of the Si single crystal layer 12 or the underlying Si〇 ₂ film 11 A. There is.

Therefore, the Si single crystal film 12 is patterned on the SOI substrate 10 including such defects 12 X and 12 Y by a normal mask process using a SiN mask, and is defined by the element isolation region. In order to form the formed element region, as shown in FIG. 4, the SiN film 13 formed as a mask pattern fills the defect 12X or 12Y.

Thus, an attempt was made to pattern such a SiN film 13 by a resist process to form mask patterns 13A to 13E corresponding to the element regions 12A to 12E, as shown in FIG. As described above, in the defect region 1 2 X, due to the lack of the exposure dose due to the local increase of the resist film at the step defining the defect, the tailing and the SiN residue 13 X is generated, and a defect surface formed on the SiO ₂ film 11A is exposed in the shallower defective region 12Y. However, in the example of FIG. 5, the defects 12X and 12Y are formed in the element regions 12C and 12D, respectively.

Therefore, depositing the S i 0 ₂ film 1 2 S on the structure of FIG. 5, the device isolation so as this is filled between the flattened by CMP S i N mask pattern 1 3 A to 1 3 G Attempting to form an insulating film pattern ^ \ As shown in FIG. 6, the slurry used in the CMP process is applied to the dicing surface of the Si〇2 film 12 S exposed in the defect region 12 Y. Participants such as grinding waste P force S may be trapped. Such trapped particles P cannot be easily removed by {Etching} scrubbing. On the other hand, these particles P may be liberated in a subsequent process, in which case, the production yield of the semiconductor device is reduced.

Further, in the state shown in FIG. 6, the SiN mask patterns 13A to 13G are removed by the etching process to expose the element regions 12A to 12E. At the same time, the tail that had occurred in area 1 2 X was also removed. As a result, it can be seen that voids are formed below the element isolation insulating film pattern in the defect region 12X. In addition, if the SiN residue 13 X previously generated in the step of FIG. 5 is also exposed on the surface of the SiO ₂ film 12 S as a result of the CMP step, When the etching process is performed, voids may be formed.

In the process of manufacturing a semiconductor device using a normal Si wafer, if there is a wafer having such a defect, the wafer is discarded as a defective wafer, thereby reducing the yield due to the wafer defect. The power of avoiding the decline Especially in the case of SOI substrates, etc., the price has recently been reduced, but it is expensive, and even with such a defect, the defect is relieved from the viewpoint of cost There are requirements that we want to use.

[Patent Document] Japanese Patent Application Laid-Open No. H8-3390974

[Patent Literature] Japanese Patent Application Laid-Open No. 2000-5311 18 Disclosure of the Invention

Accordingly, it is a general object of the present invention to provide a new and useful semiconductor device and a method for manufacturing the same, which have solved the above-mentioned problems.

More specific objects of the present invention are:

An object of the present invention is to provide a method of manufacturing a semiconductor device, which can efficiently use an expensive substrate without wasting even when a defect is included, and a semiconductor integrated circuit device manufactured by the manufacturing method.

Another object of the present invention is to

Recognizing a defect present on the substrate surface;

Covering the substrate surface with a layer,

Forming a device pattern in the device region on the substrate by patterning the layer,

The step of forming the element pattern is to perform a method of manufacturing a semiconductor integrated circuit device which is performed while avoiding the region including the defect.

Another object of the present invention is to Board and

In a semiconductor integrated circuit device comprising a semiconductor device formed on the substrate, the surface of the tflf substrate includes a recess defined by a step,

The recess is covered with a pattern filling the step,

The semiconductor device is to provide a semiconductor integrated circuit device formed so as to avoid the concave portion.

Another object of the present invention is to

Recognizing a defect present on the substrate surface;

Selectively filling the defects with a layer;

Forming an element region pattern in an element region defined on the substrate,

The step of forming the element region pattern is to perform a method of manufacturing a semiconductor integrated circuit device which is performed while avoiding the region including the defect.

According to the present invention, since the element formation is performed while avoiding the concave portions on the substrate surface, even if the substrate has a defect on the surface, it can be relieved and used. In particular, according to the present invention, the concave portion is covered with the mask pattern, so that no pattern jungling is performed in the concave portion. As a result, the problem of the formation of a defect pattern that occurs when exposure is performed in the presence of a step is avoided. Further, according to the present invention, by removing a mask pattern covering a defect after a chemical mechanical polishing step used for forming an element isolation insulating film, defects such as particles generated at the time of chemical polishing are removed. Can be removed simultaneously with the removal of the mask pattern.

Other features and characteristics of the present invention will become apparent from the following detailed description of the present invention with reference to the drawings. BRIEF DESCRIPTION OF THE FIGURES

Figure 1 is a diagram showing the cross-sectional structure of the SOI substrate;

FIG. 2 is a diagram showing an example of a semiconductor integrated circuit device formed on the SOI substrate of FIG. 1; FIG. 3 is a diagram showing an example of a defect included in the SOI substrate; 4 to 6 are diagrams illustrating problems that occur when a semiconductor device is formed on the SOI substrate including the defect of FIG. 3;

FIG. 7 is a plan view showing an SOI substrate used in the first embodiment of the present invention;

8A to 8H are views showing a manufacturing process of the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 9 is a plan view showing an SOI substrate used in a second embodiment of the present invention;

10A to 10C are diagrams showing a manufacturing process of a semiconductor integrated circuit device according to a second embodiment of the present invention;

11A to 11F are diagrams showing a manufacturing process of a semiconductor integrated circuit device according to a third embodiment of the present invention;

FIG. 12 is a view showing a modification of the third embodiment of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION

[First embodiment]

FIG. 7 is a plan view showing the SOI substrate 20 according to the first embodiment of the present invention.

Referring to FIG. 7, the SOI substrate 2 0 is shall to have a laminated structure described in Figure 1 above, a number of chip regions 2 0 Iota～ 2 0 ₉ is a matrix are separated by a scribe line Is defined. In the illustrated example, although the chip area _{2 0 ι~2 0 6, 2 08} ~ 2 0 9 does not include the defect, the chip area 2 0 _7, defects 1 2 X and 1 2 previously described Includes defect D similar to Y. In the following description, the defect area including these defects is also denoted by reference numerals 12X and 12Y.

Hereinafter, with reference to FIG. 8 A~8 H, explaining the manufacturing process of the semiconductor device to said chip region 2 0 _7.

In the step of initially Figure 8 A in the present embodiment, the CVD method the S i N film 1 3 on the SOI substrate 2 0, wherein S i N film 1 3 Te Contact Rere the chip area 2 0 ₇ defect 1 2 X, 1 2 Y is deposited so as to fill the, then at FIG. 8 B process, the S i N film 1 3 deposited in this way is patterned, the chip area 2 0 ₇ The SiN mask patterns 13A, 13B and 13E are formed corresponding to the element regions to be formed. 8B, the SiN film 13 is patterned by a resist process (not shown) based on the coordinates of the defect D obtained in the previous step of FIG. Are formed at the same time as the SiN mask patterns 13A, 13B and 13E. Next, the Si layer 12 is patterned using the SiN mask patterns 13A, 13B, 13C, 13D, and 13E as masks, and the element regions 12A to 13E correspond to the mask patterns 13A to 13E, respectively. : Forms I 2 E. However, since the element regions 12C and 12D have defects 12X and 12Y, even if the Si layer 12 is patterned using the SiN pattern 13C or 13D as a mask, these portions will not be present. No element region is formed, and a fragmentary Si pattern 12C or 12D is formed instead.

Due next high-density plasma using ivy CVD method in FIG. 8 C structural in the step of FIG. 8 D in the present embodiment, the S i 0 ₂ film 12 S of high quality, the S i 0 ₂ film said deposited so as to fill a portion between the element region 12A～12 E, polished by the CMP method in addition FIG. 8 E process it, between the device region 12A to 12E, the S i O ₂ With the film 12S, the element isolation insulating film pattern 11B described in FIG. 2 is formed.

Further, in the present embodiment, the SiN mask patterns 13A, 13B, 13C, 13D, and 13E are removed by a wet etching process in the step of FIG. 8F, and further obtained in the step of FIG. A polysilicon film 14 is deposited on the structure of FIG. 8F.

Further, in the step of FIG. 8H, the polysilicon film 14 thus formed is patterned in the element regions 12A, 12B and 12E excluding the defect regions 12X and 12Y to form polysilicon patterns 14A and 14E. Form B and 14E. Accordingly, the defect regions 12X and 12Y are covered with polysilicon films 14C and 14D. For example, in the element region 12A, the polysilicon pattern 14A forms a gate electrode. In this case, although not shown, a gate insulating film is formed between the single-crystal Si layer constituting the element region 12A and the polysilicon gate electrode pattern 14A, although not shown. ing. In the manufacturing process of the semiconductor device according to the present embodiment described above, after the defect regions 12X and 12Y are covered with the SiN film 13 in the step of FIG. 8A, the defect regions 12X and 12Y are removed. Since the covering SIN patterns 13C and 13D are lifted off in the process of FIG. 8F, for example, on the SiO2 film 12S covering the SIN pattern 13C or 13D in the CMP process of FIG. 8E. Even if foreign substances such as particles or defects exist in the substrate, these foreign substances and defects are removed together with the SiN patterns 13C and 13D, and are not carried into the steps after FIG. 8G.

In particular, the single-crystal Si film 12 has a thickness of 20 to 50 nm, the depths of the defects 12X and 12Y are 50 to 100 nm, and the single crystals at the defects 12X and 12Y. When the overhang amount of the Si film 12 is about 100 nm, the SiN film 13 is formed to a thickness of 150 nm, and the thickness of the Si film 14 is set to about 500 nm. The problem that foreign matter having a diameter of 0.1 / xm or more remains in the defect is avoided.

Further, the polysilicon film 14 formed in the step of FIG.8G is not patterned in the defect area 12X or 12Y in the step of FIG.8H, and therefore, even if there is a step in these defect areas. No defective pattern is formed due to poor exposure or the like.

In the present embodiment, the layer 13 used to form the mask patterns 13A to 13E is not limited to the SiN film, but may be a Si2 film or a metal film such as W. Is also possible.

[Second embodiment]

FIG. 9 shows an SOI substrate 40 according to a second embodiment of the present invention. However, in FIG. 9, the portions corresponding to the portions described above are denoted by the same reference numerals, and description thereof will be omitted. Referring to FIG. 9, this embodiment deals with a case where a large number of defects are formed in a specific chip area of the SOI substrate 40, for example, the area 207.

In the case where a large number of defects D are present on the chip region, the present invention can improve the production yield of the semiconductor device by excluding the chip itself from the subsequent processes.

Referring to FIG. 1 OA, the chip area 20ι to 20 shown in FIG. 9 and the chip area 4 OA and 4 OB is defined corresponding to one of the, in the chip region 4 0 B is missing that put in the single crystal S i film 1 2 and S I_〇 ₂ film 1 1 A As a result, a defect 41 X is formed.

Therefore, in the present embodiment, in the step of FIG. 1OB, the structure of FIG. 1OA is covered with a SiN film 13 and a resist film 41 is applied thereon.

Further, by exposing and developing the resist film 41 coated in this manner, resist patterns 41A to 41E are formed in the chip region 4OA, and the SiN film 13 is further formed. By performing patterning using the resist patterns 41A to 41E as a mask, the SIN patterns 13A to 13E are formed in the chip region 40A.

Further, in the subsequent steps, the Si single crystal film 12 is patterned using the resist patterns 13A to 13E as a mask, so that the SiN patterns 13A to 13A are formed in the chip region 4OA. An element region is formed corresponding to 3E.

On the other hand, in the present embodiment, as shown in FIG. 10C, an element is formed while the chip area 40 B including the defect 40 X is continuously covered with the SiN film 13. Absent.

Thus, in this embodiment, the area of the portion 12C, 12D where no element is formed due to the presence of the defect regions 12X, 12Y in the previous embodiment is extended to the entire chip. It can be thought that it did.

[Third embodiment]

Next, a manufacturing process of a semiconductor device according to a third embodiment of the present invention will be described with reference to FIGS. However, in the figure, parts corresponding to the parts described above are denoted by the same reference numerals, and description thereof will be omitted.

Referring to FIG. 11A, in this embodiment, the SOI substrate 11 including the defects 12 X and 12 Y is transported to the focused ion beam processing apparatus together with the coordinate values of the defect, and the defect region 1 Patterns 5 IX and 51 Y made of polysilicon or tungsten are deposited corresponding to 2 X and 12 Y, respectively, so as to cover the defects. Next, in the process of FIG. 11B, a patterning of a SiN film is performed on the structure of FIG. 11A. Thus, 311 ^ patterns 138, 13B and 13E are formed, and in the step of FIG. 11C, the single crystal Si film is formed using the SiN patterns 13A, 13B and 13E and the patterns 51X and 51Y as masks. 12 is patterned to form element regions 12A to 12E. However, of the element regions 12A to 12E thus formed, the regions 12C and 12D have the defects 12X and 12Y. Further, in the step of FIG. 11D, the structure of FIG. 11C is covered with a high-quality SiO ₂ film 12S formed by a high-density plasma CVD method, and in the step of FIG. The structure is polished to obtain a structure in which gaps between the element regions 12A to 12E are filled with the high-quality oxide film 12S.

Further, in the step of FIG. 11F, the metal patterns 5IX and 51Y are removed as necessary, and the steps described with reference to FIGS. 8G to 8H are further performed to obtain a desired semiconductor integrated circuit device. Can be

Further, in the present embodiment, in the step of FIG. 11A, the defect regions 12X and 12Y are formed, and as shown in FIG. 12, a step caused by the defect is formed by the polysilicon pattern 12P formed by the focused ion beam processing. It is also possible to fill to eliminate.

As described above, the present invention has been described with reference to the preferred embodiments. However, the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the gist of the claims. Industrial applicability

According to the present invention, since the element formation is performed while avoiding the concave portions on the substrate surface, even if the substrate has a defect on the surface, it can be relieved and used. In particular, according to the present invention, the concave portion is covered with the mask pattern, so that patterning is not performed in the concave portion. As a result, the problem of the formation of a defect pattern that occurs when exposure is performed in the presence of a step is avoided. Further, according to the present invention, by removing a mask pattern covering a defect after a chemical mechanical polishing step used to form an element isolation insulating film, defects such as particles generated during chemical opportunity polishing are removed. Can be removed simultaneously with the removal of the mask pattern. It is.

Claims

The scope of the claims

1. The substrate and

In a semiconductor integrated circuit device including a semiconductor device formed on the substrate, a concave portion defined by a step is included as a defect in the substrate surface, and the concave portion is formed by a pattern filling the step. Covered,

The semiconductor device is a semiconductor integrated circuit device formed avoiding the concave portion.

2. The semiconductor integrated circuit device according to claim 1, wherein the substrate is a SOI substrate.

3. The semiconductor integrated circuit device according to claim 1, wherein the pattern is made of a polysilicon film.

4. The semiconductor integrated circuit device according to claim 1, wherein the pattern comprises a metal film.

5. The semiconductor integrated circuit device according to claim 1, wherein the pattern comprises a SiO ₂ film.

6. The semiconductor integrated circuit device according to claim 1, wherein the pattern has a shape in which a central portion is recessed from a peripheral portion.

7. The semiconductor integrated circuit according to claim 1, wherein the pattern constitutes a substantially flat surface.

8. Recognizing defects present on the substrate surface;

Covering the substrate surface with a layer, including the defect,

Patterning the layer over an element region defined on the substrate to form an element region pattern corresponding to the element region,

The method of manufacturing a semiconductor integrated circuit device, wherein the step of forming the element region pattern is performed while avoiding the region including the defect.

9. The method for manufacturing a semiconductor integrated circuit device according to claim 8, wherein the substrate is an SOI substrate, and the defect is a concave portion formed on a surface of the SOI substrate.

10. The method of manufacturing a semiconductor integrated circuit device according to claim 8, wherein the step of forming the element region pattern is performed so that a portion of the layer covering the defect remains.

11. The step of forming the element region pattern includes: forming a first mask pattern so as to avoid the defect by patterning the layer; Forming a second mask pattern covering the defect by patterning the layer;

パ patterning the substrate using the first and second mask patterns as a mask, and forming the element region pattern corresponding to the element region; and forming the first mask pattern. 9. The method according to claim 8, wherein the step of forming the second mask pattern is performed simultaneously.

12. After the step of further forming the element region pattern, a step of forming an insulating film on the substrate so as to cover the first and second mask patterns; A step of chemical mechanical polishing including the mask pattern of 2,

12. The method for manufacturing a semiconductor integrated circuit device according to claim 11, further comprising: a step of removing said first and second mask patterns.

13. After further removing the first and second mask patterns, depositing a polysilicon layer on the substrate, patterning the polysilicon layer in the device region, and removing the device pattern. 13. The semiconductor integrated circuit device according to claim 12, further comprising: forming the element pattern, wherein the step of forming the element pattern is performed so that a portion of the polysilicon layer covering the defect remains. Production method.

1 4. The layers, S i N film, S i O ₂ film or the manufacturing method of a semiconductor integrated circuit device according to claim 8, wherein consisting metal film.

15. A process for recognizing defects existing on the substrate surface;

Selectively filling the defects with a layer;

16. The method for manufacturing a semiconductor integrated circuit device according to claim 15, wherein the step of selectively filling the defect is performed by focused ion beam processing.