WO2004086520A1 - ZnO SEMICONDUCTOR ELEMENT AND PROCESS FOR PRODUCING THE SAME - Google Patents
ZnO SEMICONDUCTOR ELEMENT AND PROCESS FOR PRODUCING THE SAME Download PDFInfo
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- WO2004086520A1 WO2004086520A1 PCT/JP2003/016323 JP0316323W WO2004086520A1 WO 2004086520 A1 WO2004086520 A1 WO 2004086520A1 JP 0316323 W JP0316323 W JP 0316323W WO 2004086520 A1 WO2004086520 A1 WO 2004086520A1
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- Prior art keywords
- zno
- layer
- substrate
- buffer layer
- main surface
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Links
- 238000000034 method Methods 0.000 title claims abstract description 56
- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 230000008569 process Effects 0.000 title abstract description 4
- 239000013078 crystal Substances 0.000 claims abstract description 96
- 239000000758 substrate Substances 0.000 claims abstract description 94
- 238000001027 hydrothermal synthesis Methods 0.000 claims abstract description 21
- 239000000872 buffer Substances 0.000 claims description 61
- 150000001875 compounds Chemical class 0.000 claims description 27
- 238000004519 manufacturing process Methods 0.000 claims description 25
- 238000010438 heat treatment Methods 0.000 claims description 22
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 230000003746 surface roughness Effects 0.000 claims description 7
- 230000001590 oxidative effect Effects 0.000 claims description 5
- -1 ZnO compound Chemical class 0.000 abstract 1
- 230000007547 defect Effects 0.000 description 26
- 239000007789 gas Substances 0.000 description 21
- 239000000463 material Substances 0.000 description 17
- 239000002019 doping agent Substances 0.000 description 13
- 239000012535 impurity Substances 0.000 description 13
- 229910052751 metal Inorganic materials 0.000 description 13
- 239000002184 metal Substances 0.000 description 13
- 239000011701 zinc Substances 0.000 description 9
- 229910052760 oxygen Inorganic materials 0.000 description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 7
- 239000000470 constituent Substances 0.000 description 7
- 239000001301 oxygen Substances 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 6
- 238000005520 cutting process Methods 0.000 description 6
- 229910052733 gallium Inorganic materials 0.000 description 6
- 229910052738 indium Inorganic materials 0.000 description 6
- 239000011777 magnesium Substances 0.000 description 6
- 229910052725 zinc Inorganic materials 0.000 description 6
- 239000011669 selenium Substances 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 206010021143 Hypoxia Diseases 0.000 description 4
- 229910052749 magnesium Inorganic materials 0.000 description 4
- 229910052755 nonmetal Inorganic materials 0.000 description 4
- 239000012808 vapor phase Substances 0.000 description 4
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 238000000407 epitaxy Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 239000007787 solid Substances 0.000 description 3
- WMFOQBRAJBCJND-UHFFFAOYSA-M Lithium hydroxide Chemical compound [Li+].[OH-] WMFOQBRAJBCJND-UHFFFAOYSA-M 0.000 description 2
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 2
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 description 2
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000004871 chemical beam epitaxy Methods 0.000 description 2
- AXAZMDOAUQTMOW-UHFFFAOYSA-N dimethylzinc Chemical compound C[Zn]C AXAZMDOAUQTMOW-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 125000005842 heteroatom Chemical group 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 229910052744 lithium Inorganic materials 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 229910052708 sodium Inorganic materials 0.000 description 2
- 229910052717 sulfur Inorganic materials 0.000 description 2
- 239000011593 sulfur Substances 0.000 description 2
- 229910052714 tellurium Inorganic materials 0.000 description 2
- PORWMNRCUJJQNO-UHFFFAOYSA-N tellurium atom Chemical compound [Te] PORWMNRCUJJQNO-UHFFFAOYSA-N 0.000 description 2
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 229910002091 carbon monoxide Inorganic materials 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 229910021478 group 5 element Inorganic materials 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 230000004807 localization Effects 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- QBJCZLXULXFYCK-UHFFFAOYSA-N magnesium;cyclopenta-1,3-diene Chemical compound [Mg+2].C1C=CC=[C-]1.C1C=CC=[C-]1 QBJCZLXULXFYCK-UHFFFAOYSA-N 0.000 description 1
- 238000001741 metal-organic molecular beam epitaxy Methods 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- HDZGCSFEDULWCS-UHFFFAOYSA-N monomethylhydrazine Chemical compound CNN HDZGCSFEDULWCS-UHFFFAOYSA-N 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052711 selenium Inorganic materials 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000001308 synthesis method Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- VOITXYVAKOUIBA-UHFFFAOYSA-N triethylaluminium Chemical compound CC[Al](CC)CC VOITXYVAKOUIBA-UHFFFAOYSA-N 0.000 description 1
- RGGPNXQUMRMPRA-UHFFFAOYSA-N triethylgallium Chemical compound CC[Ga](CC)CC RGGPNXQUMRMPRA-UHFFFAOYSA-N 0.000 description 1
- OTRPZROOJRIMKW-UHFFFAOYSA-N triethylindigane Chemical compound CC[In](CC)CC OTRPZROOJRIMKW-UHFFFAOYSA-N 0.000 description 1
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 1
- IBEFSUTVZWZJEL-UHFFFAOYSA-N trimethylindium Chemical compound C[In](C)C IBEFSUTVZWZJEL-UHFFFAOYSA-N 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Classifications
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B7/00—Single-crystal growth from solutions using solvents which are liquid at normal temperature, e.g. aqueous solutions
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B23/00—Single-crystal growth by condensing evaporated or sublimed materials
- C30B23/02—Epitaxial-layer growth
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
- C30B25/18—Epitaxial-layer growth characterised by the substrate
- C30B25/20—Epitaxial-layer growth characterised by the substrate the substrate being of the same materials as the epitaxial layer
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/10—Inorganic compounds or compositions
- C30B29/16—Oxides
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B7/00—Single-crystal growth from solutions using solvents which are liquid at normal temperature, e.g. aqueous solutions
- C30B7/005—Epitaxial layer growth
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B7/00—Single-crystal growth from solutions using solvents which are liquid at normal temperature, e.g. aqueous solutions
- C30B7/10—Single-crystal growth from solutions using solvents which are liquid at normal temperature, e.g. aqueous solutions by application of pressure, e.g. hydrothermal processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/024—Group 12/16 materials
- H01L21/02403—Oxides
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/02428—Structure
- H01L21/0243—Surface structure
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02551—Group 12/16 materials
- H01L21/02554—Oxides
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
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- H01L21/0257—Doping during depositing
- H01L21/02573—Conductivity type
- H01L21/02576—N-type
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0083—Processes for devices with an active region comprising only II-VI compounds
Definitions
- the present invention relates to a Z ⁇ ⁇ -based semiconductor device and a method for manufacturing the same.
- Zn ⁇ or Z ⁇ -based compounds using Z ⁇ as the base material have been used in semiconductors such as light-emitting devices such as light-emitting diodes and lasers, and transistor devices. It is promising as a constituent material of an element layer in an element. In manufacturing such a semiconductor device, it is necessary to epitaxially grow an element layer made of a Z ⁇ -based compound on the main surface of the substrate.
- ZnO single-crystal substrates manufactured by the CVT (Chemical Vapor Transport) method are not inexpensive due to manufacturing costs and lead to higher costs for semiconductor devices.
- a substrate different from the layer is used (for example, Japanese Patent Application Laid-Open No. 2001-68485).
- the present invention has been made in view of the above problems, and an object of the present invention is to improve the quality of an element layer easily, and at the same time, to provide a ZnO-based semiconductor element suitable from the viewpoint of cost, It is intended to provide a manufacturing method. Disclosure of the invention
- a ZnO-based semiconductor device of the present invention To solve the above problems, a ZnO-based semiconductor device of the present invention
- An element layer made of a Z ⁇ -based compound is formed on a main surface of a Z ⁇ single crystal substrate formed by a hydrothermal synthesis method by an epitaxy growth method.
- the device layer made of a ZnO-based compound is formed on the main surface of the Z11O single crystal substrate. Therefore, there is no excessive lattice mismatch between these substrates and the element layers, which has been a problem when a conventional sapphire substrate or the like is used. That is, generation of crystal defects and dislocations induced in the element layer due to the lattice mismatch can be reliably suppressed or prevented. As a result, the quality of the element layer can be easily and effectively improved.
- the Z ⁇ ⁇ single crystal substrate used in the present invention is formed by a hydrothermal synthesis method.
- Hydrothermal synthesis means that a single crystal is grown by mixing a material to be grown into a single crystal (in the present invention, ZnO) into a solvent and bringing the mixed solution to a state of supersaturated concentration or more in a cooling process. This is a synthesis method in which the material to be deposited is grown as a single crystal.
- the cost of the Z ⁇ ⁇ single crystal substrate formed by the hydrothermal synthesis method is 50% or less compared to that formed by the CVT method. Cost reduction of about 90% is possible.
- the hydrothermal synthesis method By using the formed Z ⁇ ⁇ single crystal substrate, it is possible to simply and effectively improve the quality of an element layer made of a ZnO-based compound formed on the main surface of the Z ⁇ ⁇ single crystal substrate. And an inexpensive semiconductor device.
- the Z ⁇ ⁇ -based compound constituting the above-mentioned element layer specifically, ZnO or a part of the Zn (zinc) site using ZnO as a base material and Mg (magnesium) etc.
- examples of such materials include those obtained by substitution and those obtained by substituting a part of the O (oxygen) site in ZnO with S (sulfur), Se (selen), Te (tellurium), and the like.
- the constituent material of the element layer is appropriately selected according to the element characteristics required for the semiconductor element, for example, according to the emission wavelength to be obtained in the element layer for a light-emitting element.
- the element layer in the Z ⁇ -based semiconductor element of the present invention is formed on the main surface of the Z ⁇ single-crystal substrate via a buffer layer made of a ZnO-based compound formed by an epitaxial growth method. It is desirable to be done.
- the element layer be formed on the main surface of the Z ⁇ single-crystal substrate via a buffer layer composed of a Z ⁇ -based compound formed by an epitaxial growth method. It can be said.
- a buffer layer composed of a Z ⁇ -based compound formed by an epitaxial growth method.
- the buffer layer in this manner, even when organic substances and particles are excessively attached to the main surface of the ZnO single crystal substrate, the thickness of crystal defects and dislocations caused by these organic substances and particles is also increased.
- the growth in the direction can be effectively suppressed or suppressed in the buffer layer.
- unintended processing strain caused by cutting such as slicing performed when forming a Z ⁇ ⁇ single crystal grown by a hydrothermal synthesis method on a substrate is caused by surface distortion. May be excessively present on the surface.
- the smoothness of the main surface of the Z ⁇ ⁇ single crystal substrate the higher the smoothness, the more the occurrence of crystal defects and dislocations in a layer to be epitaxially grown thereon can be suppressed. In addition, epitaxial growth is facilitated.
- the smoothness is low, that is, even if the surface is excessively rough, by forming the buffer layer as described above, growth of crystal defects and dislocations due to the smoothness in the layer thickness direction can be achieved. It can be effectively suppressed or suppressed in the buffer layer.
- RMS based on the JIS standard is used as an index of the smoothness.
- the surface roughness specified by the RMS be 2 nm or less.
- the lower limit of the RMS defined here is more preferably as small as possible. For example, it is sufficient to set the lower limit to 0.5 nm or more.
- Z ⁇ is particularly preferable among them, since lattice mismatch between the buffer layer and the ZnO single crystal substrate is smaller. Further, by employing Z ⁇ as a constituent material of the buffer layer, it is possible to more reliably suppress the occurrence of excessive composition fluctuation which is a problem in a mixed crystal system.
- the device layer is a light emitting layer portion.
- the Z ⁇ -based semiconductor element of the present invention can be applied to a known semiconductor element such as a light-emitting element such as a light-emitting diode-laser or a transistor element, and the element structure in the element layer is not particularly limited. That is, first, the present invention can be applied to a semiconductor element in which an element layer is formed on a main surface of a ZnO single crystal substrate by an epitaxial growth method. Among them, a light-emitting element in which the element layer is a light-emitting layer is particularly limited.
- ZnO is a direct-transition semiconductor having a band gap energy of 3.4 eV. ZnO-based compounds using ZnO or ⁇ nO as the base material emit light in the blue to ultraviolet range.
- light-emitting devices are a field particularly expected for the material properties of ZnO-based compounds.
- the quality of the element layer as the light emitting layer is required to be ensured.
- the method for manufacturing a Z ⁇ -based semiconductor device of the present invention comprises:
- the manufacturing method of the present invention is a method for manufacturing the Z ⁇ -based semiconductor device of the present invention described above.
- the substrate used in the production method of the present invention is a Z ⁇ single crystal formed by a hydrothermal synthesis method.
- the element layer forming step the main surface of the Z ⁇ single crystal substrate
- An element layer made of a Z ⁇ ⁇ -based compound is epitaxially grown thereon.
- the Z ⁇ ⁇ single crystal substrate to be used is obtained by subjecting the Z ⁇ ⁇ single crystal formed by hydrothermal synthesis to cutting such as slicing, so it is inexpensive from the viewpoint of cost.
- a semiconductor element can be obtained.
- the same compounds as those relating to the above-mentioned Z ⁇ -based semiconductor device of the present invention can be used.
- Specific methods for epitaxially growing the element layers include MOVPE (Metal Organic Vapor Phase Epitaxy) and MBE (Molecular
- a known vapor phase epitaxial growth method such as a beam epitaxy method can be used.
- the manufacturing method of the present invention desirably includes a substrate surface heat treatment step of performing a surface heat treatment on the main surface of the substrate in an oxidizing gas atmosphere.
- the above-mentioned interface impurities may be excessively present, and the interface impurities may cause crystal defects or dislocations. Therefore, performing at the substrate surface heat treatment step, the main surface of the substrate, N 2 0, NO, CO, surface heat treatment under an oxidizing gas atmosphere such as H 2 0.
- an oxidizing gas atmosphere such as H 2 0.
- interfacial impurities can be effectively released to the outside of the substrate in the form of an oxide or the like, and the concentration of interfacial impurities present on or near the main surface of the substrate can be reduced. It can be reduced effectively. It can also be expected to improve the surface smoothness. As a result, the surface condition on the main surface of the substrate can be improved, so that when the element layer is formed on the main surface of the substrate in the element layer forming step, the quality of the element layer is reduced. It is possible to further increase.
- the conditions of the surface heat treatment in the substrate surface heat treatment step include the purpose of preventing oxygen in the Z ⁇ ⁇ single crystal forming the substrate from desorbing from the substrate surface to the outside.
- the heat treatment temperature and the like in other cases are not particularly limited.
- the higher the heat treatment temperature the better the effect of releasing interface impurities to the outside of the substrate. Therefore, regarding the heat treatment temperature, it is particularly preferable that the heat treatment temperature is not less than 400 ° and not more than 900 °. By setting the heat treatment temperature to 400 ° C. or higher, it becomes possible to more effectively remove the interface impurities to the outside of the substrate.
- the heat treatment temperature exceeds 900 ° C., oxygen in the Z ⁇ single crystal forming the substrate is easily released from the substrate surface to the outside.
- a substrate having a main surface having a surface roughness of 2 nm or less in RMS it is preferable to use a substrate having a main surface having a surface roughness of 2 nm or less in RMS as the substrate.
- the surface state related to interface impurities on the main surface of the substrate has a great effect on the quality of the element layer formed thereon.
- the higher the smoothness of the main surface of the substrate the more the occurrence of crystal defects and dislocations in the element layer formed thereon can be suppressed. Therefore, it is desirable to use a substrate whose main surface has a surface roughness of 2 nm or less in RMS.
- the lower limit of the surface roughness specified by RMS is, of course, the smaller the smaller, the higher the smoothness.
- the surface roughness of the main surface of the substrate is determined by cutting the ZnO single crystal formed by the hydrothermal synthesis method into a substrate by performing a cutting process such as slicing. It can be adjusted by mechanical polishing, chemical polishing, or mechanical chemical polishing.
- the Z ⁇ -based compound constituting the buffer layer in the above-mentioned manufacturing method of the present invention specifically, the same compounds as those relating to the above-mentioned Z ⁇ -based semiconductor element of the present invention can be used. For the same reason, it is particularly desirable to use Z ⁇ ⁇ .
- Specific methods for epitaxially growing the buffer layer include MOVPE (Metal Organic Vapor Phase Jipitaxy) and MBE (Molecular Beam).
- a known vapor phase epitaxial growth method such as an Epitaxy method can be used.
- the buffer layer be grown at a temperature lower than the growth temperature of the element layer.
- the buffer layer plays a role in effectively preventing and suppressing crystal defects and dislocations generated due to the surface state of the main surface of the substrate from reaching the element layer.
- the buffer layer by growing the buffer layer at a temperature lower than the growth temperature of the element layer, the growth of crystal defects and dislocations in the thickness direction of the buffer layer can be effectively achieved in the process of forming the buffer layer. Can be suppressed. As a result, the quality of the element layer can be further improved.
- the formation temperature of the buffer layer at the time of such low-temperature growth is desirably 150 ° C. or more and 500 ° C. or less. If the temperature is lower than 150 ° C, the result is not enough to improve the orientation. In some cases, the crystallization energy cannot be applied as heat energy, so that the crystallinity of the buffer layer cannot be sufficiently secured, and it is also difficult to secure the crystallinity of the element layer. On the other hand, when the temperature exceeds 500 ° C., the growth of crystal defects and dislocations in the thickness direction in the buffer layer may not be sufficiently suppressed. On the other hand, if the growth temperature of the element layer is set to be 400 ° C. or more and 900 ° C. or less, the element layer will be a single crystal layer in which sufficient crystallinity such as crystal continuity and periodicity is secured. be able to.
- this buffer layer heat treatment step may be performed as an independent step before the element layer forming step, or, for example, after the buffer layer forming step, the element layer is formed in the element layer forming step.
- the temperature raising step required to raise the temperature at least higher than the growth temperature of the buffer layer, which is required for the above, can be used as the buffer layer heat treatment step.
- FIG. 1 is a schematic sectional view of a laminated structure to be a main part of a semiconductor device according to the present invention.
- FIG. 2 is a schematic view for explaining a method for manufacturing a ZnO single crystal substrate according to the present invention.
- FIG. 3 is a schematic sectional view of a laminated structure to be a main part of a light emitting device according to the present invention.
- FIG. 4 is a schematic cross-sectional view of a light emitting device according to a Z ⁇ ⁇ semiconductor device of the present invention.
- FIG. 1 schematically shows a laminated structure to be a main part of a Z ⁇ -based semiconductor device for explaining an embodiment of the present invention.
- an element made of a Z ⁇ -based compound is provided on a main surface of a Z ⁇ single-crystal substrate S formed by a hydrothermal synthesis method via a buffer layer 10 made of Z ⁇ .
- the layer 11 is formed.
- the buffer layer 10 and the element layer 11 are formed by an epitaxial growth method, and the MOVPE method or the MBE method can be used as the epitaxial growth method.
- MBE refers to a narrow sense MBE in which both a metal element component source and a nonmetal element component source are solid, and a nonmetal element component source in which the metal element component source is an organic metal.
- MOMB E Metal Organic Molecular Beam Epitaxy
- gas source MB E metal element source as solid and non-metal element source as gas
- MBE metal element source as organic metal and non-metal element source as gas
- the element layer 11 made of a Z ⁇ ⁇ -based compound is formed on the main surface of the Z ⁇ ⁇ single crystal substrate S, so that the element layer 11 is made to have a lattice mismatch with the substrate.
- the resulting crystal defects and dislocations are effectively suppressed, and the quality can be improved.
- the buffer layer 10 since the buffer layer 10 is formed, crystal defects and dislocations in the thickness direction of the crystal surface and dislocation at the main surface of the Z ⁇ ⁇ single crystal substrate S due to surface conditions such as surface distortion, interface impurities, and smoothness. Can be effectively suppressed in the buffer layer 10. As a result, the element layer 11 can be further improved in quality.
- the thickness of the buffer layer 10 that plays the role as described above depends on the surface condition of the Z ⁇ single crystal substrate S, but is preferably, for example, in the range of 1 nm or more and 100 nm or less. If the thickness is less than 1 nm, the growth of crystal defects and dislocations in the thickness direction may not be sufficiently suppressed.On the other hand, if the thickness exceeds 100 nm, the growth of crystal defects and dislocations in the thickness direction may be insufficient.
- the 2110 single crystal substrate 3 is formed by a hydrothermal synthesis method, so that the single crystal substrate Inexpensive semiconductor elements can be provided without incurring high costs based on the above.
- the ZnO single crystal substrate S formed by the hydrothermal synthesis method is manufactured by, for example, the following method and apparatus.
- FIG. 2 schematically shows an apparatus 20 for growing a Z ⁇ single crystal by a hydrothermal synthesis method.
- a Z ⁇ seed crystal 26 and a rod-shaped Z ⁇ sintered body 24 are arranged in the Pt root 25, a Z ⁇ seed crystal 26 and a rod-shaped Z ⁇ sintered body 24 are arranged.
- the Z ⁇ seed crystal 26 and the Z ⁇ sintered body 24 are separated by a Pt baffle plate 27, and the Pt crucible 25 is filled with an aqueous solution of KOH and LiOH.
- the Pt crucible 25 is sealed with a pressure cooker 23, and the pressure cooker 23 is disposed in the heaters 21 and 22. Then, the temperature of the autoclave 23 is raised to about 400 ° C., and a pressure of about 0.1 GPa is applied.
- the heaters 21 and 22 provide a region where the Z ⁇ seed crystal 26 is disposed. Is set to be about 10 ° C. lower than the temperature of the region where the Z ⁇ sintered body 24 is arranged. Under such growth conditions, a Z ⁇ single crystal can be obtained while growing a Z 11 O single crystal using the Z ⁇ ⁇ seed crystal 26 as a seed crystal. Then, the ZnO single crystal substrate S is obtained by subjecting the ZnO single crystal thus produced to a cutting process such as slicing and shaping into a shape of a Z ⁇ single crystal substrate S.
- the laminated structure 1 shown in FIG. 1 is to be a main part of the ZnO-based semiconductor element according to the present invention, and various element structures such as a light emitting element and a transistor element are formed using the laminated structure 1.
- various element structures such as a light emitting element and a transistor element are formed using the laminated structure 1.
- FIG. 3 schematically shows a laminated structure to be a main part of a light emitting device according to the present invention.
- an element layer 11 is formed on a main surface of a Z ⁇ single crystal substrate S via a buffer layer 10 made of Z ⁇ . This is the same as the laminated structure of FIG. However, the element layer 11 in FIG.
- MgZnO layer 3 composed of Mg-ZnO
- active layer 4 composed of Z ⁇ -based compound
- p-type MgZ ⁇ layer 5 are formed in order by double epitaxial growth method.
- the light emitting layer portion 11 of FIG. Further, as a constituent material of the active layer 4, a Z ⁇ -based compound according to a target emission wavelength is selected. A method for manufacturing the laminated structure 1 shown in FIG. 3 will be described.
- a buffer layer made of Z ⁇ is epitaxially grown on the main surface of the Z ⁇ single crystal substrate S.
- the element layer 11 which is to be a light emitting layer in the element layer forming step is epitaxially grown.
- Both the buffer layer formation step and the element layer formation step can be performed using a vapor phase epitaxial growth method such as the MOVPE method or the MBE method.
- the growth temperature of each of the buffer layer and the element layer is, for example, 150 ° C. or more and 500 ° C. or less, although it depends on the constituent materials.
- the following materials can be used as main materials of the buffer layer and the element layer, respectively.
- 'Oxidizing gas oxygen gas, N 2 0, NO, N0 2, CO, etc. H 2 0.
- Zn source (metal component source) gas dimethyl zinc (DMZn), getyl zinc (DEZn), etc.
- Mg source (metal component source) gas bis cyclopentadienyl magnesium (C p 2 M g) and the like.
- the n-type MgZ ⁇ layers 3 and ⁇ ! ) -Type MgZ ⁇ layer 5 contains an n-type dopant and a p-type dopant, respectively.
- the n-type dopant one or more of B, Al, Ga, and In Is contained.
- Group III elements B, Al, Ga and In can replace the group II elements Mg and Zn elements and dope n-type carriers.
- the p-type dopant one or more of Li, Na, Cu, N, P, As, Al, Ga, and In are contained.
- Group I elements L i and Na replace the group II elements Mg and Zn sites, and group V elements N, P and As replace the group VI O sites, resulting in p-type.
- CuO is a p-type semiconductor by son doping, by doping Cu to generate CuO, Cu functions as a p-type dopant.
- Al, Ga, In, and Li with N favorable p-type characteristics can be obtained more reliably.
- N having a ionic radius close to the Zn or O element and one or more of Ga, A1 and In, and particularly Ga are selected. It is preferred to do so.
- the p-type dopant one or more of Al, Ga, and In can be made to function as a good] type 3 dopant by co-addition with N.
- the following can be used as the dopant gas.
- A1 source gas trimethylaluminum (TMA1), triethylaluminum
- Ga source gas Trimethyl gallium (TMG a), triethyl gallium (TEG a), etc.
- TMI n Trimethyl indium
- TE In triethyl indium
- a gas serving as an N source for example, NH 3 , monomethylhydrazine, etc.
- N 20 usable as an oxidizing gas may be made to function as an N source.
- n-type carriers can be doped by adding one or more of Al, Ga and In as n-type dopants.
- the dopant gas the same gas as described above can be used.
- MgZnO is very susceptible to oxygen deficiency during layer growth in a vacuum atmosphere, and the conductivity type tends to be n-type. Therefore, in growing the n-type MgZnO layer 3 in FIG. 3, it is also possible to adopt a method in which oxygen deficiency is actively generated to make the n-type, and the active layer 4 and the p-type MgZnO layer 5 are formed. It is effective to lower the pressure atmosphere (for example, to less than 1 ⁇ 10 3 Pa) than when growing. At the same time, it is possible to dope the n-type carrier positively by growing the layer while introducing the n-type dopant.
- the oxygen partial pressure is preferably set to 1 X 10 3 P a or more.
- a part of the active layer 4 and a part of the p-type MgZnO layer 5 are subjected to photolithography as shown in FIG.
- a transparent electrode 32 made of ITO or the like is formed by partially removing the film by, for example, a graphic technique. Then, a metal electrode 31 is formed on the remaining p-type MgZnO layer 5 and then diced together with the ZnO single crystal substrate S. 0 is obtained.
- the ZnO-based semiconductor element is a light-emitting element having an element layer as a light-emitting layer portion, but can be applied to various semiconductor elements such as a laser element and a transistor element.
- the light emitting layer in FIGS. 3 and 4 is of a double hetero type, it may be of a single hetero type or a p-type layer and an n-type layer from the substrate side. It is good also as a form formed in order.
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Abstract
ZnO single crystal substrate (S) produced through hydrothermal synthesis procedure is used as a substrate, and element layer (11) constituted of a ZnO compound is formed on the main surface of the ZnO single crystal substrate (S) in accordance with the method of epitaxial growth. Thus, there are provided a ZnO semiconductor element and process for producing the same, wherein not only can a quality enhancement be easily realized for the element layer but also an advantage in cost can be ensured.
Description
明 細 書 Specification
Z η θ系半導体素子およびその製造方法 技術分野 Technical Field of the Invention
本発明は、 Z η θ系半導体素子およびその製造方法に関する。 背景技術 The present invention relates to a Z η θ-based semiconductor device and a method for manufacturing the same. Background art
近年の酸化物材料における薄膜ェピタキシャル成長技術の向上により、 Z n Oま たは Z η θを母物質とした Z η θ系化合物は、 発光ダイオードやレーザーなどの発 光素子、 トランジスタ素子といった半導体素子における素子層の構成材料として有 望視されている。 このような半導体素子を製造するにあたっては、 基板の主表面上 に Z η θ系化合物からなる素子層をェピタキシャル成長させる必要がある。 例えば C V T (Chemical Vapor Transport) 法にて製造されている Z n O単結晶基板は 製造コストに起因して安価なものではなく、 半導体素子のコスト高に繋がるので、 一般的にサファイア基板などの素子層とは異種の基板が用いられている (例えば、 特開 2 0 0 1— 6 8 4 8 5号公報） 。 With the recent improvement of thin film epitaxial growth technology for oxide materials, Znθ or Zηθ-based compounds using Zηθ as the base material have been used in semiconductors such as light-emitting devices such as light-emitting diodes and lasers, and transistor devices. It is promising as a constituent material of an element layer in an element. In manufacturing such a semiconductor device, it is necessary to epitaxially grow an element layer made of a Zηθ-based compound on the main surface of the substrate. For example, ZnO single-crystal substrates manufactured by the CVT (Chemical Vapor Transport) method are not inexpensive due to manufacturing costs and lead to higher costs for semiconductor devices. A substrate different from the layer is used (for example, Japanese Patent Application Laid-Open No. 2001-68485).
しかしながら、 上記のように、 Z η θ系化合物からなる素子層をサファイア基板 といつた素子層とは異種の基板上にェピタキシャル成長させる場合、 これら基板と 素子層との間には必然的に格子不整合が発生してしまう。 そして、 この格子不整合 は過大であるため、 該格子不整合に起因した結晶欠陥、 ミスフィット転位や貫通転 位などの転位が素子層に誘起されやすい。 そのため、 これら結晶欠陥や転位の発生 を抑制させるための結晶成長条件の適正化が必要となり、 半導体素子の製造に係わ る製造条件の複雑化を招くとともに、 素子層の品質を向上させるにも自ずと限界が 生じてしまう。
そこで、 基板として Z η θ単結晶基板を用いればよいのだが、 上述のごとく、 C V T法にて製造される Z η θ単結晶基板は安価なものではなく、 半導体素子のコス ト高を考慮すると、 とても使用できるものではない。 However, as described above, when an element layer made of a Zηθ-based compound is epitaxially grown on a substrate different from the element layer that is different from the sapphire substrate, an inevitable gap is formed between these substrates and the element layer. Lattice mismatch occurs. Since the lattice mismatch is excessive, crystal defects and dislocations such as misfit dislocations and threading dislocations due to the lattice mismatch are easily induced in the element layer. Therefore, it is necessary to optimize the crystal growth conditions to suppress the occurrence of these crystal defects and dislocations, which complicates the manufacturing conditions related to the manufacture of semiconductor devices and improves the quality of the device layers. Naturally, there are limits. Therefore, a Z η θ single crystal substrate may be used as the substrate, but as described above, the Z η θ single crystal substrate manufactured by the CVT method is not inexpensive, and considering the high cost of semiconductor elements. It is not very usable.
上記問題を鑑みてなされたのが本発明であって、 本発明の課題は、 簡便に素子層 の品質向上を可能とするとともに、 コストの観点からも適した Z n O系半導体素子 および、 その製造方法を提供することを目的とする。 発明の開示 The present invention has been made in view of the above problems, and an object of the present invention is to improve the quality of an element layer easily, and at the same time, to provide a ZnO-based semiconductor element suitable from the viewpoint of cost, It is intended to provide a manufacturing method. Disclosure of the invention
上記課題を解決するための本発明の Z n O系半導体素子は、 To solve the above problems, a ZnO-based semiconductor device of the present invention
水熱合成法により形成された Z η θ単結晶基板の主表面上に、 ェピタキシャル成 長法にて Z η θ系化合物からなる素子層が形成されてなることを特徴とする。 上記本発明の Z η θ系半導体素子において、 Z n O系化合物からなる素子層は、 Z 11 O単結晶基板の主表面上に形成されてなる。 そのため、 これら基板と素子層と の間には、 従来のサファイア基板などを用いた場合に問題となった過大な格子不整 合は存在しない。 つまり、 該格子不整合に起因して素子層に誘起される結晶欠陥や 転位の発生を、 確実に抑制ないし防止することができる。 その結果、 素子層の品質 を簡便に効果的に向上させることが可能となる。 また、 本発明において用いられる Z η θ単結晶基板は、 水熱合成法にて形成されたものとされる。 水熱合成法とは、 単結晶育成すべき材料 （本発明では Z n O) を溶媒に混合し、 その混合液を降温過 程にて過飽和濃度以上の状態にすることで、 単結晶育成すべき材料を単結晶として 析出育成する合成法である。 この水熱合成法を採用することで、 従来の C V T法に て形成された Z n O単結晶基板より格段に安価な Z n O単結晶基板とすることがで きる。 例えば、 同一径、 同一膜厚のゥエーハで比較した場合、 水熱合成法にて形成 した Z η θ単結晶基板は、 C V T法にて形成したものに比べて、 コスト面にて 5 0 %〜 9 0 %程度もコストの削減化が可能となる。 このように、 水熱合成法により
形成された Z η θ単結晶基板を用いることで、 該 Z η θ単結晶基板の主表面上に形 成される Z n O系化合物からなる素子層の品質を簡便に効果的に向上させることが 可能となるとともに、 安価な半導体素子とすることが可能となる。 An element layer made of a Zηθ-based compound is formed on a main surface of a Zηθ single crystal substrate formed by a hydrothermal synthesis method by an epitaxy growth method. In the Zηθ-based semiconductor device of the present invention, the device layer made of a ZnO-based compound is formed on the main surface of the Z11O single crystal substrate. Therefore, there is no excessive lattice mismatch between these substrates and the element layers, which has been a problem when a conventional sapphire substrate or the like is used. That is, generation of crystal defects and dislocations induced in the element layer due to the lattice mismatch can be reliably suppressed or prevented. As a result, the quality of the element layer can be easily and effectively improved. Further, the Z η θ single crystal substrate used in the present invention is formed by a hydrothermal synthesis method. Hydrothermal synthesis means that a single crystal is grown by mixing a material to be grown into a single crystal (in the present invention, ZnO) into a solvent and bringing the mixed solution to a state of supersaturated concentration or more in a cooling process. This is a synthesis method in which the material to be deposited is grown as a single crystal. By employing this hydrothermal synthesis method, a ZnO single crystal substrate that is much cheaper than a ZnO single crystal substrate formed by the conventional CVT method can be obtained. For example, when compared with a wafer having the same diameter and the same thickness, the cost of the Z η θ single crystal substrate formed by the hydrothermal synthesis method is 50% or less compared to that formed by the CVT method. Cost reduction of about 90% is possible. Thus, the hydrothermal synthesis method By using the formed Z η θ single crystal substrate, it is possible to simply and effectively improve the quality of an element layer made of a ZnO-based compound formed on the main surface of the Z η θ single crystal substrate. And an inexpensive semiconductor device.
上述の素子層を構成する Z η θ系化合物としては、 具体的には、 Z n Oや、 Z n Oを母物質として Z n (亜鉛） サイトの一部を M g (マグネシウム) などで置換さ せたものや、 Z n Oにおける O (酸素） サイトの一部を S (硫黄） 、 S e (セレ ン） 、 T e (テルル） などで置換させたものなどを例示することができる。 ただし、 素子層の構成材料は、 半導体素子において求められる素子特性に応じて、 例えば、 発光素子であれば素子層にて得るべき発光波長などに応じて適宜選択されるもので ある。 As the Z η θ-based compound constituting the above-mentioned element layer, specifically, ZnO or a part of the Zn (zinc) site using ZnO as a base material and Mg (magnesium) etc. Examples of such materials include those obtained by substitution and those obtained by substituting a part of the O (oxygen) site in ZnO with S (sulfur), Se (selen), Te (tellurium), and the like. However, the constituent material of the element layer is appropriately selected according to the element characteristics required for the semiconductor element, for example, according to the emission wavelength to be obtained in the element layer for a light-emitting element.
本発明の Z η θ系半導体素子における素子層は、 ェピタキシャル成長法にて形成 されてなる Z n O系化合物からなるバッファ層を介して、 Z η θ単結晶基板の主表 面上に形成されてなることが望ましい。 The element layer in the Zηθ-based semiconductor element of the present invention is formed on the main surface of the Zηθ single-crystal substrate via a buffer layer made of a ZnO-based compound formed by an epitaxial growth method. It is desirable to be done.
上記のように、 水熱合成法にて形成された Z η θ単結晶基板を用いることで、 安 価な半導体素子とするとともに、 基板との格子不整合に起因した結晶欠陥や転位の 発生を効果的に抑制した品質に優れた素子層とすることが可能となる。 しかしなが ら、 Z η θ単結晶基板の主表面やその表面近傍には、 水熱合成法による Z 11 O単結 晶形成時に起因した界面不純物が過度に存在する場合がある。 この界面不純物が過 度に存在する場合、 その上にェピタキシャル成長させる層に結晶欠陥や転位が発生 しゃすくなる。 そこで、 特には、 素子層は、 ェピタキシャル成長法にて形成された Z η θ系化合物からなるバッファ層を介した形で、 Z η θ単結晶基板の主表面上に 形成されるのが望ましいと言える。 このようにバッファ層を形成することで、 Z n O単結晶基板の主表面やその表面近傍に界面不純物が過度に存在した場合にも、 該 界面不純物に伴う結晶欠陥や転位の層厚方向への成長をバッファ層内にて効果的に 抑止ないしは抑制させることが可能となり、 ひいては、 素子層の品質をさらに向上
させることを可能とする。 また、 このようにバッファ層を形成することで、 Z n O 単結晶基板の主表面に有機物やパーティクルが過度に付着した場合にも、 これら有 機物やパーティクルに伴う結晶欠陥や転位の層厚方向への成長をバッファ層内にて 効果的に抑止ないしは抑制させることが可能となる。 また、 水熱合成法にて成長さ せた Z η θ単結晶を基板に成形する際に施されるスライス加工などの切削加工に起 因する意図しない加工歪が、 表面歪の形にて基板表面に過大に存在する場合がある。 この表面歪が過大である場合、 その上にェピタキシャル成長させる層には結晶欠陥 や転位が発生しやすくなるが、 バッファ層を形成することで、 該表面歪が過度に存 在した場合にも、 該表面歪に伴う結晶欠陥や転位の層厚方向への成長をバッファ層 内にて効果的に抑止ないしは抑制させることが可能となる。 As described above, by using a Z η θ single crystal substrate formed by hydrothermal synthesis, a low-cost semiconductor device can be obtained, and the occurrence of crystal defects and dislocations due to lattice mismatch with the substrate can be reduced. It becomes possible to obtain an element layer which is effectively suppressed and has excellent quality. However, there are cases where excessive interfacial impurities due to the formation of a Z 11 O single crystal by hydrothermal synthesis exist on the main surface of the Z η θ single crystal substrate and in the vicinity of the main surface. If this interfacial impurity is excessively present, crystal defects and dislocations are likely to be generated on a layer to be epitaxially grown thereon. Therefore, in particular, it is desirable that the element layer be formed on the main surface of the Zηθ single-crystal substrate via a buffer layer composed of a Zηθ-based compound formed by an epitaxial growth method. It can be said. By forming the buffer layer in this manner, even when interface impurities are excessively present on or near the main surface of the ZnO single crystal substrate, crystal defects and dislocations due to the interface impurities are caused in the layer thickness direction. Growth can be effectively suppressed or suppressed in the buffer layer, which further improves the quality of the element layer. It is possible to make. In addition, by forming the buffer layer in this manner, even when organic substances and particles are excessively attached to the main surface of the ZnO single crystal substrate, the thickness of crystal defects and dislocations caused by these organic substances and particles is also increased. The growth in the direction can be effectively suppressed or suppressed in the buffer layer. In addition, unintended processing strain caused by cutting such as slicing performed when forming a Z η θ single crystal grown by a hydrothermal synthesis method on a substrate is caused by surface distortion. May be excessively present on the surface. When this surface strain is excessive, crystal defects and dislocations are liable to occur in a layer to be epitaxially grown thereon, but by forming a buffer layer, even if the surface strain is excessively present, The growth of crystal defects and dislocations in the layer thickness direction due to the surface strain can be effectively suppressed or suppressed in the buffer layer.
また、 Z η θ単結晶基板の主表面の平滑性について言えば、 より平滑性が高いほ ど、 その上にェピタキシャル成長させる層への結晶欠陥や転位の発生を抑制するこ とができ、 かつェピタキシャル成長が容易となる。 勿論、 平滑性が低い、 つまりは、 表面が過度に粗い状態であっても、 上記のようにバッファ層を形成することにより、 この平滑性に伴う結晶欠陥や転位の層厚方向への成長をバッファ層内にて効果的に 抑止ないし抑制させることは可能である。 しかしながら、 特には、 Z n O単結晶基 板の主表面の平滑性としては、 該平滑性の指標として J I S規格に基づく RM S Further, regarding the smoothness of the main surface of the Z η θ single crystal substrate, the higher the smoothness, the more the occurrence of crystal defects and dislocations in a layer to be epitaxially grown thereon can be suppressed. In addition, epitaxial growth is facilitated. Of course, even if the smoothness is low, that is, even if the surface is excessively rough, by forming the buffer layer as described above, growth of crystal defects and dislocations due to the smoothness in the layer thickness direction can be achieved. It can be effectively suppressed or suppressed in the buffer layer. However, in particular, as the smoothness of the main surface of the ZnO single crystal substrate, RMS based on the JIS standard is used as an index of the smoothness.
(Root Mean Square：二乗平均粗さ) を代表させた場合、 該 RM Sにて規定される 表面粗さが 2 n m以下とされるものが望ましい。 このように、 RM Sが 2 n m以下 とされる主表面の Z n O単結晶基板を用いることにより、 該主表面上にェピタキシ ャル成長させる層への結晶欠陥や転位の発生を効果的に抑制することができ、 ひい ては、 素子層の品質をより高めることが可能となる。 なお、 ここで規定される RM Sの下限値としては、 小さいほどより望ましいが、 例えば、 0 . 5 n m以上として おけば十分である。 (Root Mean Square), it is desirable that the surface roughness specified by the RMS be 2 nm or less. As described above, by using a ZnO single crystal substrate having a main surface having an RMS of 2 nm or less, the generation of crystal defects and dislocations in a layer for epitaxial growth on the main surface can be effectively prevented. Thus, the quality of the element layer can be further improved. Note that the lower limit of the RMS defined here is more preferably as small as possible. For example, it is sufficient to set the lower limit to 0.5 nm or more.
上述のバッファ層を構成する Z η θ系化合物としては、 具体的には、 上述の素子
層と同様に、 ZnOや、 2110を母物質として211 (亜鉛） サイトの一部を MgAs the Zηθ-based compound constituting the buffer layer described above, specifically, the above-described device Similar to the layer, ZnO or a part of 211 (zinc)
(マグネシウム） などで置換させたものや、 Z nOにおける O (酸素） サイトの一 部を S (硫黄） 、 S e (セレン） 、 T e (テルル） などで置換させたものを例示す ることができる。 ただし、 バッファ層の構成材料としては、 この中でも、 Z nO単 結晶基板との間の格子不整合がより小さい、 Z ηθが特には好適であると言える。 また、 バッファ層の構成材料として Z ηθを採用することで、 混晶系において問題 とされる過度の組成揺らぎの発生をより確実に抑制することができる。 (Magnesium), etc., or those in which part of the O (oxygen) site in ZnO is replaced with S (sulfur), Se (selenium), Te (tellurium), etc. Can be. However, as a constituent material of the buffer layer, it can be said that Z ηθ is particularly preferable among them, since lattice mismatch between the buffer layer and the ZnO single crystal substrate is smaller. Further, by employing Z ηθ as a constituent material of the buffer layer, it is possible to more reliably suppress the occurrence of excessive composition fluctuation which is a problem in a mixed crystal system.
本発明の Z ηθ系半導体素子は、 例えば、 素子層が発光層部とされる。 In the Zηθ-based semiconductor device of the present invention, for example, the device layer is a light emitting layer portion.
本発明の Z ηθ系半導体素子としては、 発光ダイォードゃレーザーなどの発光素 子、 トランジスタ素子といった公知の半導体素子に適用可能であり、 その素子層に おける素子構造は特に限定されない。 つまり、 第一には、 Z nO単結晶基板の主表 面上に素子層がェピタキシャル成長法にて形成されてなる半導体素子に適用可能で ある。 その中でも特に限定するならば、 素子層が発光層部とされる発光素子である。 Z n Oは、 バンドギヤップエネルギーが 3. 4 e Vを有する直接遷移型の半導体で あり、 Z n Oまたは∑ n Oを母物質とした Z n O系化合物は、 青色から紫外域の発 光を可能とする発光層部の構成材料として特に有望視されている。 つまり、 Z nO 系化合物の材料特性に対して特に期待されている分野が、 発光素子なのである。 発 光層部としての素子層は、 その品質確保が必要とされている。 The Zηθ-based semiconductor element of the present invention can be applied to a known semiconductor element such as a light-emitting element such as a light-emitting diode-laser or a transistor element, and the element structure in the element layer is not particularly limited. That is, first, the present invention can be applied to a semiconductor element in which an element layer is formed on a main surface of a ZnO single crystal substrate by an epitaxial growth method. Among them, a light-emitting element in which the element layer is a light-emitting layer is particularly limited. ZnO is a direct-transition semiconductor having a band gap energy of 3.4 eV. ZnO-based compounds using ZnO or ∑nO as the base material emit light in the blue to ultraviolet range. Is particularly promising as a constituent material of the light-emitting layer portion that enables the above. In other words, light-emitting devices are a field particularly expected for the material properties of ZnO-based compounds. The quality of the element layer as the light emitting layer is required to be ensured.
次に、 本発明の Z ηθ系半導体素子の製造方法は、 Next, the method for manufacturing a Z ηθ-based semiconductor device of the present invention comprises:
水熱合成法により形成された Z n O単結晶を基板として、 該基板の主表面上に、 ZnO系化合物からなる素子層をェピタキシャル成長させる素子層形成工程を有す ることを特徴とする。 An element layer forming step of epitaxially growing an element layer made of a ZnO-based compound on a main surface of a substrate using a ZnO single crystal formed by a hydrothermal synthesis method as a substrate. .
上記本発明の製造方法は、 上述してきた本発明の Z ηθ系半導体素子の製造方法 である。 本発明の製造方法において用いる基板は、 水熱合成法により形成された Z ηθ単結晶である。 そして、 素子層形成工程にて、 この Z ηθ単結晶基板の主表面
上に、 Z η θ系化合物からなる素子層をェピタキシャル成長させる。 このように素 子層を形成することで、 基板との格子不整合に起因した結晶欠陥や転位の発生を簡 便に抑止ないし抑制することが可能となるとともに、 効果的に素子層の品質を向上 させることが可能となる。 使用する Z η θ単結晶基板は、 水熱合成法にて形成され た Z η θ単結晶をスライス加工などの切削加工を施すことにより得られるものであ るので、 コストの観点からも安価な半導体素子とすることが可能となる。 The manufacturing method of the present invention is a method for manufacturing the Zηθ-based semiconductor device of the present invention described above. The substrate used in the production method of the present invention is a Z ηθ single crystal formed by a hydrothermal synthesis method. Then, in the element layer forming step, the main surface of the Z ηθ single crystal substrate An element layer made of a Z η θ-based compound is epitaxially grown thereon. By forming the element layer in this way, it is possible to easily suppress or suppress the occurrence of crystal defects and dislocations due to lattice mismatch with the substrate, and to effectively reduce the quality of the element layer. It can be improved. The Z η θ single crystal substrate to be used is obtained by subjecting the Z η θ single crystal formed by hydrothermal synthesis to cutting such as slicing, so it is inexpensive from the viewpoint of cost. A semiconductor element can be obtained.
上曾己本発明の製造方法における素子層を構成する Z η θ系化合物としては、 具体 的には、 上述した本発明の Z η θ系半導体素子に係わるものと同様のものを用いる ことができる。 また、 素子層をェピタキシャル成長させる具体的な方法としては、 MO V P E (Metal Organic Vapor Phase Epitaxy) 法や、 MB E (Molecular As the Zηθ-based compound constituting the device layer in the manufacturing method of the present invention, specifically, the same compounds as those relating to the above-mentioned Zηθ-based semiconductor device of the present invention can be used. . Specific methods for epitaxially growing the element layers include MOVPE (Metal Organic Vapor Phase Epitaxy) and MBE (Molecular
Beam Epitaxy) 法などの公知の気相ェピタキシャル成長法を用いることができる。 本発明の製造方法においては、 基板の主表面に対して、 酸化性ガス雰囲気下にて 表面熱処理を行う基板表面熱処理工程を有することが望ましい。 A known vapor phase epitaxial growth method such as a beam epitaxy method can be used. The manufacturing method of the present invention desirably includes a substrate surface heat treatment step of performing a surface heat treatment on the main surface of the substrate in an oxidizing gas atmosphere.
用いる基板の主表面もしくはその表面近傍においては、 上述したような界面不純 物が過度に存在する場合があり、 該界面不純物は結晶欠陥や転位の発生要因となる。 そこで、 基板表面熱処理工程にて、 基板の主表面に対して、 N 2 0、 N O、 C O、 H 20等の酸化性ガス雰囲気下にて表面熱処理を行う。 このような基板表面熱処理 工程を行うことで、 界面不純物を酸化物などの形にて基板外部に効果的に離脱させ ることができ、 基板の主表面もしくは表面近傍に存在する界面不純物の濃度を効果 的に減少させることができる。 また、 表面の平滑性を高める効果も期待できる。 そ の結果、 基板の主表面における表面状態を良好なものとすることができるので、 該 基板の主表面上に上記素子層形成工程にて素子層を形成する際に、 該素子層の品質 をさらに高めることが可能となる。 On the main surface of the substrate to be used or in the vicinity thereof, the above-mentioned interface impurities may be excessively present, and the interface impurities may cause crystal defects or dislocations. Therefore, performing at the substrate surface heat treatment step, the main surface of the substrate, N 2 0, NO, CO, surface heat treatment under an oxidizing gas atmosphere such as H 2 0. By performing such a substrate surface heat treatment step, interfacial impurities can be effectively released to the outside of the substrate in the form of an oxide or the like, and the concentration of interfacial impurities present on or near the main surface of the substrate can be reduced. It can be reduced effectively. It can also be expected to improve the surface smoothness. As a result, the surface condition on the main surface of the substrate can be improved, so that when the element layer is formed on the main surface of the substrate in the element layer forming step, the quality of the element layer is reduced. It is possible to further increase.
上記基板表面熱処理工程における表面熱処理の条件としては、 基板をなす Z η θ 単結晶における酸素が基板表面から外部に離脱するのを防止する目的もあり、 酸化
性ガス雰囲気下が必須とされるが、 それ以外における熱処理温度などは特には限定 されない。 勿論、 熱処理温度が高いほど、 界面不純物を基板外部に離脱させる効果 は向上する。 そこで、 熱処理温度について言えば、 特には、 4 0 0 °じ以上9 0 0で 以下とするのが望ましい。 熱処理温度を 4 0 0 °C以上とすることで、 より効果的に 界面不純物を基板外部に離脱させることが可能となる。 一方、 熱処理温度が 9 0 0 °Cを超えると、 基板をなす Z η θ単結晶における酸素が基板表面から外部に離脱 しゃすくなる。 The conditions of the surface heat treatment in the substrate surface heat treatment step include the purpose of preventing oxygen in the Z η θ single crystal forming the substrate from desorbing from the substrate surface to the outside. Although it is essential to use an atmosphere of an inert gas, the heat treatment temperature and the like in other cases are not particularly limited. Of course, the higher the heat treatment temperature, the better the effect of releasing interface impurities to the outside of the substrate. Therefore, regarding the heat treatment temperature, it is particularly preferable that the heat treatment temperature is not less than 400 ° and not more than 900 °. By setting the heat treatment temperature to 400 ° C. or higher, it becomes possible to more effectively remove the interface impurities to the outside of the substrate. On the other hand, when the heat treatment temperature exceeds 900 ° C., oxygen in the Z ηθ single crystal forming the substrate is easily released from the substrate surface to the outside.
本発明の製造方法においては、 基板として、 該基板の主表面の表面粗さが RM S にて 2 n m以下のものを用いることが望ましい。 In the production method of the present invention, it is preferable to use a substrate having a main surface having a surface roughness of 2 nm or less in RMS as the substrate.
上述のごとく、 基板の主表面における界面不純物に係わる表面状態は、 その上に 形成される素子層の品質に大きく影響を及ぼす。 また、 平滑性に係わる表面状態に 関しては、 基板の主表面の平滑性がより高いほど、 その上に形成される素子層への 結晶欠陥や転位の発生を抑制することができる。 そこで、 基板として、 その主表面 の表面粗さが RM Sにて 2 n m以下のものを用いることが望ましい。 このように、 RM Sが 2 n m以下とされる主表面の基板を用いることで、 該主表面上に形成され る素子層の品質をさらに高めることができる。 ここで、 RM Sにて規定される表面 粗さの下限値であるが、 勿論、 小さいほど平滑性がより高いものとされるが、 例え ば、 0 . 5 n m以上としておけば十分である。 また、 基板の主表面における表面粗 さは、 水熱合成法にて形成された Z n O単結晶をスライス加工などの切削加ェを施 すことで基板に成形した後に、 該基板の主表面に対して機械的研磨、 化学的研磨や 機械的化学的研磨を施すことにより調整することが可能である。 As described above, the surface state related to interface impurities on the main surface of the substrate has a great effect on the quality of the element layer formed thereon. Regarding the surface condition related to the smoothness, the higher the smoothness of the main surface of the substrate, the more the occurrence of crystal defects and dislocations in the element layer formed thereon can be suppressed. Therefore, it is desirable to use a substrate whose main surface has a surface roughness of 2 nm or less in RMS. As described above, by using a substrate having a main surface with an RMS of 2 nm or less, the quality of an element layer formed on the main surface can be further improved. Here, the lower limit of the surface roughness specified by RMS is, of course, the smaller the smaller, the higher the smoothness. For example, it is sufficient to set it to 0.5 nm or more. The surface roughness of the main surface of the substrate is determined by cutting the ZnO single crystal formed by the hydrothermal synthesis method into a substrate by performing a cutting process such as slicing. It can be adjusted by mechanical polishing, chemical polishing, or mechanical chemical polishing.
本発明の製造方法においては、 素子層形成工程の前に、 基板の主表面上に、 Z n O系化合物からなるバッファ層をェピタキシャル成長させるバッファ層形成工程を 有することが望ましい。 In the manufacturing method of the present invention, it is preferable to include a buffer layer forming step of epitaxially growing a buffer layer made of a ZnO-based compound on the main surface of the substrate before the element layer forming step.
基板の主表面には、 水熱合成法にて形成された Z n O単結晶を基板に成形する際
に施されるスライス加工などの切削加工に起因する意図しない加工歪が、 表面歪の 形にて過大に存在する場合がある。 この表面歪が過大である場合、 その上にェピタ キシャル成長させる層には結晶欠陥や転位が発生しやすくなる。 しかしながら、 ノ ッファ層形成工程にてパッファ層を形成することで、 例え基板の主表面に意図しな い表面歪が過大に存在している場合においても、 該表面歪に伴う結晶欠陥や転位の 層厚方向への成長をパッファ層内にて効果的に抑止ないしは抑制させることが可能 となり、 ひいては、 素子層の品質をさらに向上させることを可能とする。 また、 界 面不純物や表面粗さに伴う結晶欠陥や転位の層厚方向への成長についても、 パッフ ァ層内にて効果的に抑止ないしは抑制させることが可能となる。 When the ZnO single crystal formed by hydrothermal synthesis is formed on the main surface of the substrate, In some cases, unintended machining strains resulting from cutting processes such as slicing performed on steel sheets are excessively present in the form of surface strains. If the surface strain is excessive, crystal defects and dislocations are liable to occur in a layer to be epitaxially grown thereon. However, by forming the puffer layer in the buffer layer forming step, even if unintended surface strain is excessively present on the main surface of the substrate, crystal defects and dislocations due to the surface strain are prevented. The growth in the layer thickness direction can be effectively suppressed or suppressed in the puffer layer, and the quality of the element layer can be further improved. In addition, the growth of crystal defects and dislocations in the layer thickness direction due to interface impurities and surface roughness can be effectively suppressed or suppressed in the buffer layer.
上記本発明の製造方法におけるバッファ層を構成する Z η θ系化合物としては、 具体的には、 上述した本発明の Z η θ系半導体素子に係わるものと同様のものを用 いることができるとともに、 同様の理由にて、 特には Z η θを用いるのが望ましい。 また、 バッファ層をェピタキシャル成長させる具体的な方法としては、 MO V P E (Metal Organic Vapor Phase Jipitaxy) 法や、 M B E (Molecular Beam As the Zηθ-based compound constituting the buffer layer in the above-mentioned manufacturing method of the present invention, specifically, the same compounds as those relating to the above-mentioned Zηθ-based semiconductor element of the present invention can be used. For the same reason, it is particularly desirable to use Z η θ. Specific methods for epitaxially growing the buffer layer include MOVPE (Metal Organic Vapor Phase Jipitaxy) and MBE (Molecular Beam).
Epitaxy) 法などの公知の気相ェピタキシャル成長法を用いることができる。 A known vapor phase epitaxial growth method such as an Epitaxy method can be used.
本発明の製造方法においては、 バッファ層を、 素子層の成長温度よりも低温にて 成長させることが望ましい。 In the manufacturing method of the present invention, it is desirable that the buffer layer be grown at a temperature lower than the growth temperature of the element layer.
バッファ層は、 上記のように、 基板の主表面の表面状態に起因して発生する結晶 欠陥や転位が素子層に至るのを効果的に抑制な V、し抑止する役割を担うものである。 このように、 バッファ層を素子層の成長温度よりも低温とされる温度にて低温成長 させることで、 バッファ層の形成過程において、 層厚方向も含めた結晶欠陥や転位 の成長を効果的に抑制することができる。 その結果、 素子層の品質をさらに高める ことが可能となる。 As described above, the buffer layer plays a role in effectively preventing and suppressing crystal defects and dislocations generated due to the surface state of the main surface of the substrate from reaching the element layer. As described above, by growing the buffer layer at a temperature lower than the growth temperature of the element layer, the growth of crystal defects and dislocations in the thickness direction of the buffer layer can be effectively achieved in the process of forming the buffer layer. Can be suppressed. As a result, the quality of the element layer can be further improved.
このような低温成長させる際のバッファ層の形成温度は、 1 5 0 °C以上 5 0 0 °C 以下とするのが望ましい。 1 5 0 °C未満であると、 配向性を十分に高めるための結
晶化エネルギーを熱エネルギーとして付与できない場合があり、 バッファ層の結晶 性を十分に確保できず、 ひいては素子層の結晶性も確保し難くなる。 一方、 5 0 0 °Cを超えると、 バッファ層内にて、 結晶欠陥や転位の層厚方向への成長を十分に 抑制できない場合がある。 一方、 素子層の成長温度は、 4 0 0 °C以上 9 0 0 °C以下 としておけば、 素子層を、 結晶の連続性や周期性といった結晶性が十分に確保され た単結晶層とすることができる。 The formation temperature of the buffer layer at the time of such low-temperature growth is desirably 150 ° C. or more and 500 ° C. or less. If the temperature is lower than 150 ° C, the result is not enough to improve the orientation. In some cases, the crystallization energy cannot be applied as heat energy, so that the crystallinity of the buffer layer cannot be sufficiently secured, and it is also difficult to secure the crystallinity of the element layer. On the other hand, when the temperature exceeds 500 ° C., the growth of crystal defects and dislocations in the thickness direction in the buffer layer may not be sufficiently suppressed. On the other hand, if the growth temperature of the element layer is set to be 400 ° C. or more and 900 ° C. or less, the element layer will be a single crystal layer in which sufficient crystallinity such as crystal continuity and periodicity is secured. be able to.
本発明の製造方法においては、 バッファ層形成工程の後、 バッファ層の成長温度 よりも高温にて熱処理を行うバッファ層熱処理工程を有することが望ましい。 In the manufacturing method of the present invention, it is preferable to include a buffer layer heat treatment step of performing a heat treatment at a temperature higher than the growth temperature of the buffer layer after the buffer layer formation step.
上記のようにバッファ層を低温成長させると、 形成されるバッファ層内において、 局所的に結晶の連続性や周期性が確保されずに多結晶粒が介在する不具合や、 局所 的に結晶が成長せずに隙間が介在する不具合などの結晶性の低下に繋がる不具合が 発生してしまう場合がある。 そこで、 このようなバッファ層熱処理工程を行うこと で、 バッファ眉に対して再結晶化を促進させることが可能となり、 ひいてはバッフ ァ層の結晶性を十分に確保することが可能となる。 なお、 このバッファ層熱処理ェ 程は、 素子層形成工程の前に独立した工程として行ってもよいし、 例えば、 パッフ ァ層形成工程の後に、 素子層形成工程にて素子層の形成を行うために必要とされる、 バッファ層の成長温度よりも少なくとも昇温させる昇温過程をバッファ層熱処理ェ 程とすることもできる。 図面の簡単な説明 When the buffer layer is grown at a low temperature as described above, in the buffer layer to be formed, defects such as localization of crystal continuity and periodicity are not ensured and polycrystalline grains are interposed, and local crystal growth occurs. Otherwise, there may be a problem that leads to a decrease in crystallinity such as a problem that a gap is interposed. Therefore, by performing such a buffer layer heat treatment step, recrystallization of the buffer eyebrows can be promoted, and thus the crystallinity of the buffer layer can be sufficiently ensured. Note that this buffer layer heat treatment step may be performed as an independent step before the element layer forming step, or, for example, after the buffer layer forming step, the element layer is formed in the element layer forming step. The temperature raising step required to raise the temperature at least higher than the growth temperature of the buffer layer, which is required for the above, can be used as the buffer layer heat treatment step. BRIEF DESCRIPTION OF THE FIGURES
図 1は、 本発明に係わる半導体素子の要部となるべき積層構造の概略断面図。 図 2は、 本発明に係わる Z n O単結晶基板の製造方法を説明するための模式図。 図 3は、 本発明に係わる発光素子の要部となるべき積層構造の概略断面図。 FIG. 1 is a schematic sectional view of a laminated structure to be a main part of a semiconductor device according to the present invention. FIG. 2 is a schematic view for explaining a method for manufacturing a ZnO single crystal substrate according to the present invention. FIG. 3 is a schematic sectional view of a laminated structure to be a main part of a light emitting device according to the present invention.
図 4は、 本発明の Z η θ系半導体素子に係わる発光素子の概略断面図。
発明を実施するための最良の形態 FIG. 4 is a schematic cross-sectional view of a light emitting device according to a Z η θ semiconductor device of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION
以下、 本発明を実施するための最良の形態を、 図面を用いて説明する。 Hereinafter, the best mode for carrying out the present invention will be described with reference to the drawings.
図 1は、 本発明の一実施形態を説明するための Z η θ系半導体素子の要部となる べき積層構造を模式的に示すものである。 該積層構造 1においては、 水熱合成法に て形成された Z η θ単結晶基板 Sの主表面上に、 Z η θからなるバッファ層 1 0を 介して、 Z η θ系化合物からなる素子層 1 1が形成されてなる。 ここで、 バッファ 層 1 0および素子層 1 1はェピタキシャル成長法にて形成されてなり、 このェピタ キシャル成長法としては、 MO V P E法もしくは MB E法などを用いることができ る。 なお、 本明細書において MB Eは、 金属元素成分源と非金属元素成分源との両 方を固体とする狭義の MB Eに加え、 金属元素成分源を有機金属とし非金属元素成 分源を固体とする MOMB E (Metal Organic Molecular Beam Epitaxy) 、 金属 元素成分源を固体とし非金属元素成分源を気体とするガスソース MB E、 金属元素 成分源を有機金属とし非金属元素成分源を気体とする化学ビームェピタキシ （C B E (Chemical Beam Epitaxy) ) を概念として含む。 FIG. 1 schematically shows a laminated structure to be a main part of a Zηθ-based semiconductor device for explaining an embodiment of the present invention. In the laminated structure 1, an element made of a Zηθ-based compound is provided on a main surface of a Zηθ single-crystal substrate S formed by a hydrothermal synthesis method via a buffer layer 10 made of Zηθ. The layer 11 is formed. Here, the buffer layer 10 and the element layer 11 are formed by an epitaxial growth method, and the MOVPE method or the MBE method can be used as the epitaxial growth method. In this specification, MBE refers to a narrow sense MBE in which both a metal element component source and a nonmetal element component source are solid, and a nonmetal element component source in which the metal element component source is an organic metal. MOMB E (Metal Organic Molecular Beam Epitaxy) as solid, gas source MB E as metal element source as solid and non-metal element source as gas, MBE as metal element source as organic metal and non-metal element source as gas Includes the concept of chemical beam epitaxy (CBE).
図 1に示すように、 Z η θ系化合物からなる素子層 1 1は Z η θ単結晶基板 Sの 主表面上に形成されてなるので、 素子層 1 1を、 基板との格子不整合に起因した結 晶欠陥や転位の発生が効果的に抑制された品質に優れたものとすることができる。 さらに、 バッファ層 1 0が形成されてなるので、 Z η θ単結晶基板 Sの主表面にお ける、 表面歪、 界面不純物や平滑性といった表面状態に起因する結晶欠陥や転位の 層厚方向への成長をバッファ層 1 0内にて効果的に抑制することができる。 その結 果、 素子層 1 1をさらに品質に優れたものとすることができる。 As shown in FIG. 1, the element layer 11 made of a Z η θ-based compound is formed on the main surface of the Z η θ single crystal substrate S, so that the element layer 11 is made to have a lattice mismatch with the substrate. The resulting crystal defects and dislocations are effectively suppressed, and the quality can be improved. Further, since the buffer layer 10 is formed, crystal defects and dislocations in the thickness direction of the crystal surface and dislocation at the main surface of the Z η θ single crystal substrate S due to surface conditions such as surface distortion, interface impurities, and smoothness. Can be effectively suppressed in the buffer layer 10. As a result, the element layer 11 can be further improved in quality.
上記のような役割を担うバッファ層 1 0の層厚は、 Z η θ単結晶基板 Sの表面状 態にもよるが、 例えば、 1 n m以上 1 0 0 n m以下の範囲としておくのがよい。 1 n m未満であると、 十分に結晶欠陥や転位の層厚方向への成長を抑制できない場合 があり、 一方、 1 0 0 n mを超えると、 十分に結晶欠陥や転位の層厚方向への成長
を抑制できるものの、 層厚の過大化のためにコスト高を招くことになるからである また、 2110単結晶基板3は、 水熱合成法にて形成されたものであるので、 単結 晶基板に基づくコスト高を招くことなく、 安価な半導体素子とすることができる。 水熱合成法にて形成される Z n O単結晶基板 Sは、 例えば以下のような方法および 装置により製造される。 The thickness of the buffer layer 10 that plays the role as described above depends on the surface condition of the Zηθ single crystal substrate S, but is preferably, for example, in the range of 1 nm or more and 100 nm or less. If the thickness is less than 1 nm, the growth of crystal defects and dislocations in the thickness direction may not be sufficiently suppressed.On the other hand, if the thickness exceeds 100 nm, the growth of crystal defects and dislocations in the thickness direction may be insufficient. However, the 2110 single crystal substrate 3 is formed by a hydrothermal synthesis method, so that the single crystal substrate Inexpensive semiconductor elements can be provided without incurring high costs based on the above. The ZnO single crystal substrate S formed by the hydrothermal synthesis method is manufactured by, for example, the following method and apparatus.
図 2は水熱合成法にて Z ηθ単結晶を育成するための装置 20の概略を示すもの である。 P tルツポ 25内に、 Z ηθ種結晶 26と、 棒状の Z ηθ焼結体 24が配 置されている。 これら Z ηθ種結晶 26と Z ηθ焼結体 24とは、 P tパッフル板 27で分離されており、 P tルツボ 25内には、 KOHおよび L i OHの水溶液が 充填されている。 そして、 この P tルツボ 25は、 耐圧釜 23でシールされており この耐圧釜 23がヒータ 21、 22内に配置されている。 そして、 この耐圧釜 23 の温度を約 400°Cに上昇させるとともに、 0. 1 GP a程度の圧力を印加させる, このとき、 ヒータ 21、 22により、 Z ηθ種結晶 26が配置されている領域の温 度を、 Z ηθ焼結体 24が配置されている領域の温度よりも約 10°C程度低く設定 しておく。 このような育成条件にて、 Z ηθ種結晶 26を種結晶として Z 11 O単結 晶を育成するとともに、 Z ηθ単結晶を得ることができる。 そして、 このように作 製した Z n O単結晶に対してスライス加工などの切削加工を施し、 Z ηθ単結晶基 板 Sの形状に成形することで、 Z n O単結晶基板 Sを得る。 FIG. 2 schematically shows an apparatus 20 for growing a Z ηθ single crystal by a hydrothermal synthesis method. In the Pt root 25, a Zηθ seed crystal 26 and a rod-shaped Zηθ sintered body 24 are arranged. The Z ηθ seed crystal 26 and the Z ηθ sintered body 24 are separated by a Pt baffle plate 27, and the Pt crucible 25 is filled with an aqueous solution of KOH and LiOH. The Pt crucible 25 is sealed with a pressure cooker 23, and the pressure cooker 23 is disposed in the heaters 21 and 22. Then, the temperature of the autoclave 23 is raised to about 400 ° C., and a pressure of about 0.1 GPa is applied. At this time, the heaters 21 and 22 provide a region where the Z ηθ seed crystal 26 is disposed. Is set to be about 10 ° C. lower than the temperature of the region where the Z ηθ sintered body 24 is arranged. Under such growth conditions, a Z ηθ single crystal can be obtained while growing a Z 11 O single crystal using the Z η θ seed crystal 26 as a seed crystal. Then, the ZnO single crystal substrate S is obtained by subjecting the ZnO single crystal thus produced to a cutting process such as slicing and shaping into a shape of a Zηθ single crystal substrate S.
図 1に示す積層構造 1は、 本発明に係わる Z n O系半導体素子の要部となるべき ものであり、 該積層構造 1を用いて発光素子やトランジスタ素子といった種々の素 子構造が形成される。 以下、 発光素子を代表させて、 本発明の Z ηθ系半導体素子 および製造方法に係わる実施形態について説明する。 The laminated structure 1 shown in FIG. 1 is to be a main part of the ZnO-based semiconductor element according to the present invention, and various element structures such as a light emitting element and a transistor element are formed using the laminated structure 1. You. Hereinafter, embodiments relating to a Z ηθ-based semiconductor device and a manufacturing method of the present invention will be described as a representative of a light emitting device.
図 3は、 本発明に係わる発光素子の要部となるべき積層構造を模式的に示すもの である。 図 3における積層構造 1においては、 Z ηθ単結晶基板 Sの主表面上に、 Z ηθからなるバッファ層 10を介して素子層 1 1が形成されてなり、 この点につ
いては図 1の積層構造と同様である。 しかしながら、 図 3における素子層 1 1は、 発光素子の素子構造に対応する形にて、 Z ηθ単結晶基板 S側から、 Mg l— a Z n aO (0≤ a≤ 1) (以下、 Mg Z nOとも言う） からなる n型 Mg Z n O層 3、 Z ηθ系化合物からなる活性層 4、 さらに p型 Mg Z ηθ層 5が順にェピタキシャ ル成長法にて形成されたダブルへテロ型の発光層部 1 1とされる。 また、 活性層 4 の構成材料としては、 目的とする発光波長に応じた Z ηθ系化合物が選定される。 図 3に示す積層構造 1の製造方法について説明する。 まず、 バッファ層形成工程 にて、 Z ηθ単結晶基板 Sの主表面上に Z ηθからなるバッファ層をェピタキシャ ル成長させる。 そして、 素子層形成工程にて発光層部とされる素子層 1 1を、 ェピ タキシャル成長させる。 これら、 バッファ層形成工程および素子層形成工程をとも に、 MOVP E法や MB E法などの気相ェピタキシャル成長法を用いて行うことが できる。 その際、 それぞれバッファ層おょぴ素子層の成長温度としては、 構成材料 にもよるが、 例えば、 1 50°C以上 5 00°C以下とされる。 また、 それぞれバッフ ァ層および素子層の主原料としては次のようなものを用いることができる。 FIG. 3 schematically shows a laminated structure to be a main part of a light emitting device according to the present invention. In the laminated structure 1 in FIG. 3, an element layer 11 is formed on a main surface of a Zηθ single crystal substrate S via a buffer layer 10 made of Zηθ. This is the same as the laminated structure of FIG. However, the element layer 11 in FIG. 3 has a shape corresponding to the element structure of the light-emitting element, from the side of the Z ηθ single crystal substrate S, M gl — a Z n a O (0≤a≤1) (hereinafter, referred to as MgZnO layer 3 composed of Mg-ZnO, active layer 4 composed of Z ηθ-based compound, and p-type MgZ ηθ layer 5 are formed in order by double epitaxial growth method. The light emitting layer portion 11 of FIG. Further, as a constituent material of the active layer 4, a Z ηθ-based compound according to a target emission wavelength is selected. A method for manufacturing the laminated structure 1 shown in FIG. 3 will be described. First, in a buffer layer forming step, a buffer layer made of Zηθ is epitaxially grown on the main surface of the Zηθ single crystal substrate S. Then, the element layer 11 which is to be a light emitting layer in the element layer forming step is epitaxially grown. Both the buffer layer formation step and the element layer formation step can be performed using a vapor phase epitaxial growth method such as the MOVPE method or the MBE method. At this time, the growth temperature of each of the buffer layer and the element layer is, for example, 150 ° C. or more and 500 ° C. or less, although it depends on the constituent materials. In addition, the following materials can be used as main materials of the buffer layer and the element layer, respectively.
'酸化性ガス ：酸素ガス、 N20、 NO、 N02、 CO、 H20など。 'Oxidizing gas: oxygen gas, N 2 0, NO, N0 2, CO, etc. H 2 0.
• S源ガス： H 2 Sなど。 • S source gas: H 2 S etc.
• S e源ガス ： H 2 S eなど。 • Se source gas: H 2 Se, etc.
• T e源ガス ： H2T eなど。 • Te source gas: H 2 Te etc.
• Z n源 (金属成分源) ガス：ジメチル亜鉛 （DMZ n) 、ジェチル亜鉛 （DE Z n) など。 • Zn source (metal component source) gas: dimethyl zinc (DMZn), getyl zinc (DEZn), etc.
• Mg源 （金属成分源） ガス ： ビスシクロペンタジェニルマグネシウム （C p 2M g) など。 • Mg source (metal component source) gas: bis cyclopentadienyl magnesium (C p 2 M g) and the like.
また、 発光層部とされる素子層 1 1を構成するそれぞれ n型 Mg Z ηθ層 3およ ぴ！)型 Mg Z ηθ層 5には、 それぞれ n型ドーパントおよび p型ドーパントが含有 されてなる。 n型ドーパントとしては、 B、 A l、 G a、 I nの 1種又は 2種以上
が含有される。 I I I族元素である B、 A l、 Ga、 I nは、 I I族元素である M g、 Z n元素を置換し、 n型キャリアをドーピングすることが可能である。 n型 M g Z ηθ層の結晶性を考慮し、 Z n元素のイオン半径に近い G aを、 n型ドーパン トとして選択することが好適である。 他方、 p型ドーパントとしては、 L i、 Na、 Cu、 N、 P、 A s、 A l、 Ga、 I nの 1種又は 2種以上が含有される。 I族元 素である L i、 Naは、 I I族元素である Mg、 Znサイトを置換し、 V族元素で ある N、 P、 Asは、 V I族である Oサイトを置換することにより p型キャリアを ドーピングすることが可能である。 CuOは、 ソンドーピングで p型半導体である ので、 Cuをドーピングし CuOを生成することにより、 Cuは p型ドーパントと して機能することになる。 また、 A l、 Ga、 I n、 L iは、 Nと共添加すること により、 良好な p型特性をより確実に得ることができる。 さらに、 p型 Mg Z nO 層 5の結晶性を考盧して、 Z nもしくは O元素にイオン半径が近い Nと、 Ga、 A 1及び I nの一種又は 2種以上、 特に Gaとを選択することが好適である。 The n-type MgZηθ layers 3 and ぴ! ) -Type MgZηθ layer 5 contains an n-type dopant and a p-type dopant, respectively. As the n-type dopant, one or more of B, Al, Ga, and In Is contained. Group III elements B, Al, Ga and In can replace the group II elements Mg and Zn elements and dope n-type carriers. In consideration of the crystallinity of the n-type M g Z ηθ layer, it is preferable to select Ga close to the ionic radius of the Zn element as the n-type dopant. On the other hand, as the p-type dopant, one or more of Li, Na, Cu, N, P, As, Al, Ga, and In are contained. Group I elements L i and Na replace the group II elements Mg and Zn sites, and group V elements N, P and As replace the group VI O sites, resulting in p-type. It is possible to dope carriers. Since CuO is a p-type semiconductor by son doping, by doping Cu to generate CuO, Cu functions as a p-type dopant. By co-adding Al, Ga, In, and Li with N, favorable p-type characteristics can be obtained more reliably. Further, considering the crystallinity of the p-type MgZnO layer 5, N having a ionic radius close to the Zn or O element and one or more of Ga, A1 and In, and particularly Ga are selected. It is preferred to do so.
上記のように、 p型ドーパントとして、 A l、 G a及び I nの 1種又は 2種以上 を、 Nとの共添加により良好な] 3型ドーパントとして機能させることができる。 ド 一パントガスとしては以下のようなものを使用できる。 As described above, as the p-type dopant, one or more of Al, Ga, and In can be made to function as a good] type 3 dopant by co-addition with N. The following can be used as the dopant gas.
• A 1源ガス ： トリメチルアルミニウム （TMA 1 ) 、トリエチルアルミニウム • A1 source gas: trimethylaluminum (TMA1), triethylaluminum
(TEA 1 ) など。 (TEA 1).
• G a源ガス ： トリメチルガリゥム (TMG a) 、トリェチルガリゥム (TEG a) など。 • Ga source gas: Trimethyl gallium (TMG a), triethyl gallium (TEG a), etc.
• I n源ガス ： トリメチルインジウム (TMI n) 、トリェチルインジウム (TE I n) など。 • In source gas: Trimethyl indium (TMI n), triethyl indium (TE In), etc.
p型ドーパントとして金属元素 （Ga) とともに Nが使用される場合、 p型 Mg Z ηθ層のェピタキシャル成長を行なう際に、 N源となる気体 （例えば NH3、 モ ノメチルヒ ドラジンなど） を、 Ga源となる有機金属ガスとともに供給するように
する。 また、 例えば、 酸化性ガスとして使用可能な N20を N源としても機能させ る形にしてもよい。 When N is used together with a metal element (Ga) as a p-type dopant, a gas serving as an N source (for example, NH 3 , monomethylhydrazine, etc.) is used for epitaxial growth of the p-type MgZηθ layer. So that it is supplied together with the organic metal gas I do. Further, for example, N 20 usable as an oxidizing gas may be made to function as an N source.
他方、 上述のように、 n型ドーパントとして、 A l、 G a及ぴ I nの 1種又は 2 種以上を添加することにより n型キャリアをドーピングすることができる。 ドーパ ントガスとしては、 上記同様なものが使用できる。 On the other hand, as described above, n-type carriers can be doped by adding one or more of Al, Ga and In as n-type dopants. As the dopant gas, the same gas as described above can be used.
また、 Mg Z nOは真空雰囲気中での層成長時に、 酸素欠損が非常に生じやすく、 導電型が n型となる傾向がある。 そこで、 図 3における n型 Mg Z nO層 3の成長 に際しては酸素欠損を積極的に生じさせて n型とする方法をとることも可能で、 活 性層 4及ぴ p型 Mg ZnO層 5を成長する場合よりも圧力雰囲気を下げる （例えば 1 X 103P a未満とする) ことが有効である。 また、 同時に n型ドーパントを導 入する形で層成長を行なうことにより積極的に n型キヤリァをドーピングすること も可能である。 Also, MgZnO is very susceptible to oxygen deficiency during layer growth in a vacuum atmosphere, and the conductivity type tends to be n-type. Therefore, in growing the n-type MgZnO layer 3 in FIG. 3, it is also possible to adopt a method in which oxygen deficiency is actively generated to make the n-type, and the active layer 4 and the p-type MgZnO layer 5 are formed. It is effective to lower the pressure atmosphere (for example, to less than 1 × 10 3 Pa) than when growing. At the same time, it is possible to dope the n-type carrier positively by growing the layer while introducing the n-type dopant.
他方、 活性層 4及ぴ p型 Mg Z n O層 5を成長させる場合、 l X 1 03P a以上、 特には 2. 5 X 103P a以上の圧力雰囲気下で行なうことにより、 成膜中の酸素 欠損発生をより効果的に抑制でき、 良好な特性の活性層 4あるいは p型 Mg Z nO 層 5を得ることができる。 この場合、 より望ましくは、 酸素分圧 （02以外の酸素 含有分子も、 含有される酸素を〇2に換算して組み入れるものとする） が 1 X 10 3P a以上とするのがよい。 さらに、 p型 Mg Z nO層 5を成長させる場合、 p型 Mg Z nO層 5の主原料となるガス流量を間欠的に中断させ、 酸化を促進すること で酸素欠損発生をさらに抑制することもできる。 On the other hand, when growing the active layer 4及Pi p-type Mg Z n O layer 5, l X 1 0 3 P a or more, particularly 2. By performing under a pressure atmosphere of more than 5 X 10 3 P a, formed Oxygen deficiency in the film can be more effectively suppressed, and the active layer 4 or the p-type MgZnO layer 5 having good characteristics can be obtained. In this case, more desirably, the oxygen partial pressure (oxygen-containing molecules other than 0 2 are also intended to incorporate by converting the oxygen contained in 〇 2) is preferably set to 1 X 10 3 P a or more. Furthermore, when growing the p-type MgZnO layer 5, it is possible to intermittently interrupt the gas flow rate, which is the main raw material of the p-type MgZnO layer 5, to further suppress the generation of oxygen deficiency by promoting oxidation. it can.
以上のようにしてバッファ層 10および発光層部とされる素子層 1 1の形成が終 了すれば、 図 4に示すように活性層 4及ぴ p型 Mg Z nO層 5の一部をフォトリソ グラフィ一等により一部除去して、 I TO等からなる透明電極 32を形成する。 そ して、 残余の p型 Mg Z nO層 5上には金属電極 3 1を形成し、 その後、 Z nO単 結晶基板 Sとともにダイシングすれば、 発光素子とされる Z nO系半導体素子 10
0が得られる。 When the formation of the buffer layer 10 and the element layer 11 serving as the light emitting layer portion is completed as described above, a part of the active layer 4 and a part of the p-type MgZnO layer 5 are subjected to photolithography as shown in FIG. A transparent electrode 32 made of ITO or the like is formed by partially removing the film by, for example, a graphic technique. Then, a metal electrode 31 is formed on the remaining p-type MgZnO layer 5 and then diced together with the ZnO single crystal substrate S. 0 is obtained.
以上、 本発明の一実施形態を説明したが、 本発明はこれに限定されるものではな く、 請求項の記載に基づく技術的範囲を逸脱しない限り、 種々の変形ないし改良を 付加することができる。 例えば、 図 3および図 4において、 Z n O系半導体素子は 素子層を発光層部とする発光素子とされるが、 例えばレーザ素子やトランジスタ素 子といった種々の半導体素子に適用可能である。 また、 図 3およぴ図 4における発 光層部はダブルへテロ型とされるが、 シングルヘテロ型のものとしてもよいし、 さ らには、 基板側より p型層、 n型層の順に形成される形としてもよい。
As described above, one embodiment of the present invention has been described, but the present invention is not limited to this, and various modifications or improvements can be added without departing from the technical scope based on the description of the claims. it can. For example, in FIGS. 3 and 4, the ZnO-based semiconductor element is a light-emitting element having an element layer as a light-emitting layer portion, but can be applied to various semiconductor elements such as a laser element and a transistor element. Although the light emitting layer in FIGS. 3 and 4 is of a double hetero type, it may be of a single hetero type or a p-type layer and an n-type layer from the substrate side. It is good also as a form formed in order.
Claims
1. 水熱合成法により形成された ZnO単結晶基板の主表面上に、 ェピタキシ ャル成長法にて Z n O系化合物からなる素子層が形成されてなることを特徴とする Z nO系半導体素子。 1. A ZnO-based semiconductor characterized in that an element layer composed of a ZnO-based compound is formed on a main surface of a ZnO single crystal substrate formed by a hydrothermal synthesis method by an epitaxial growth method. element.
2. 前記素子層は、 ェピタキシャル成長法にて形成されてなる ZnO系化合物 からなるバッファ層を介して、 前記求 Z n O単結晶基板の主表面上に形成されてなる ことを特徴とする請求の範囲第 1項記載のの Z n O系半導体素子。 2. The element layer is formed on a main surface of the ZnO-based single crystal substrate via a buffer layer made of a ZnO-based compound formed by an epitaxial growth method. 2. The ZnO-based semiconductor device according to claim 1.
3. 前記素子層が発光層部とされる発光素子であることを特徴とする請求の範 囲 3. The device according to claim 1, wherein the device layer is a light-emitting device serving as a light-emitting layer portion.
囲第 1項または第 2項に記載の Z ηθ系半導体素子。 3. The Z ηθ-based semiconductor device according to item 1 or 2.
4. 水熱合成法により形成された ZnO単結晶を基板として、 該基板の主表面 上に、 Z nO系化合物からなる素子層をェピタキシャル成長させる素子層形成工程 を有することを特徴とする Z n O系半導体素子の製造方法。 4. Using a ZnO single crystal formed by a hydrothermal synthesis method as a substrate, comprising a device layer forming step of epitaxially growing a device layer made of a ZnO-based compound on a main surface of the substrate. n O-based semiconductor element manufacturing method.
5. 前記基板の主表面に対して、 酸化性ガス雰囲気下にて表面熱処理を行う基 板表面熱処理工程を有することを特徴とする請求の範囲第 4項記載の Z 11 O系半導 体素子の製造方法。 5. The Z 11 O-based semiconductor device according to claim 4, further comprising a substrate surface heat treatment step of performing a surface heat treatment on the main surface of the substrate in an oxidizing gas atmosphere. Manufacturing method.
6. 前記基板としては、 該基板の主表面の表面粗さが RMSにて 2 nm以下の ものを用いることを特徴とする請求の範囲第 4項または第 5項に記載の Z n O系半 導体素子の製造方法。 6. The ZnO-based half according to claim 4 or 5, wherein the substrate has a main surface having a surface roughness of 2 nm or less in RMS. A method for manufacturing a conductive element.
7. 前記素子層形成工程の前に、 前記基板の主表面上に、 ZnO系化合物から なるバッファ層をェピタキシャル成長させるバッファ層形成工程を有することを特 徴とする請求の範囲第 4項ないし第 6項のいずれか 1項に記載の Z n O系半導体素 子の製造方法。 7. The method according to claim 4, further comprising, before the element layer forming step, a buffer layer forming step of epitaxially growing a buffer layer made of a ZnO-based compound on the main surface of the substrate. 7. The method for producing a ZnO-based semiconductor device according to any one of clauses 6.
8. 前記バッファ層を、 前記素子層の成長温度よりも低温にて成長させること を特徴とする請求の範囲第 7項記載の Z ηθ系半導体素子の製造方法。
8. The method according to claim 7, wherein the buffer layer is grown at a temperature lower than a growth temperature of the element layer.
9 . 前記バッファ層形成工程の後、 前記バッファ層の成長温度よりも高温にて 熱処理を行うバッファ層熱処理工程を有することを特徴とする請求の範囲第 8項記 载の Z n O系半導体素子の製造方法。
9. The ZnO based semiconductor device according to claim 8, further comprising a buffer layer heat treatment step of performing a heat treatment at a temperature higher than a growth temperature of the buffer layer after the buffer layer formation step. Manufacturing method.
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| JP4851103B2 (en) * | 2005-03-01 | 2012-01-11 | 学校法人常翔学園 | Zinc oxide transistor |
| JP4610422B2 (en) | 2005-06-21 | 2011-01-12 | スタンレー電気株式会社 | Manufacturing method of ZnO substrate |
| JP3945782B2 (en) | 2005-09-06 | 2007-07-18 | シチズン東北株式会社 | Semiconductor light emitting device and manufacturing method thereof |
| JP4921761B2 (en) * | 2005-09-30 | 2012-04-25 | 東京電波株式会社 | Method for producing zinc oxide single crystal substrate |
| WO2008111277A1 (en) * | 2007-03-15 | 2008-09-18 | Kyushu Institute Of Technology | Single crystal zinc oxide substrate |
| JP5355221B2 (en) * | 2009-05-25 | 2013-11-27 | スタンレー電気株式会社 | Method for growing zinc oxide based semiconductor and method for manufacturing semiconductor light emitting device |
| JP5638772B2 (en) * | 2009-05-25 | 2014-12-10 | スタンレー電気株式会社 | Method for growing zinc oxide based semiconductor and method for manufacturing semiconductor light emitting device |
| JP5411681B2 (en) * | 2009-12-09 | 2014-02-12 | スタンレー電気株式会社 | Method for growing zinc oxide based semiconductor and method for manufacturing semiconductor light emitting device |
| JP5893981B2 (en) * | 2012-03-23 | 2016-03-23 | スタンレー電気株式会社 | Magnesium / Zinc Oxide Crystal Growth Method |
| JP5893980B2 (en) * | 2012-03-23 | 2016-03-23 | スタンレー電気株式会社 | Magnesium / Zinc Oxide Crystal Growth Method |
| JP6368980B2 (en) * | 2013-08-20 | 2018-08-08 | 正幸 安部 | Semiconductor device |
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| JPH09270543A (en) * | 1996-04-01 | 1997-10-14 | Asahi Chem Ind Co Ltd | Flat oxide piezoelectric board, manufacturing method of oxide board and device |
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