WO2004086512A1

WO2004086512A1 - Semiconductor memory

Info

Publication number: WO2004086512A1
Application number: PCT/JP2003/003682
Authority: WO
Inventors: Ayako Sato
Original assignee: Fujitsu Limited
Priority date: 2003-03-26
Filing date: 2003-03-26
Publication date: 2004-10-07

Abstract

A semiconductor memory in which the unit memory size is reduced while increasing the operating speed and a nonvolatile data retaining function for retaining data even if power is not supplied can be realized by connecting the output nodes of nonvolatile semiconductor memory circuits MT1 and MT2 for retaining the memory state by storing in the trap area in a nitride film charges with the internal nodes N1 and N2 of a volatile memory circuit (10) for latching the output of the nonvolatile semiconductor memory circuits MT1 and MT2.

Description

Semiconductor storage device technology

The present invention relates to a semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device configured by connecting a volatile memory circuit and a nonvolatile memory circuit. Background art

• Conventionally, there has been a non-volatile memory cell configured by combining a non-volatile bright memory element using a ferroelectric substance and a volatile memory cell. For example, as disclosed in Japanese Unexamined Patent Application Publication No. Hei 8-246472, a nonvolatile random access memory constructed by connecting a ferroelectric capacitor to an SRAM (Static Random Access Memory) type volatile memory cell is disclosed. There was a memory cell.

However, the conventional non-volatile memory cell configured as described above has problems such as that a long time is required for a re-read operation or the like, and that a predetermined start-up process must be executed at the start-up after power-on. Was. In addition, there is a problem that the size of one storage unit of a nonvolatile memory cell (the circuit scale required to store one data) is large. In addition, the conventional nonvolatile memory cell is a normal logic unit including a volatile memory cell. The use of a special material (ferroelectric material) that is different from non-volatile memory elements greatly increases the number of steps in the manufacturing process.

Patent Document 1

Unexamined Japanese Patent Application Publication No. Hei 8-2,64,728

The present invention has been made in order to solve such a problem, and has a semiconductor memory including a volatile memory circuit and a nonvolatile memory circuit, which has a high operation speed and a small circuit scale required for storing one data. It is intended to provide a device.

According to the semiconductor memory device of the present invention, the electric charge is stored in the trap region in the nitride film to store the electric charge. A non-volatile semiconductor storage circuit that holds a state, and a volatile storage circuit that latches an output of the non-volatile semiconductor storage circuit. The output node of the non-volatile semiconductor storage circuit and the internal node of the volatile storage circuit Connect.

According to the present invention, it is possible to realize a nonvolatile data holding function of holding data even when power is not supplied, and to store data by a nonvolatile semiconductor memory circuit having a size of one transistor, and to store the stored data in a volatile manner. The signal can be output in a short time by the storage circuit.

In the case where a plurality of nonvolatile semiconductor memory circuits are provided and an output signal can be changed by selectively driving the plurality of nonvolatile semiconductor memory circuits, a plurality of data are stored. The output signal can be changed easily and at any time only by controlling the selection signal. BRIEF DESCRIPTION OF THE FIGURES

1A to 1C are diagrams for explaining a MONOS type storage element.

FIG. 2 is a diagram showing a configuration example of a memory cell in the semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is a timing chart showing a data read operation from the MONOS element in the semiconductor memory device according to the first embodiment.

FIG. 4 is a timing chart showing a data programming operation to the MONOS element in the semiconductor memory device according to the first embodiment.

FIG. 5 is a timing chart showing a data erasing operation of the MONOS element in the semiconductor memory device according to the first embodiment.

FIG. 6 is a diagram showing a configuration example of a memory cell in the semiconductor memory device according to the second embodiment of the present invention.

FIG. 7 is a diagram showing a configuration example of a memory cell in the semiconductor memory device according to the third embodiment of the present invention.

FIG. 8 is a diagram illustrating another configuration example of the memory cell according to the third embodiment. FIG. 9 is a diagram showing a configuration example of a memory cell in the semiconductor memory device according to the fourth embodiment of the present invention. FIG. 10 is a timing chart showing a data read operation of the MONOS element in the semiconductor memory device according to the fourth embodiment.

FIGS. 11 to 16 are diagrams showing another configuration example of the memory cell according to the fourth embodiment. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1A to 1C illustrate a MONO S (Metal-Oxide-Nitride-Oxide-Silicon) storage element (hereinafter also referred to as a “MOMO S element”), which is one of nonvolatile storage elements. FIG. The MONO S element has high compatibility with the CMO S process (standard Si process), and adds several steps to the logic process for forming a normal logic section without using special materials (for example, adding a mask). It can be made by simply adding two).

FIG. 1A is a device cross-sectional view showing an example of the structure of the MONOS element. The MON OS element includes a semiconductor (silicon) substrate 1, a first gate oxide film 2, a nitride film 3, a second gate oxide film 4, a metal gate 5, and a first diffusion layer 6. And a second diffusion layer 7.

As shown in FIG. 1A, the first gate oxide film 2, the nitride film 3, the second gate oxide film 4, and the gate 5 are sequentially formed in a predetermined region on the semiconductor substrate 1. Further, if the semiconductor substrate 1 is, for example, a p-type silicon substrate, the diffusion layers 6 and 7 are formed by introducing an n-type impurity into a predetermined region of the semiconductor substrate 1. (S), the second diffusion layer 7 becomes the drain (D).

In each of the embodiments described below, the MONOS element is illustrated using the symbols (circuit diagram notation) shown in FIG. 1B. In FIG. 1B, G is a gate, S is a source, and D is a drain.

The MONOS element can store at least one data in the structure shown in FIG. 1A, that is, one transistor size, and has a charge accumulation region 8 (a nitride trap, a first trap, a trapping center of a silicon nitride film). The data is stored by accumulating electric charges in the gate oxide film 2 and the nitride film 3 at the interface region. In charge storage area 8 Since the threshold value of the MONOS element changes according to the state of charge accumulation, the storage state (storage data) of the MONOS element can be determined by detecting a current flowing under a predetermined potential condition.

FIG. 1C is a diagram showing an example of a potential condition in each operation of the MONOS element, and shows potentials respectively applied to the gate G, the source S, and the drain D of the MONOS element.

In the data read operation, a positive potential V2 is applied to the gate G, and a positive potential V3 lower than the potential V2 is applied to the source S. At this time, the potential applied to the drain D is 0 V.

In the data write (program) operation, when writing "0", a positive high potential HV is applied to the gate G, and a positive potential V1 lower than the potential HV is applied to the drain D. At this time, the potential applied to the source S is 0 V. When the data to be written is "1", 0 V is applied to both source S and drain D. In the data erase operation, a negative potential NV is applied to the gate G, and a positive potential V4 is applied to the source S and the drain D.

The potentials applied to the gate G, the source S, and the drain D of the MONOS element are different depending on the operation as described above. The values of the potentials V1 to V4, HV, and NV are set to appropriate values according to the manufacturing conditions of the MONOS element and the like.

(First Embodiment)

FIG. 2 is a diagram showing a configuration example of a memory cell in the semiconductor memory device according to the first embodiment of the present invention. The memory cell shown in FIG. 2 has an arbitrary number in the direction in which the signal lines DSL 1 and DSL r extend. Connected to form a semiconductor memory device. '

In FIG. 2, reference numeral 10 denotes a latch circuit (flip-flop circuit), which includes four transistors (two P-channel MOS transistors PT 1 and PT 2 and two N-channel transistors NT 1 and NT 2). . Specifically, the latch circuit 10 is composed of a CMOS transistor composed of transistors PT1 and NT1, and a CMOS transistor composed of transistors PT2 and NT2, each of which constitutes an inverter. Are cross-coupled (cross-coupled) to form an SRAM-type volatile storage circuit. Power is supplied to the latch circuit 10 via a P-channel MOS transistor PT 3 and an N-channel MOS transistor NT 3. The transistor PT 3 has a source connected to the power supply voltage V ii, a drain connected to the latch circuit 10 (sources of the transistors PT 1 and PT 2), and a gate connected to the signal line LE n via the inverter circuit 11. Is done. The transistor NT3 has a source connected to ground (reference potential: ground GND), a drain connected to the latch circuit 10 (sources of the transistors NT1 and NT2), and a gate connected to the signal line LEn. You.

MT1 and MT2 are MONOS elements constituting a nonvolatile memory circuit. The source of the MO NO S element MT 1 is connected to the internal node N 1 (drain of the transistors PT 1 and NT 1) of the latch circuit 10, the drain is connected to the signal line SL n, and the gate is connected to the signal line DSL 1. Connected. Similarly, in the MONOS element MT2, the source is connected to the internal node N2 (the drain of the transistor PT2,) 2) of the latch circuit 10, the drain is connected to the signal line SLη, and the gate is connected to the signal line DSL. Connected to r. The MONOS elements MT1 and MT2 store data in a complementary relationship (the state is maintained).

In addition, a signal line (output data line) DATAn is connected to the internal node N2. In the signal lines LE n, S L n, and DATA n, n is a suffix and n is an arbitrary integer.

Next, the operation will be described.

The normal operation of latching (holding) data in the memory cell in the semiconductor memory device according to the first embodiment is a data read operation in the MONOS element. The MONOS elements MT1 and MT2 have data written in advance in a complementary relationship and hold the complementary state.

First, the potential of the signal line SL n is set to a low level (0 V, hereinafter referred to as “L”). At this time, the potentials of the signal lines DSL1, DSLr, and LEn are 0 V ("L"). The internal nodes Nl and N2 are charged to a positive potential V3 in advance by a circuit (not shown). (Floating) before the signal line SL n is set to “L”. Therefore, when the potential of the signal line S Ln is set to “L”, the potential of the signal line DAT An is V 3, and the potentials of the gate, source, and drain of the MONOS elements MT 1 and MT 2 are 0 V, respectively. , V3, 0V.

Next, at time T1, a pair of signal lines DSL1 and DSLr (hereinafter, also referred to as "DSL signal line pair") are simultaneously driven to a positive potential V2 higher than the potential V3. That is, the potential V2 is applied to the gates of the MONOS elements MT1 and MT2. Thus, depending on the storage state of the MONO S elements IvIT 1 and MT 2, one of the MONO S elements MT 1 and MT 2 flows in the seawater (turns on), and the other does not flow the current (off). State). Therefore, one of the internal nodes N 1 and N 2 (the node connected to the MONOS element through which current flows) decreases in potential, and the other node maintains the potential V 3. FIG. 3 shows a case where a current flows in the MONOS element MT1 as an example.

The latch circuit 10 is activated by setting the potential of the signal line LE n to a high level (power supply voltage V ii, hereinafter referred to as “H”) at a time T 2 after a predetermined time has elapsed from the time T 1. Is done. As a result, the potential difference between the internal nodes Nl and N2 is amplified, the potential becomes "H" or "L", and the potential of the signal line DATAn is determined to be "H" or "L".

At time T3, the potential of the signal line LEn is set to "L" to cut off the power supply to the latch circuit 10, and the internal nodes N1 and N2 are precharged to the potential V3 by a circuit (not shown). . Thereafter, the DSL signal line pair and the signal line SLn are deactivated, and the data read operation is completed.

In the above description, the potential of the signal line SL n is set to “L”, and then the potential of the DSL signal line pair is set to V 2, but almost simultaneously, the potential of the signal line SL n and the potential of the DSL signal line are set. The potential of the pair may be changed.

When the output state of the signal line DATAn is to be held, the potential of the signal line LEn may be held at "H" even after the DSL signal line pair and the signal line SLn are inactivated.

<Data write (program) operation> Next, a data programming operation for the MONOS element will be described.

FIG. 4 is a timing chart showing a data program operation in the semiconductor memory device according to the first embodiment.

First, the signal line SLn is driven to a positive potential V1. Next, in the DSL signal line pair, the signal line DSL 1 connected to one of the MONOS elements MT 1 and MT 2 to which "0" is written so that no current flows during data read operation (in a non-conducting state). , DSLr are driven from the potential V1 to 髙ぃ high potential HV. The other potentials of the signal lines DS L1 and DS Lr connected to the other MONO S elements MT 1 and MT 2 maintain 0 ヽ T.

As a result, electrons are accumulated only in the charge accumulation region 8 in one of the MONOS elements MT1 and MT2, and the MONOS elements MT1 and MT2 maintain a complementary state. Thereafter, the potential of the DSL signal line pair and the potential of the signal line SLn are set to 0 V, and the data programming operation is completed.

Note that during the data programming operation, by setting the potential of the signal line L En to “L”, a through current or the like does not occur. During the data programming operation, the potentials of the internal nodes Nl and N2 are maintained at 0 V by a circuit (not shown).

Data erase operation>

Next, the data erase operation of the MONOS element will be described.

FIG. 5 is a timing chart showing a data erase operation in the semiconductor memory device according to the first embodiment, and shows a case where the storage states of the MONOS elements MTl and MT2 are erased collectively. I have.

First, the signal line SLn is driven to a positive potential V4, and the potentials of the internal nodes Nl and N2 are set to the potential V4 by a circuit (not shown). Next, the DS Lm signal line pair is simultaneously driven to the negative potential NV. As a result, the electrons stored in the charge storage region 8 in the MONOS elements MT1 and MT2 are released, and the storage state is erased. Thereafter, the DSL signal line pair and the signal line SLn are deactivated, and the data erasing operation ends. Note that the potential of the signal line LEn is set to "L" when performing the data erase operation. As described above, according to the first embodiment, the sources of the MONOS elements MT1 and MT2, which are nonvolatile storage circuits, are connected to the internal nodes Nl and Nl of the SRAM type latch circuit 10. Connect to N2 to configure non-volatile storage circuit like SRAM. As a result, it is possible to realize a nonvolatile data retention function that retains data without losing data even when power is not supplied, with a high operation speed and a small storage unit size. In addition, by using MONOS elements MT1 and MT2 as the nonvolatile memory circuit, it is possible to fabricate a semiconductor memory device using only a CMOS process that adds several steps to a normal logic process without using special materials. it can.

For example, it can be widely used as a circuit having a register function of a semiconductor circuit, and can be used as a nonvolatile register circuit or a storage circuit of a look-up table (a truth table of logic of a programmable device). Further, for example, since it has a non-volatile data holding function, it can be applied to a programmable device that does not require an external non-volatile memory (EEPROM or the like) or an instant-on system.

(Second embodiment)

Next, a second embodiment will be described.

FIG. 6 is a diagram showing a configuration example of a memory cell in a semiconductor memory device according to a second embodiment of the present invention. The memory cells shown in FIG. A storage device is configured. 6, circuit components and the like having the same functions as the circuit components and the like shown in FIG. 2 are denoted by the same reference numerals, and redundant description will be omitted.

As shown in FIG. 6, the memory cell according to the second embodiment includes a latch circuit including two P-channel MOS transistors PT 4 and PT 5 instead of the latch circuit 10 according to the first embodiment. 20 is used. In the latch circuit 20, two transistors PT4 and PT5 are cross-coupled to form a volatile storage circuit. In the second embodiment, the sources of the MONOS elements MT1 and MT2 that constitute the nonvolatile memory circuit are the internal nodes N3 (the drain of the transistor PT4), N4 (the transistor PT4) of the latch circuit 20. 4 drain). The drain of the transistor NT3 is connected to the drains of the MONOS elements MT1 and MT2. Connected to

The data read, data write, and data erase operations for the MONOS element in the semiconductor memory device according to the second embodiment are the same as those in the first embodiment. In the data read operation in the second embodiment, when the potential of the signal line LEii is set to "H" to activate the latch circuit 20, the operation of the cross-coupled transistors PT4 and PT5 causes The potentials of the internal nodes N3 and N4 become "H" or "L", and the potential of the signal line DATAn becomes "H" or "L".

According to the second embodiment, the same effects as those of the above-described first embodiment can be obtained, and the circuit scale can be made smaller than that of the first embodiment. (Third embodiment)

Next, a third embodiment will be described.

The memory cell in the semiconductor memory device according to the first and second embodiments described above has a pair of MONOS elements MT 1 and MT 2 in which data is stored in a complementary relationship. Holds two data. The memory cell in the semiconductor memory device according to the third embodiment of the present invention described below is provided with a plurality of pairs of two MONOS elements in which data is stored in a complementary relationship, and a plurality of data are stored in one memory cell. Can be held.

FIG. 7 is a diagram showing a configuration example of a memory cell according to the third embodiment. An arbitrary number of the memory cells shown in FIG. 7 are connected in the direction in which the DSL signal line pair extends, to configure a semiconductor memory device. 7, circuit components and the like having the same functions as the circuit components and the like shown in FIG. 2 are denoted by the same reference numerals, and redundant description will be omitted.

The memory cell according to the third embodiment has a plurality of MONO S elements MT ij (i and j are suffixes, i = l or 2, j is an arbitrary natural number), and two MONO S elements MT 1 j and MT 2 j form a pair and store data in a complementary relationship. Therefore, the DSL signal line pair is also provided corresponding to each set of two MONOS elements MT1j and MT2j.

The MONOS element MT 1 j has a source connected to the internal node FN 1 of the latch circuit 10, a drain connected to the signal line SL n, and a gate connected to the signal line DS L 1 j. It is. Similarly, the MONOS element MT 2 j has a source connected to the internal node N 2 of the latch circuit 10, a drain connected to the signal line SL n, and a gate connected to the signal line DSL rj.

FIG. 8 is a diagram showing another configuration example of the memory cell according to the third embodiment. The semiconductor memory device is configured by connecting an arbitrary number of the memory cells shown in FIG. 8 in the direction in which the DSL signal line pairs extend. You. 8, circuit components and the like having the same functions as the circuit components and the like shown in FIGS. 2, 6, and 7 are denoted by the same reference numerals, and redundant description will be omitted.

The memory cell shown in FIG. 8 has the same configuration as the memory cell in the second embodiment, and is provided with a plurality of MONOS elements MT ij. The memory cell shown in FIG. 8 has a DSL signal line pair corresponding to each set of two M〇NOS elements MT 1 j and MT 2 j, similarly to the memory cell shown in FIG. Two MONO S elements MT 1 j and MT 2 j are paired and store data in a complementary relationship.

The sources of the MONO S elements MT 1 j and MT 2 i are connected to the internal nodes N 3 and N 4 of the latch circuit 20, and the drain of the transistor NT 3 is connected to the drain of the MONO S element MT i j.

Note that the data read, data write, and data erase operations for the MON OS element in the semiconductor memory device according to the third embodiment shown in FIGS. 7 and 8 are performed in the first and second embodiments described above. The operations are the same as those described above.

In the data read operation of the MONOS element according to the third embodiment, only one DSL signal line pair to which the MONOS elements M 1 j and M 2 j holding the data are connected is activated (positive Of the DSL signal line pair to the inactive state (potential 0 V). Thereby, one activated DSL signal line 'pair and the MONOS elements Ml j and M2 j connected thereto operate in the same manner as in the first and second embodiments. At this time, the MONOS element M ij connected to the inactive DSL signal line pair is in the off state regardless of the storage state, and thus does not affect the activated MONOS element M ij.

In the third embodiment, a plurality of MONOS elements M ij are connected as shown in FIGS. Therefore, in the data erase operation, the signal line SL n By setting the potentials of the internal nodes Nl and N2 (N3, N4) to V4 and simultaneously driving a plurality of DSL signal line pairs to a negative potential NV, the connection to the plurality of DSL signal line pairs is achieved. The stored state of the MONOS element M ij can be simultaneously erased. According to the third embodiment, an example of which is shown in FIGS. 7 and 8, the same effects as those of the first and second embodiments can be obtained. Furthermore, by holding a plurality of data (data patterns) in one memory cell and selecting an appropriate DSL signal line pair to be activated, desired data is selected from the plurality of data and a signal is selected. It is possible to easily realize a so-called multi-context function in which data output via the line DAT An can be changed. In this way, data can be easily changed even during operation, so performance can be improved by applying multi-context using on-chip memory in a programmable device, for example. .

(Fourth embodiment)

Next, a fourth embodiment will be described.

FIG. 9 is a diagram showing a configuration example of a memory cell in the semiconductor memory device according to the fourth embodiment of the present invention. In FIG. 9, circuit components and the like having the same functions as the circuit components and the like shown in FIG. 2 are given the same reference numerals, and overlapping descriptions will be omitted. The memory cell according to the fourth embodiment shown in FIG. 9 is different from the memory cell shown in FIG. 2 in that an N-channel MOS transistor NT4 is newly provided as an output control gate and is connected to an internal node N2 via a transistor NT4. Signal line DAT An is connected. That is, the transistor NT4 has a source connected to the internal node N2 of the latch circuit 1 ◦, a drain connected to the signal line DATAn, and a gate connected to the signal line (output control signal line) CLn.

The signal line CLn controls the transistor NT4 by turning on and off a predetermined timing signal such as a close signal of an external circuit that receives the potential of the signal line DATAn as data. It is for supply. Note that the predetermined timing signal is not limited to a clock signal, but may be an arbitrary synchronous signal or an asynchronous signal.

FIG. 10 shows a data read operation in the semiconductor memory device according to the fourth embodiment. This is a timing chart. The operation up to time T12 is the same as the operation up to time T2 in the above-described first embodiment. At time T13 after a predetermined time has elapsed from time T12, the transistor NT4 is turned on by setting the potential of the signal line CLn to "H", and the potential of the internal node N2 is changed to the signal line. It is transmitted to DAT An. Thereafter, the potential of the signal line CL n is set to, and the transistor NT4 is turned off, so that the signal line DAT An becomes a floating state. The operation after time T14 is the same as the operation after time T3 in the above-described first embodiment. As described above, when reading the data latched in the memory cell in the fourth embodiment, the output timing of the data latched in the memory cell can be controlled by the potential of the signal line CLn. For example, by supplying a clock signal of an external circuit or the like to the gate of the transistor NT4 through the signal line CLn, data latched in the memory cell can be output in synchronization with the clock signal. Further, for example, it is possible to control whether to output data latched in the memory cell by the signal line DATAn.

FIG. 11 is a diagram illustrating another configuration example of the memory cell according to the fourth embodiment. In the memory cell shown in FIG. 11, the wiring connecting the source of the MON OS element MT2 and the internal node N2 is different from the wiring connecting the source of the transistor NT4 and the internal node N2 'of the latch circuit 10. The only difference from the memory cell shown in FIG. Note that the internal nodes N 2 and N 2 ′ are electrically connected.

In this manner, by using different wiring for connecting the source of the MONOS element MT2 and the source of the transistor NT4 to the internal node of the latch circuit 10, the load such as the parasitic capacitance of the M〇NOS element can be avoided. The data latched in the memory cell by the signal line DAT An can be output. Therefore, it is possible to reduce a wiring delay when outputting data latched in a memory cell by the signal line DATAn.

FIGS. 12 to 16 are diagrams C ′ to showing another configuration example of the memory cell in the fourth embodiment.

FIGS. 12, 13, and 15 illustrate the memory cells shown in FIGS. 6, 7, and 8. In the same manner as the memory cell shown in FIG. 9, a transistor NT4 is provided as an output control gate. FIGS. 14 and 16 show a transistor NT4 as an output control gate in the memory cell shown in FIGS. 7 and 8 in the same manner as the memory cell shown in FIG. The source and the source of the transistor NT4 are connected to the internal node of the latch circuit by different wiring. The configuration and operation of the memory cell shown in FIGS. 12 to 16 are the same as those of the memory cell in each of the above-described embodiments except that the transistor NT4 as an output control gate and the operation related thereto are different.ぴ Operation is the same.

According to the fourth embodiment, in addition to the effects obtained in the above embodiments, an N-channel MOS transistor NT 4 is newly provided as an output control gate, and the internal node of the latch circuit is connected via the transistor NT 4. The data output timing can be controlled by connecting the signal line DAT An to the power supply. For example, if the signal line DAT An is long, connecting the signal line DAT An to the internal node without providing the transistor NT 4 will increase the load on one circuit when the latch circuit is activated. However, by providing the transistor NT4, an increase in the load due to the signal line DAT An can be suppressed, and the latch circuit can operate stably. Also, by connecting the source of the transistor NT4 and the internal node of the latch circuit with a different wiring from the wiring connecting the source of the MONOS element and the internal node of the latch circuit, data is output via the signal line DATAn. In this case, wiring delay due to the parasitic capacitance of the MONOS element can be reduced. In particular, a greater effect can be obtained when a plurality of sets of MONOS elements are provided.

In the fourth embodiment, by providing a flip-flop circuit or the like at the output of the signal line DATAn, the determined data can be maintained even when the transistor NT4 is in the off state. It is possible to reduce the influence of noise and the like.

Here, in the memory cells shown in FIG. 7, FIG. 8, and FIG. 13 to FIG. 16 described above, by activating a desired DSL signal line pair, the data output by the signal line DAT An is changed. If a plurality of these are arranged to form a data pattern, it is possible to selectively output a plurality of data patterns. In addition, in the activated state The timing of changing the DSL signal line pair may be at the time of startup immediately after power-on or at any time during operation.

In the first to fourth embodiments described above, two MONOS elements connected to different internal nodes are stored as a set and data is stored in a complementary relationship. It may be possible to memorize in one MONO S Hatako instead of the relationship. In this case, the MONOS element is selectively driven by one DSL signal line, instead of selectively driving the MONOS element by the DSL signal line pair. .

Also, the difference in the manufacturing method of the MONOS element and the so-called 2-bit / cell that stores two data in one MONOS element by localizing and accumulating charge in the charge accumulation region 8 of the nitride film 3 It is also conceivable to use the MONOS element. In this case, data reading, writing, and erasing characteristics in the MONOS element, potential conditions to be applied, and the like may be different, but may be appropriately set according to the MONOS element.

In the first to fourth embodiments described above, the MONOS element is used as the nonvolatile memory circuit. However, the MONOS element is not limited to the MONOS element.

Semiconductor-Oxide-Nitride-Oxide-Silicon) type storage elements and MNO S (Metal-Nitride-Oxide-Silicon) type storage elements may be used. Here, in the SONOS type storage element, a first gate oxide film, a nitride film, a second gate oxide film, and a gate made of a semiconductor are sequentially stacked in a predetermined region on a semiconductor substrate, and a lower region of the gut is sandwiched therebetween. Thus, a diffusion layer is formed in a surface region in a semiconductor substrate. In the MNOS type memory device, a gate made of a gate oxide film, a nitride film, and a metal is sequentially stacked in a predetermined region on the semiconductor substrate, and a diffusion layer is formed in a surface region in the semiconductor substrate so as to sandwich the gate lower region. Is formed.

Further, all of the above embodiments are merely examples of the embodiment of the present invention, and the technical scope of the present invention should not be interpreted in a limited manner. It is. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof. Industrial applicability

As described above, according to the present invention, an output node of a non-volatile semiconductor storage circuit that stores electric charge in a trap region in a nitride film to maintain a storage state, and a volatile that latches an output of the non-volatile semiconductor storage circuit By using a circuit configuration that connects the internal nodes of the volatile memory circuit, data is held by a nonvolatile semiconductor memory circuit of one transistor size, and the data held by the volatile memory circuit is signaled in a short time. Can be output. As a result, a nonvolatile data holding function can be realized, and a circuit scale required for storing one data can be reduced. For example, as a non-volatile semiconductor memory device, the present invention can be applied to a programmable logic device which does not require an external non-volatile memory, an instant-on system, and the like.

In the case where an output signal can be changed by providing a plurality of nonvolatile semiconductor memory circuits and selectively driving the same, desired data can be arbitrarily selected from a plurality of data and output. it can.

Claims

The scope of the claims

1. A non-volatile semiconductor storage circuit that stores a charge by accumulating charges in a trap region in a nitride film,

A semiconductor memory device having an internal node connected to an output node of the nonvolatile semiconductor memory circuit and a volatile memory circuit for latching an output of the nonvolatile semiconductor memory circuit.

2. The non-volatile semiconductor memory circuit is formed on a first gate oxide film formed on a semiconductor substrate, a nitride film formed on the first gate oxide film, and formed on the nitride film. A second gate oxide film, a gate made of a metal formed on the second gate oxide film, and a pair of sources and a pair formed in a surface region in the semiconductor substrate so as to sandwich the gut lower region. 2. The semiconductor memory device according to claim 1, further comprising a drain.

3. The nonvolatile semiconductor memory circuit is formed on a first gate oxide film formed on a semiconductor substrate, a nitride film formed on the first gate oxide film, and formed on the nitride film. A second gate oxide film; a gate made of a semiconductor formed on the second gate oxide film; and a pair of sources and a pair formed in a surface region in the semiconductor substrate so as to sandwich the gate lower region. 2. The semiconductor memory device according to claim 1, comprising a drain.

4. The nonvolatile semiconductor memory circuit includes a gate oxide film formed on a semiconductor substrate, a nitride film formed on the gate oxide film, and a gate made of a metal formed on the nitride film. 2. The semiconductor memory device according to claim 1, further comprising a pair of a source and a drain formed in a surface region in the semiconductor substrate so as to sandwich the gut lower region.

5. The volatile storage circuit has two internal nodes and the two nonvolatile semiconductors. The output node of one of the nonvolatile semiconductor memory circuits in the set of body memory circuits is connected to one internal node, and the output node of the other nonvolatile semiconductor memory circuit is connected to the other internal node. 2. The semiconductor memory device according to claim 1, wherein:

6. The semiconductor memory device according to claim 5, wherein the two non-volatile semiconductor memory circuits maintain a storage state in a relation of cancellation.

7. The semiconductor memory device according to claim 6, wherein the two nonvolatile semiconductor memory circuits are selected by signals that can be simultaneously driven and independently driven.

8. The semiconductor memory device according to claim 1, further comprising an output control circuit between a partial node of the volatile memory circuit and an output terminal of the semiconductor memory device.

9. The semiconductor memory device according to claim 8, wherein the output control circuit is controlled by a timing signal.

10. The semiconductor memory device according to claim 1, wherein the volatile memory circuit has two cross-coupled CMOS transistors.

11. The volatile storage circuit is characterized in that the output node of the non-volatile semiconductor storage circuit is connected to a drain and has two P-channel transistors whose gate and drain are cross-coupled. 2. The semiconductor memory device according to claim 1,

12. The semiconductor memory device according to claim 10, wherein the volatile memory circuit is activated in response to a control signal.

1 3. A plurality of the nonvolatile semiconductor memory circuits are provided, and the plurality of nonvolatile semiconductor memory circuits are provided. 2. The semiconductor memory device according to claim 1, wherein a signal output can be changed by selectively driving a circuit.

14. The semiconductor memory device according to claim 13, wherein the output signal is changed at startup immediately after power-on.

15. The semiconductor memory device according to claim 13, wherein the change of the output signal is performed at an arbitrary time.

1 6. A first P-channel transistor having a source connectable to the power supply potential, a drain connected to the first internal node, and a gate connected to the second internal node;

A first N-channel transistor having a source connectable to a reference potential, a drain connected to the first internal node, and a good connected to the second internal node;

A second P-channel transistor having a source connectable to the power supply potential, a drain connected to the second internal node, and a gate connected to the first internal node;

A second N-channel transistor having a source connectable to the reference potential, a drain connected to the second internal node, and a gate connected to the first internal node;

The source is connected to the internal node, the gate is connected to the first signal line, and the drain is connected to the second signal line. A semiconductor storage device comprising: a nonvolatile semiconductor storage element.

17. A third N-channel transistor having a source connected to the internal node, a drain connected to the output terminal, and a gate connected to an output control signal line. 16. The semiconductor memory device according to item 16.

1 8. A first P-channel transistor having a source connectable to the power supply potential, a drain connected to the first internal node, and a gate connected to the second internal node;

19. The semiconductor device further comprising a first N-channel transistor having a source connected to the internal node, a drain connected to the output terminal, and a gate connected to the output control signal line. 18. The semiconductor memory device according to item 18.