WO2004084303A3 - Dispositif a puce a bosses sur support de substrat - Google Patents

Dispositif a puce a bosses sur support de substrat Download PDF

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Publication number
WO2004084303A3
WO2004084303A3 PCT/DE2004/000504 DE2004000504W WO2004084303A3 WO 2004084303 A3 WO2004084303 A3 WO 2004084303A3 DE 2004000504 W DE2004000504 W DE 2004000504W WO 2004084303 A3 WO2004084303 A3 WO 2004084303A3
Authority
WO
WIPO (PCT)
Prior art keywords
chip
substrate carrier
contact elements
arrangment
flip
Prior art date
Application number
PCT/DE2004/000504
Other languages
German (de)
English (en)
Other versions
WO2004084303A2 (fr
Inventor
Erik Heinemann
Frank Pueschner
Original Assignee
Infineon Technologies Ag
Erik Heinemann
Frank Pueschner
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Erik Heinemann, Frank Pueschner filed Critical Infineon Technologies Ag
Publication of WO2004084303A2 publication Critical patent/WO2004084303A2/fr
Publication of WO2004084303A3 publication Critical patent/WO2004084303A3/fr

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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745—Mounting details of integrated circuit chips
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
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    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
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    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Theoretical Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Credit Cards Or The Like (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

L'invention concerne un dispositif comprenant un support de substrat (S) présentant une première surface (01) sur laquelle sont disposés des éléments de contact extérieur (AK), une seconde surface opposée (02) sur laquelle sont disposés des éléments de contact à puce (CK), les éléments de contact des deux surfaces étant connectés électriquement entre eux (D) à travers le substrat (S), une puce (IC), dont la partie (K) munie de points de contact (B) est tournée vers la seconde surface, et qui est connectée électriquement avec les éléments de contact à puce (CK), l'épaisseur (D2) de la puce étant supérieure à l'épaisseur du substrat (S). Les points de contact (B) de la puce (IC) sont formés en un métal présentant une dureté différente des éléments de contact à puce (CK).
PCT/DE2004/000504 2003-03-18 2004-03-12 Dispositif a puce a bosses sur support de substrat WO2004084303A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10311965A DE10311965A1 (de) 2003-03-18 2003-03-18 Flip-Chip Anordnung auf einem Substratträger
DE10311965.5 2003-03-18

Publications (2)

Publication Number Publication Date
WO2004084303A2 WO2004084303A2 (fr) 2004-09-30
WO2004084303A3 true WO2004084303A3 (fr) 2004-12-23

Family

ID=32980617

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2004/000504 WO2004084303A2 (fr) 2003-03-18 2004-03-12 Dispositif a puce a bosses sur support de substrat

Country Status (2)

Country Link
DE (1) DE10311965A1 (fr)
WO (1) WO2004084303A2 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6346192B2 (ja) * 2013-10-22 2018-06-20 凸版印刷株式会社 Ｉｃモジュール及びｉｃカード、ｉｃモジュール基板

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0682369A1 (fr) * 1994-04-28 1995-11-15 Kabushiki Kaisha Toshiba Ensemble à semi-conducteur
FR2736452A1 (fr) * 1995-07-05 1997-01-10 Solaic Sa Procede de fabrication d'une carte intelligente comprenant un corps en matiere fibreuse, et carte intelligente ainsi obtenue
US5740606A (en) * 1995-11-03 1998-04-21 Schlumberger Industries Method of manufacturing a set of electronic modules for electronic memory cards
EP0905657A1 (fr) * 1997-09-23 1999-03-31 STMicroelectronics S.r.l. Billet de banque comportant un circuit integré
EP0930651A1 (fr) * 1998-01-13 1999-07-21 SCHLUMBERGER Systèmes Procédé de connexion de plots d'un composant à circuits intégrés à des plages de connexion d'un substrat plastique au moyen de protubérances

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0863567A (ja) * 1994-08-19 1996-03-08 Citizen Watch Co Ltd Ｉｃカード用モジュール
EP1256982A1 (fr) * 2001-05-11 2002-11-13 Valtronic S.A. Module électronique et son procede d'assemblage
DE10139395A1 (de) * 2001-08-10 2003-03-06 Infineon Technologies Ag Kontaktierung von Halbleiterchips in Chipkarten
DE10145752B4 (de) * 2001-09-17 2004-09-02 Infineon Technologies Ag Nicht-leitendes, ein Band oder einen Nutzen bildendes Substrat, auf dem eine Vielzahl von Trägerelementen ausgebildet ist

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0682369A1 (fr) * 1994-04-28 1995-11-15 Kabushiki Kaisha Toshiba Ensemble à semi-conducteur
FR2736452A1 (fr) * 1995-07-05 1997-01-10 Solaic Sa Procede de fabrication d'une carte intelligente comprenant un corps en matiere fibreuse, et carte intelligente ainsi obtenue
US5740606A (en) * 1995-11-03 1998-04-21 Schlumberger Industries Method of manufacturing a set of electronic modules for electronic memory cards
EP0905657A1 (fr) * 1997-09-23 1999-03-31 STMicroelectronics S.r.l. Billet de banque comportant un circuit integré
EP0930651A1 (fr) * 1998-01-13 1999-07-21 SCHLUMBERGER Systèmes Procédé de connexion de plots d'un composant à circuits intégrés à des plages de connexion d'un substrat plastique au moyen de protubérances

Also Published As

Publication number Publication date
DE10311965A1 (de) 2004-10-14
WO2004084303A2 (fr) 2004-09-30

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