WO2004084064A2 - Unite de conversion de type dans un systeme multiprocesseur - Google Patents

Unite de conversion de type dans un systeme multiprocesseur Download PDF

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Publication number
WO2004084064A2
WO2004084064A2 PCT/IB2004/050268 IB2004050268W WO2004084064A2 WO 2004084064 A2 WO2004084064 A2 WO 2004084064A2 IB 2004050268 W IB2004050268 W IB 2004050268W WO 2004084064 A2 WO2004084064 A2 WO 2004084064A2
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WO
WIPO (PCT)
Prior art keywords
register file
data
processor
conversion
conversion unit
Prior art date
Application number
PCT/IB2004/050268
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English (en)
Other versions
WO2004084064A3 (fr
Inventor
Marco J. G. Bekooij
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Koninklijke Philips Electronics N.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics N.V. filed Critical Koninklijke Philips Electronics N.V.
Priority to EP04721266A priority Critical patent/EP1606705A2/fr
Priority to JP2006506722A priority patent/JP2006520957A/ja
Priority to US10/549,215 priority patent/US20060179285A1/en
Publication of WO2004084064A2 publication Critical patent/WO2004084064A2/fr
Publication of WO2004084064A3 publication Critical patent/WO2004084064A3/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30025—Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing

Definitions

  • the invention relates to a processor comprising a plurality of execution units, a register file accessible by the execution units and a communication network for coupling the execution units and the register file.
  • a widely used concept to achieve high performance is the introduction of instruction level parallelism, in which a number of execution units are present in the processor architecture for executing a number of instructions more or less at the same time.
  • instruction level parallelism in which a number of execution units are present in the processor architecture for executing a number of instructions more or less at the same time.
  • Two main concepts have been adopted: the multithreading concept, in which several threads of a program are accessible by the execution units, and the very large instruction word (VLIW) concept, in which bundles of instructions corresponding with the functionality of the execution units are present in the instruction set.
  • VLIW very large instruction word
  • VLIW Very Large Instruction Word
  • a VLIW processor uses multiple, independent execution units to execute these multiple instructions in parallel.
  • the processor allows exploiting instruction-level parallelism in programs and thus executing more than one instruction at a time.
  • the compiler attempts to minimize the time needed to execute the program by optimizing parallelism.
  • the compiler combines instructions into a VLIW instruction under the constraint that the instructions assigned to a single VLIW instruction can be executed in parallel and under data dependency constraints.
  • Encoding of instructions can be done in two different ways, for a data stationary VLIW processor or for a time stationary VLIW processor, respectively.
  • a data stationary VLIW processor all information related to a given pipeline of operations to be performed on a given data item is encoded in a single VLIW instruction.
  • time stationary VLIW processors the information related to a pipeline of operations to be performed on a given data item is spread over multiple instructions in different VLIW instructions, thereby exposing said pipeline of the processor in the program.
  • multiple data-types can be used.
  • programs using C as the programming language a data type is often implicitly converted or explicitly casted to another data-type.
  • the actual type conversion may then be perfo ⁇ ned in the network of the VLIW processor, or at the output of an execution unit.
  • the network of the VLIW processor or the execution unit may not provide the required type conversion hardware for all data type conversions. Therefore, it may turn out that a certain data type conversion can not be performed for some applications to be run on such a VLIW processor.
  • US 6,460,135 describes a microprocessor comprising an input/output execution unit, a calculation execution unit, a plurality of data registers, an instruction controller and an interconnect structure.
  • the instruction controller decodes the instruction word and sends the operation code to the input/output execution unit or the calculation execution unit.
  • Type information registers are associated with the data registers and an information register holds the type information indicating the data type and the effective bit width of the data stored in the corresponding data register.
  • the instruction word designates the type information of the execution result, i.e. the data type and the effective bit width, independently of the type information of the data used for the calculation.
  • the calculation execution unit compares the type information of the two operands, and in case a disagreement exists, an interrupt is generated and subsequently data is converted to the correct type and this conversion is done in software.
  • the input/output execution unit has to execute an input/output instruction, it compares the type information stored in the type information register with that of the instruction word. In case of disagreement, an interrupt is generated as well and subsequently the data is also converted to the correct type and this conversion is done in software.
  • the processor further comprises a conversion device for converting the type of data when transferring said data between an execution unit of the plurality of execution units and the register file.
  • the type conversion can be performed by the conversion device.
  • An embodiment of the invention is characterized in that the register file is a distributed register file, and that the communication network is a partially connected communication network for coupling the execution units and selected parts of the distributed register file.
  • An advantage of a distributed register file is that it requires less read and write ports per register file segment, resulting in a smaller register file bandwidth. Furthermore, the addressing of a register in a distributed register file requires less bits when compared to a central register file.
  • a partially connected communication network is less expensive in terms of code size and power consumption, when compared to a fully connected communication network, especially in case of a large number of execution units.
  • An embodiment of the invention is characterized in that the conversion device comprises a conversion register file and a conversion unit, the conversion register file being accessible by the conversion unit.
  • the conversion unit can read the data from the conversion register file, convert the data into the required type, and write the results to the appropriate register, for each request.
  • An embodiment of the invention is characterized in that the processor further comprises a communication device for coupling the execution units, the conversion unit, the distributed register file, and the conversion register file.
  • the processor further comprises a communication device for coupling the execution units, the conversion unit, the distributed register file, and the conversion register file.
  • a communication device for coupling the execution units, the conversion unit, the distributed register file, and the conversion register file.
  • An embodiment of the invention is characterized in that the communication device supports all data types of a programming language.
  • An advantage of this embodiment is that all data can be transferred to the conversion device for data type conversion, independent of its type and without requiring any intermediate conversion by the communication network or the communication device itself.
  • An embodiment of the invention is characterized in that the communication device couples all execution units, the conversion unit, all parts of the distributed register file, and the conversion register file.
  • An advantage of this embodiment is that all execution units can transfer data to the conversion register file via the communication device, and that the conversion unit can always transfer data to all register file segments via the communication device.
  • An embodiment of the invention is characterized in that the conversion unit is part of one of the execution units of the plurality of execution units.
  • An advantage of this embodiment is that no separate conversion unit is required, saving additional silicon area as well as communication connections.
  • Figure 1 shows a processor, comprising a plurality of execution units, according to the invention.
  • a schematic block diagram illustrates a VLIW processor, comprising a plurality of execution units 101, 103 and 105, and a distributed register file, including the register file segments 109, 111, 113.
  • the processor also has a conversion device 135.
  • Conversion device 135 comprises conversion register file 115 and type conversion unit 107.
  • Register file segment 109 is accessible by execution units 101 and 103
  • register file segments 111 and 113 are accessible by execution unit 105
  • conversion register file 115 is accessible by type conversion unit 107.
  • the processor also has a partially connected network 117 for coupling the execution units 101, 103 and 105, and selections of distributed register file segments 109, 111, 113 and conversion register file 115.
  • the partially connected network 117 also couples conversion device 135 with selected distributed register file segments 109, 111 and 113.
  • the partially connected network 117 comprises the multiplexers 119, 121, 123, 125 and 127.
  • the processor handles a specific range of applications, and the partially connected network 117 is designed for this purpose, i.e. during design of the processor a connection from an execution unit to a distributed register file segment is made via the partially connected network, if that execution unit has to write values into that register file segment during execution of an application within that range.
  • execution unit 101 produces an output in the form of an unsigned fixed point number, comprising 16 bits from which 15 bits are positioned behind the decimal point, that has to be written to register file segment 111, via the partially connected network 117.
  • Execution unit 105 will use this data output as input for an operation, but this input is required to be an unsigned fixed number, comprising 32 bits from which 31 bits are positioned behind the decimal point. Therefore, the type of the data will have to be converted.
  • the partially connected network supports this data type conversion, and the unsigned fixed point number comprising 16 bits is implicitly converted by the multiplexer 123 to an unsigned fixed point number comprising 32 bits.
  • execution unit 103 When executing an application that is outside the range for which the processor is originally designed, it may turn out that a required data type conversion can not be performed implicitly by the processor.
  • execution unit 103 produces a data output in the form of an unsigned fixed point number, comprising 16 bits, that should be written to register file segment 113, via the partially comiected network 117.
  • Execution unit 105 requires these data as input data for an operation, as floating point number comprising 32 bits.
  • multiplexer 125 is not capable of converting the type of the data from an unsigned fixed point number to a floating point number. In this case, execution unit 103 writes the data to conversion register file 115, via the partially connected network 117.
  • Type conversion unit 107 reads the data from register file segment 115, and this unit converts the type of the data from unsigned fixed point number to floating point number, by executing a dedicated instruction. Subsequently, type conversion unit 107 writes the data in the form of a floating point number to register file segment 113, via the partially connected network 117. Now the data are available in the correct data type for execution unit 105.
  • execution unit 105 produces output data in the form of an unsigned fixed point number comprising 32 bits, and these data have to be written twice to register file segment 109, via the partially connected network 117, once as an unsigned fixed point number comprising 16 bits and once as a floating point number comprising 32 bits.
  • Execution unit 105 writes its output data to conversion register file 115, via the partially connected network 117.
  • Execution unit 107 reads the data from conversion register file 115, converts the data from an unsigned fixed point number comprising 32 bits to an unsigned fixed point number comprising 16 bits, and writes the converted data to register file segment 109, via the partially connected network 117.
  • execution unit 115 reads the data again from conversion register file 115, converts the data from an unsigned fixed point number comprising 32 bits to a floating point number comprising 32 bits, and writes the converted data to register file segment 109, via the partially connected network 117. Subsequently, these data can be read by execution units 101 and 103 from register file segment 109, and used for further processing.
  • writing data from the execution units 101, 103 and 105 to the conversion register file 115 or writing data from the type conversion unit 107 to register file segments 109, 111 and 113 may require more than one step.
  • execution unit 101 produces output data of type floating point number, and this data has to written to register file segment 111 as an unsigned fixed point number, to be used as input data for an operation to be performed by execution unit 105.
  • the partially connected network does not support this type conversion.
  • the type conversion can be performed by type conversion unit 107, but execution unit 101 can not write directly its output data to register file segment 115, via the partially connected network 117, but only via an alternative route.
  • a possible alternative route is that execution unit 101 writes its output data to register file segment 111, via the partially connected network 117, without implicit data type conversion.
  • Execution unit 105 reads the output data from register file segment 111, and write these output data to register file segment 115, via the partially connected network 117.
  • type conversion unit 107 reads the output data from register file segment 115 and performs the required data type conversion.
  • Type conversion unit 107 is not capable of writing the data directly to register file segment 111, via the partially connected network 117, but only via an alternative route.
  • a possibility is that type conversion unit 107 writes the data to register file segment 109, via the partially connected network 117.
  • the data are read from the register file segment 109 by execution unit 101, who writes the data to register file segment 111, via the partially connected network 117.
  • execution unit 101 who writes the data to register file segment 111, via the partially connected network 117.
  • the compiler detects that data cannot be written directly by an execution unit to the conversion register file, or by the type conversion unit directly to a register file segment, it will determine an alternative route and inserts the required additional instructions in the program.
  • the type conversion unit 107 can perform this type conversion and write the converted data to the proper register file segment via the partially connected network.
  • the processor can still efficiently execute applications outside the range for which the processor was originally designed, increasing the flexibility of the processor.
  • the compiler will detect that a required data type conversion can not be performed implicitly by the network, and introduces additional instructions in the program for sending the data to the type conversion unit 107, via the partially connected network 117, converting the data to the required data type by the type conversion unit 107, and sending the converted data to the required register file segment, via the partially connected network 117.
  • the explicit type conversion performed by the type conversion unit 107 can be implemented by means of one or more operations, as known by the person skilled in the art. For example, when only using unsigned fixed point types, a shift left operation, a shift right operation and an AND operation will suffice. In case of signed fixed point types it should be possible to add bits as most significant bits in case of a shift right operation, in order to prevent a change of the sign bit.
  • the communication network 117 may be a fully connected communication network, i.e. all execution units 101, 103 an 105, and type conversion unit 107 are coupled to all distributed register file segments 109, 111 and 113, and the conversion register file 115. In case of a relatively small number of execution units, the overhead of a fully connected communication network will be relatively small.
  • the processor also comprises a communication device 129 for coupling the functional units 101, 103 and 105, type conversion unit 107, and all distributed register file segments 109, 111 and 113, and conversion register file 115.
  • the communication device 129 shares multiplexers 119, 121, 123, 125 and 127 with the partially connected network 117.
  • the communication device support all data types for the programming language in which the application to be executed is written.
  • the partially connected network 117 can not implicitly perfo ⁇ n a required type conversion.
  • an alternative route for writing the data to conversion register file 115 of type conversion unit 107, or writing the data from type conversion unit 107 to register file segments 109, 111 and 113 may require many steps or even does not exist.
  • the communication device 129 allows transferring values between the execution units 101, 103 and 105, the type conversion unit 107, the distributed register file segments 109, 111 and 113, and the conversion register file 115, in case this is not possible via the partially connected network 117.
  • execution unit 101 is not directly coupled to register file segment 115 via the partially connected network 117, but a direct coupling only exists via communication device 129. If possible, however, direct communication between the execution units, type conversion unit and register files via the partially connected network 117 is preferred.
  • execution unit 101 produces result data as an unsigned fixed point number comprising 32 bits, and these data have to be written to register file segment 111, for subsequent use by execution unit 105, which requires data as floating point number as input data.
  • Execution unit 101 can not write the data directly to register file segment 111 via the partially connected network 117 since it does not support this type of data conversion.
  • Execution unit 101 can also not write the output data directly to register file segment 115 via the partially connected network 117, as this connection does not exist.
  • type conversion unit 107 can also not write data directly to register file segment 111 via the partially connected network 117, since this connection also does not exist.
  • the compiler detects these problems during program compilation, decides to transfer data via the communication device 129, and inserts the appropriate instructions for performing these data transfers in the program.
  • the execution unit 101 writes the output data to register file segment 115, via communication device 129.
  • the type conversion unit 107 reads the data from conversion register file 115 and converts the type of the data to a floating point number.
  • type conversion unit 107 writes the data to register file segment 111, via communication device 129.
  • data may be written from execution units 101, 103 and 105 to conversion register file 115 via the partially connected network 117, and subsequently from type conversion unit 107 to register file segments 109, 111 and 113 via communication device 129.
  • data may be written from execution units 101, 103 and 105 to conversion register file 115 via communication device 129, and subsequently from type conversion unit 107 to register file segments 109, 111 and 113 via the partially connected network 117.
  • the communication device 129 is arranged for communication with a first latency
  • the partially connected communication network 117 is arranged for communication with a second latency, the first latency exceeding the second latency.
  • the communication via the communication device 129 may be slow down by its control logic, especially in case of a large number of execution units. Dividing the communication via the communication device into several sequential steps, each of which takes place in one clock cycle, keeps the latency of one communication step low. This prevents the communication via the communication device to limit the clock frequency of the processor.
  • the total latency of the communication via the communication device being the sum of the latencies of all separate steps, will be higher than the latency of the communication via the partially connected communication network.
  • the higher latency of the communication via the communication device 129 will hardly affect the overall performance of the processor, since the majority of the communication will take place via the partially connected communication network 117.
  • the communication device 129 comprises a multiplexer 131 and a global bus 133, the multiplexer being arranged for coupling the functional units 101, 103 and 105, type conversion unit 107, and the global bus 133, the global bus 133 being arranged for coupling the multiplexer 131 and all distributed register file segments 109, 111 and 113, and conversion register file 115.
  • the global bus 133 differs from the partially connected communication network 117 in that multiple functional units 101, 103 and 105, and type conversion unit 107 are coupled to the global bus 133 and these functional units and type conversion unit time-multiplex the global bus, whereas the partially connected communication network 117 couples one execution unit or the conversion unit to a register file segment or the conversion register file.
  • the execution units or type conversion unit can be coupled to one register file segment, as in case of type conversion unit 107, or to multiple register file segments, as in case of execution unit 105, or multiple functional units may be coupled to one register file segment, as in case of the functional units 101 and 103.
  • the register file segments can be coupled to one execution unit, as in case of conversion register file 115, or to multiple execution units, as in case of register file segment 109.
  • the degree of coupling between the register file segments and the execution units can depend on the type of operations that the execution unit has to perform.
  • the partially connected network 117 and the communication device 129 share some resources, such as the multiplexers 119, 121, 123, 125 and 127. In other embodiments even more resources may be shared, or no resources are shared.
  • the type conversion unit 107 may be part of one of the execution units 101, 103 and 105, and the register file segment 115 being part of the corresponding register file segment of that execution unit.
  • a superscalar processor also comprises multiple issue slots that can perform multiple operations in parallel, as in case of a VLIW processor.
  • the processor hardware itself determines at runtime which operation dependencies exist and decides which operations to execute in parallel based on these dependencies, while ensuring that no resource conflicts will occur.
  • the principles of the embodiments for a VLIW processor, described in this section, also apply for a superscalar processor.
  • a VLIW processor may have more execution units in comparison to a superscalar processor.
  • the hardware of a VLIW processor is less complicated in comparison to a superscalar processor, which results in a better scalable architecture. The number of execution units and the complexity of each execution unit, among other things, will determine the amount of benefit that can be reached using the present invention.

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Devices For Executing Special Programs (AREA)
  • Multi Processors (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

Processeur à très long mot instruction (VLIW) comportant plusieurs unités d'exécution (101, 103, 105), un fichier registre (109, 111, 113) et un réseau de communication (117) permettant de raccorder les unités d'exécution et le fichier registre. Dans le cas d'un processeur VLIW propre à une application, c'est-à-dire un processeur VLIW conçu pour prendre en charge une gamme d'applications très spécifique, il se peut que le réseau de communication du processeur VLIW ne soit pas en mesure d'assurer tous les types de conversion de données. Par conséquent, il peut s'avérer qu'un type précis de conversion de données est impossible pour certaines applications à exécuter sur un tel processeur VLIW. L'incorporation dans l'architecture du processeur VLIW d'une unité de conversion de type (107) permet de garantir la possibilité d'exécuter toute conversion de type de données. Dans le cas d'un réseau de communication (117) partiellement connecté, un dispositif de communication (129) peut également être intégré à l'architecture pour permettre à toutes les unités d'exécution de transférer une valeur à l'unité de conversion de type, et permettre à l'unité de conversion de type de transférer une valeur à n'importe quel segment du fichier registre distribué.
PCT/IB2004/050268 2003-03-19 2004-03-17 Unite de conversion de type dans un systeme multiprocesseur WO2004084064A2 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP04721266A EP1606705A2 (fr) 2003-03-19 2004-03-17 Unite de conversion de type dans un systeme multiprocesseur
JP2006506722A JP2006520957A (ja) 2003-03-19 2004-03-17 マルチプロセッサシステムのタイプ変換ユニット
US10/549,215 US20060179285A1 (en) 2003-03-19 2004-03-17 Type conversion unit in a multiprocessor system

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP03100708 2003-03-19
EP03100708.1 2003-03-19

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WO2004084064A2 true WO2004084064A2 (fr) 2004-09-30
WO2004084064A3 WO2004084064A3 (fr) 2005-08-04

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JP (1) JP2006520957A (fr)
KR (1) KR20050119125A (fr)
CN (1) CN1761941A (fr)
WO (1) WO2004084064A2 (fr)

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JP3799041B2 (ja) * 2002-03-28 2006-07-19 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Ｖｌｉｗプロセッサ
CN101727435B (zh) * 2008-10-28 2012-01-25 北京芯慧同用微电子技术有限责任公司 一种超长指令字处理器
KR101700405B1 (ko) 2010-03-22 2017-01-26 삼성전자주식회사 레지스터, 프로세서 및 프로세서 제어 방법
CN108055041B (zh) * 2017-12-22 2021-06-29 苏州中晟宏芯信息科技有限公司 一种数据类型转换电路单元及装置
CN109543845B (zh) * 2018-09-17 2020-04-14 合肥本源量子计算科技有限责任公司 单量子比特逻辑门的转化方法及装置
CN112394989A (zh) * 2019-08-13 2021-02-23 上海寒武纪信息科技有限公司 无符号转半精度浮点指令处理装置、方法及相关产品

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5642499A (en) * 1988-11-30 1997-06-24 Hitachi, Ltd. Method and apparatus for controlling timing of execution of saving and restoring operations in a processor system
US5878266A (en) * 1995-09-26 1999-03-02 Advanced Micro Devices, Inc. Reservation station for a floating point processing unit
WO2001042903A1 (fr) * 1999-12-07 2001-06-14 Hitachi, Ltd. Appareil et systeme de traitement de donnees
US20020133691A1 (en) * 1997-11-29 2002-09-19 Ip-First, Llc. Instruction set for bi-directional conversion and transfer of integer and floating point data

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5887160A (en) * 1996-12-10 1999-03-23 Fujitsu Limited Method and apparatus for communicating integer and floating point data over a shared data path in a single instruction pipeline processor
JP3123047B2 (ja) * 1998-10-02 2001-01-09 日本電気株式会社 マイクロプロセッサ

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5642499A (en) * 1988-11-30 1997-06-24 Hitachi, Ltd. Method and apparatus for controlling timing of execution of saving and restoring operations in a processor system
US5878266A (en) * 1995-09-26 1999-03-02 Advanced Micro Devices, Inc. Reservation station for a floating point processing unit
US20020133691A1 (en) * 1997-11-29 2002-09-19 Ip-First, Llc. Instruction set for bi-directional conversion and transfer of integer and floating point data
WO2001042903A1 (fr) * 1999-12-07 2001-06-14 Hitachi, Ltd. Appareil et systeme de traitement de donnees

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US20060179285A1 (en) 2006-08-10
JP2006520957A (ja) 2006-09-14
KR20050119125A (ko) 2005-12-20
WO2004084064A3 (fr) 2005-08-04
EP1606705A2 (fr) 2005-12-21
CN1761941A (zh) 2006-04-19

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