WO2004083985A2 - Architecture double bus - Google Patents
Architecture double bus Download PDFInfo
- Publication number
- WO2004083985A2 WO2004083985A2 PCT/FR2004/000624 FR2004000624W WO2004083985A2 WO 2004083985 A2 WO2004083985 A2 WO 2004083985A2 FR 2004000624 W FR2004000624 W FR 2004000624W WO 2004083985 A2 WO2004083985 A2 WO 2004083985A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- ram
- bus
- image
- image processing
- data
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/60—Memory management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/363—Graphics controllers
Definitions
- the present invention relates to the field of hardware architectures for image processing.
- the present invention relates more particularly to a specific double bus architecture.
- a multiplexer comprising a video port and a microprocessor port, provides the input of the RAM memory.
- a memory array, a sensor module and an input / output module, in addition to the multiplexer, constitute the pipeline architecture, allowing access to the RAM in three locations.
- a clock circuit is constructed to generate extremely stable internal clock pulses such that the interval of each clock pulse varies automatically according to the manufacturing process and the ambient temperature of use, adapting to the appropriate preload interval for the memory array, the multiplexer, and the sensor module.
- the converter includes a video RAM memory to store the luminance and chrominance of the image, a video controller to store data in the image memory or control the image memory to display the data stored in the image memory after reading and extraction , a converter which can change an image memory space with address index data of the image memory between the video controller and the image memory and a first transmission bus for the luminance data and that transmits synchronized image data and is connected between the video controller and image memory.
- the present invention intends to remedy the drawbacks of the prior art by proposing an architecture which makes it possible to reserve a portion of the flow towards the memory to the components specifically linked to image processing and to the printer interface.
- the invention relates, in its most general sense, to an electronic circuit for image processing comprising calculation means, input-output and communication interfaces, and at least one specific processing module of pre-program images, as well as at least one random access memory, characterized in that it comprises a random access memory management interface connected to a first bus known as a system bus for the exchange of data between said random access memory on the one hand, and the computation means and input-output interfaces on the other hand, and to a second bus called image bus, for the exchange of data between said RAM and said specific module for pre-image processing.
- a third bus called "peripheral bus" is connected to the system bus.
- a printing interface is connected to the image bus.
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- General Engineering & Computer Science (AREA)
- Computer Graphics (AREA)
- Computer Hardware Design (AREA)
- Image Processing (AREA)
- Multi Processors (AREA)
Abstract
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0303061A FR2852440B1 (fr) | 2003-03-12 | 2003-03-12 | Architecture double bus |
FR03/03061 | 2003-03-12 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2004083985A2 true WO2004083985A2 (fr) | 2004-09-30 |
WO2004083985A3 WO2004083985A3 (fr) | 2006-12-21 |
Family
ID=32893246
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/FR2004/000624 WO2004083985A2 (fr) | 2003-03-12 | 2004-03-12 | Architecture double bus |
Country Status (2)
Country | Link |
---|---|
FR (1) | FR2852440B1 (fr) |
WO (1) | WO2004083985A2 (fr) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5138702A (en) * | 1987-04-17 | 1992-08-11 | Minolta Camera Co., Ltd. | External image input/output device connectable image processing system |
US5826035A (en) * | 1994-06-10 | 1998-10-20 | Hitachi, Ltd. | Image display apparatus |
US20010007112A1 (en) * | 1997-07-02 | 2001-07-05 | Porterfield A. Kent | System for implementing a graphic address remapping table as a virtual register file in system memory |
US20020070941A1 (en) * | 2000-12-13 | 2002-06-13 | Peterson James R. | Memory system having programmable multiple and continuous memory regions and method of use thereof |
-
2003
- 2003-03-12 FR FR0303061A patent/FR2852440B1/fr not_active Expired - Fee Related
-
2004
- 2004-03-12 WO PCT/FR2004/000624 patent/WO2004083985A2/fr active Application Filing
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5138702A (en) * | 1987-04-17 | 1992-08-11 | Minolta Camera Co., Ltd. | External image input/output device connectable image processing system |
US5826035A (en) * | 1994-06-10 | 1998-10-20 | Hitachi, Ltd. | Image display apparatus |
US20010007112A1 (en) * | 1997-07-02 | 2001-07-05 | Porterfield A. Kent | System for implementing a graphic address remapping table as a virtual register file in system memory |
US20020070941A1 (en) * | 2000-12-13 | 2002-06-13 | Peterson James R. | Memory system having programmable multiple and continuous memory regions and method of use thereof |
Also Published As
Publication number | Publication date |
---|---|
FR2852440B1 (fr) | 2005-05-20 |
FR2852440A1 (fr) | 2004-09-17 |
WO2004083985A3 (fr) | 2006-12-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Ghosh et al. | Estimating specular roughness and anisotropy from second order spherical gradient illumination | |
Zickler et al. | Reflectance sharing: Predicting appearance from a sparse set of images of a known shape | |
Liu et al. | A new polarization image demosaicking algorithm by exploiting inter-channel correlations with guided filtering | |
FR2882602A1 (fr) | Logique de virtualisation | |
FR2739702A1 (fr) | Commutateur de peripheriques d'ordinateur | |
FR2702576A1 (fr) | Terminal pour un dialogue homme/machine avec un système informatique faisant intervenir une pluralité d'éléments de visualisation. | |
FR2583904A1 (fr) | Systeme d'ordinateur du type a trains multiples de donnees et instruction unique (simd), avec traitement selectif des donnees | |
WO2004083985A2 (fr) | Architecture double bus | |
WO2008058965A1 (fr) | Systeme de traitement d'objets graphiques comportant un gestionnaire graphique securise | |
EP3712838B1 (fr) | Dispositif électronique de traitement d'images | |
Fournier | Filtering normal maps and creating multiple surfaces | |
FR2841013A1 (fr) | Procede et systeme de gestion des evenements | |
FR2602074A1 (fr) | Systeme programmable d'acquisition et de visualisation rapide d'une image haute resolution. | |
FR2563024A1 (fr) | Dispositif pour modifier l'aspect des points d'une image sur un ecran d'une console de visualisation d'images graphiques | |
US7623179B2 (en) | Storage medium and method to control auto exposure by the same | |
EP0245152A1 (fr) | Processeur de calcul de la transformée de Fourier discrète comportant un dispositif de test en ligne | |
US20240046505A1 (en) | Electronic device and method with pose prediction | |
Kim et al. | Overexposure Mask Fusion: Generalizable Reverse ISP Multi-step Refinement | |
WO2023198728A1 (fr) | Prédiction du teint de la peau à l'aide d'un modèle de visage 3d | |
Djemal et al. | A real-time image processing with a compact FPGA-based architecture | |
Giljum | Versatile Compressive Sensing: Extensions of Random Projections for Imaging and Machine Vision | |
US20220086324A1 (en) | Apparatus and method with imaging reconstruction | |
EP0680015A1 (fr) | Dispositif d'alimentation en pixels d'une série d'opérateurs d'un circuit de compression d'images mobiles | |
Sharif et al. | High level synthesis implementation of object tracking algorithm on reconfigurable hardware | |
CN117764123A (zh) | 一种神经网络加速系统、其测试装置和电子设备 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A2 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A2 Designated state(s): BW GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
122 | Ep: pct application non-entry in european phase |