WO2004070954A1

WO2004070954A1 - A/d conversion circuit device

Info

Publication number: WO2004070954A1
Application number: PCT/JP2003/001196
Authority: WO
Inventors: Kenji Ito; Hisao Suzuki
Original assignee: Fujitsu Limited
Priority date: 2003-02-05
Filing date: 2003-02-05
Publication date: 2004-08-19
Also published as: AU2003207239A1

Abstract

The difference between high/low potentiasls (VRH, VRL) is divided by a vesistance dividing circuit (1) with a center potential (V2) centered, so that reference potentials (V1-V3) develop in nodes (17-19) and are inputted to the inverse input terminals (IM) of comparators (5-7) and comparators (8-10). An analog input signal (VIN) is inputted to the non-inverse input terminal (IP) of the comparators (5-7), and the opposie phase signal (VINB) of the analog input signal (VIN) to the non-inverse input terminal (IP) of the comparators (8-10). Each set of the comparators (5 and 10, 6 and 9, 7 and 8) in opposite phase input relations has equivalent circuit configurations. Thus, the fluctuation in the reference potential due to parasitic capacitors existing at the input stages of the capacitors (5-7) is cancelled, so that a rapid and accurate comparing operation is possible.

Description

Specification

A / D conversion circuit device

The present invention relates to an A / D conversion circuit device that converts an analog signal into a digital signal. In particular, the present invention relates to an A / D conversion circuit device capable of suppressing fluctuations in reference potential and performing a good comparison operation. Background art

As an influential AZD conversion circuit device that converts an analog signal into a digital signal at high speed (hereinafter abbreviated as A / D conversion), the following non-patent document 1 is exemplified as a prior art document. There is an A / D conversion circuit device called a parallel type in which a plurality of comparators are arranged and an analog input signal is compared with a plurality of reference potentials at once. In a parallel type A / D conversion circuit device, a method of generating a reference potential generally uses a resistance dividing circuit.

FIG. 5 shows a configuration diagram of an A / D conversion circuit device for obtaining a reference potential by a resistance dividing circuit. In this AZD conversion circuit device, the potential difference between the potential VRH of the high-potential power supply connected to the terminal 105 and the potential VRL of the low-potential power supply connected to the terminal 108 is determined by a plurality of resistance elements ( In the figure, two resistors 106 and Γ07 are shown, each of which has a resistance value of r.) A resistor divider 101 is connected in series to divide the voltage. A reference potential V1 is generated at a node 109 which is a connection point of the resistive elements in the resistance dividing circuit 101. Of the two input terminals of the comparator 104, the inverted input terminal IM is connected to the node 109 and the reference potential V1 is input. <The non-inverted input terminal IP is the analog input signal via the terminal 102. VIN is input. In the comparator 104, VIN and VI are compared, and an A / D conversion is performed by outputting a digital output signal VUT from the output terminal 103. As the prior art document, the following non-patent document 1 is exemplified.

Iwao Sagara, "Introduction to AZD / D / A Converter Circuits", First Edition, 5th Edition, Nikkan Kogyo Shinbunsha, February 10, 1990, p. 2 16-2 17

FIG. 6 is an example of the input section of the comparator 104. The non-inverting input terminal IP and the inverting input terminal IM are connected to a differential pair composed of a field effect transistor (hereinafter abbreviated as FET) 112, 113. The comparison operation is based on the input voltage difference between the analog input signal VIN input to the non-inverting input terminal IP and the reference potential V1 input to the inverting input terminal IM. This is performed by shunting currents II and 12 between the nodes 12 and 11. During the comparison operation, the analog input signal V IN changes, so that the current I 1 changes. As a result, the current I 2 also fluctuates. Due to the fluctuation of the current 12, the drain voltage of the FET 113 changes. Due to the fluctuation of the drain voltage, charge and discharge of the parasitic capacitance 1 16 of the FET 113 occurs. As a result, the current i flows in and out of the gate of FET113 via the inverting input terminal.

FIG. 7 is a circuit diagram of the AZD conversion circuit device of FIG. 5 when the current i is regarded as the current source 11 1. Equation (1) is obtained when the potential V 1, of the node 109 when the current i flows, is obtained.

Equation (1)

V I '= (1/2) * (V H + VR L-i * r)

According to the equation (1), the reference potential V1 of the node 109 changes by (1/2) * i * r with respect to VI (= (1/2) * (VRH + VRL)). In other words, in this A / D conversion circuit device, the current i flows in and out of the gate of the FET 113 through the inverting input terminal due to the charging and discharging of the charge to and from the parasitic capacitance 116. The reference potential V1 fluctuates.

The comparator 104 compares the analog input signal VIN with V 1, when the reference potential V 1 changes to VI ′. Therefore, in this A / D conversion circuit device, there is a problem that the analog input signal VIN cannot be compared with the accurate reference potential V 1. The time at which this variation occurs depends on the parasitic capacitance Since it is determined by a time constant determined by 1 16 and the resistance value of the resistance element in the resistance dividing circuit 101, it is greatly affected when performing high-speed AZD conversion.

To reduce the amount of change from V I to V I, the resistance value r should be reduced. However, by reducing the resistance value r, the current that constantly flows through the resistance dividing circuit 101 increases, which is a problem from the viewpoint of power consumption.

The present invention has been made to solve the problems of the prior art. That is, the purpose is to provide an A / D conversion circuit device that suppresses the reference potential fluctuation caused by charging and discharging the parasitic capacitance of the comparator, and obtains the reference potential that enables high-speed and accurate comparison operation by a resistance dividing circuit. It is to provide. Disclosure of the invention

In order to achieve the above object, an AZD conversion circuit device according to claim 1, wherein at least two resistance elements connecting two voltage sources are connected in series, and a resistance element row is formed at a connection point of the resistance element row. An A / D conversion circuit device comprising at least one reference potential and at least one first comparator to which a first input signal is inputted, wherein the A / D conversion circuit device is provided for each first comparator, At least one second comparator to which at least one reference potential input to the first comparator and a second input signal are input is provided.

In the A / D conversion circuit device according to claim 1, the reference potential input to the first comparator is also input to the second comparator in addition to the first comparator.

The A / D conversion circuit device according to claim 2 is the A / D conversion circuit device according to claim 1, wherein the first comparator and the second comparator have an equivalent circuit configuration, and the first comparator is Among the connection points of the resistance element row, a connection point at a predetermined position is connected to a center connection point having the same resistance value from any of the two voltage sources, and the second comparator is connected to a predetermined position with respect to the center connection point. It is characterized in that connection points located symmetrically with the position are connected.

In the A / D conversion circuit device according to claim 2, in the resistor element row, two Of the two connection points that are symmetrical with respect to the center connection point where the resistance values from any of the pressure sources are equal, the first comparator to which one contact point is connected and the other connection point are connected This is an equivalent circuit configuration to the second comparator.

As a result, the two connection points symmetrical with respect to the center connection point are connected to the first comparator and the second comparator, and the first and second comparators have an equivalent circuit configuration. Therefore, the charging and discharging of the parasitic capacitance of the input terminal of each comparator is symmetrical with each other, and the fluctuation of the reference potential caused by the charging and discharging is equal. The fluctuation of the reference potential can be suppressed by the symmetric and equivalent fluctuation amount.

In the A / D conversion circuit device according to claim 3, in the AZD conversion circuit device according to claim 1 or 2, the resistance element row has a center connection point having the same resistance value from any of the two voltage sources among the connection points. It is characterized in that equivalent resistance elements are arranged at symmetrical positions with respect to.

In the A / D conversion circuit device according to claim 3, an equivalent resistance element is arranged between the connection points located symmetrically with respect to the center connection point.

Thus, a reference potential symmetric with respect to the reference potential generated at the center connection point can be generated at two connection points symmetrically positioned with respect to the center connection point.

In the A / D conversion circuit device according to claim 4, in the A / D conversion circuit device according to claim 1, by inputting the source input signal, an in-phase input signal having the same phase as the source input signal and a reverse phase having the opposite phase. A signal input section for outputting a phase input signal, the in-phase input signal is input to the first comparator as a first input signal, and the anti-phase input signal is input to the second comparator as a second input signal It is characterized by being performed.

In the A / D conversion circuit device according to claim 4, the in-phase input signal and the in-phase input signal are generated based on the source input signal in the signal input section, and the in-phase input signal is first compared as the first input signal. The negative-phase input signal is input to the second comparator as a second input signal.

By inputting the source input signal, the first comparator and the second comparator And input signals having an opposite phase relationship to each other.

In the A / D conversion circuit device according to claim 5, in the A / D conversion circuit device according to claim 4, the in-phase input signal is obtained by folding an in-phase input signal with respect to a center potential generated at a center connection point. Signal.

Here, to fold the in-phase input signal with respect to the center potential means to invert the potential by the potential difference from the center potential to the in-phase input signal on the opposite side to the in-phase input signal with respect to the center potential. In other words, the in-phase input signal and the anti-phase input signal have a potential difference equal to each other with respect to the central potential, and are in a phase opposite to each other.

With this, input signals having a relationship of opposite phases to each other with respect to the center potential can be input to the first comparator and the second comparator.

In the A / D conversion circuit device according to claim 6, in the parallel AZD conversion circuit device according to claim 4 or 5, the in-phase input signal is an analog signal and the anti-phase input signal is an inverted analog signal. Is preferred.

In the AZD conversion circuit device according to claim 7, in the A / D conversion circuit device according to claim 1, the input terminal of the first comparator to which the first input signal is input, and the second input signal are input. Both of the input terminals of the second comparator are inverting input terminals or non-inverting input terminals.

In the A / D conversion circuit device according to claim 7, both the first input signal input to the first comparator and the second input signal input to the second comparator are an inverting input terminal or a non-inverting input. Input to the terminal.

Thus, the potential relationship between the first input signal input to the input terminal of the first comparator and the reference potential, and the second input signal input to the input terminal of the second comparator and the reference potential And the potential relationship between the two are opposite to each other. The fluctuation of the reference voltage generated by charging and discharging the parasitic capacitance of the input terminal of the first comparator and the fluctuation of the reference voltage generated by charging and discharging the parasitic capacitance of the input terminal of the second comparator There is an anti-phase relationship, and the fluctuation of each reference potential is suppressed. The fluctuation of the reference voltage during the comparison operation is suppressed, and a high-speed and accurate comparison operation can be realized. An A / D conversion circuit device according to claim 8 is the A / D conversion circuit device according to claim 1, wherein a comparison result is output from one of the first comparator and the second comparator.

Since the output of the first comparator and the output of the second comparator have an inverse logic relationship with each other, a comparison result can be obtained only with the output from one of the comparators. In the A / D conversion circuit device according to claim 9, in the A / D conversion circuit device according to claim 1, at least one first comparator and at least one second comparator have an equivalent circuit configuration. Preferably, there is. Thereby, the circuit characteristics between the comparators can be matched. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a configuration diagram of a 2-bit A / D conversion circuit device of an embodiment. FIG. 2 is a configuration diagram of a circuit device for obtaining V IN and V INB. FIG. 3 shows the reference potential in the 2-bit AZD conversion circuit device of the embodiment.

This is the result of simulation of the fluctuation of V1.

FIG. 4 is a waveform chart showing voltage conditions used in the simulation.

FIG. 5 is a configuration diagram of an A / D conversion circuit using a conventional resistance dividing circuit.

FIG. 6 is an equivalent circuit of the input section of the comparator.

FIG. 7 is a circuit diagram when the fluctuating current i is regarded as a current source. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, an embodiment of an A / D conversion circuit device according to the present invention will be described in detail with reference to the drawings based on FIG. 1 to FIG.

FIG. 1 shows an example in which the present invention is applied to a 2-bit parallel A / D conversion circuit device as an embodiment of the present invention.

In the resistance division circuit 1, a plurality of resistance elements connected in series (four elements 12 to 15 are illustrated in the figure. Each of the resistance elements 12 to The resistance values of 15 are all r. ), The input voltage range of the parallel A / D converter circuit device of the present embodiment is the potential VRH by the high potential side power supply connected to the terminal 11 and the potential VRH by the low potential side power supply connected to the terminal 16. Voltages between the potential VRL and the reference potentials VI to V3 are output. The resistance elements 12 to 15 are arranged symmetrically with respect to a point having the same resistance value as viewed from the power supply on the high potential side and from the power supply on the low potential side.

The nodes 17 to 19 are connected to the inverting input terminals IM of the comparators 8 to 10 in addition to the inverting input terminals IM of the comparators 5 to 7 for performing the A / D conversion operation. That is, the comparators 5 and 8 are connected to the node 17, the comparator 6 and the comparator 9 are connected to the node 18, and the comparator 7 and the comparator 10 are connected to the node 19, respectively.

The analog input signal VIN is input from the terminal 3 to the non-inverting input terminals IP of the comparators 5 to 7. Further, a non-inverting input terminal IP of the comparators 8 to 10 receives a reverse-phase signal VINB of the analog input signal VIN from the terminal 4. This inverted-phase signal VINB is obtained by inverting the analog input signal VIN around a center potential which is equidistant from the potential VRH and the potential VRL. That is, the comparator 5 and the comparator 10, the comparator 6 and the comparator 9, and the comparator 7 and the comparator 8 receive signals having phases opposite to each other. Here, each set of comparators (5 and 10; 6 and 9; and 7 and 8) operating in opposite phases has the same circuit configuration. The above-mentioned center potential is a potential generated at the node 18 which has the same resistance value when viewed from the high-potential side power supply and the low-potential side power supply in the resistance dividing circuit 1 and is a reference. The potential V 2 corresponds to this. The analog input signal VIN and the negative-phase signal VINB can be generated by a circuit as shown in FIG. 2, for example. In the circuit of FIG. 2, by inputting the analog signal V 0 from the terminal 31, the analog input signal VIN in phase with the analog signal V 0 is input to the terminal 39, and the analog signal V 0 is input to the terminal 40. Can output the reverse phase signal VINB. In the circuit of FIG. 2, terminal 31 is connected to the non-inverting input terminal IP of amplifier 41. Node 43 is connected via resistor element 35 (resistance value R 2). A node 44 is connected via a resistor 44 (resistance value R 5) to a node 49, and a ground potential 33 is connected via a capacitor 32. Node 44 is connected to node 47 and to the inverting input terminal IM of amplifier 41. The node 47 is connected to the node 45 via the resistance element 34 (resistance value R 1) and to the non-inverting input terminal IP of the amplifier 42. Node 49 is connected to node 48 and to the inverting input terminal IM of amplifier 42. Node 45 is connected to the output terminal of amplifier 41 and to node 46. Node 46 is connected to node 48 via resistor element 37 (resistance value R4) and to terminal 39. Node 48 is connected to node 50 via resistance element 36 (resistance value R 3). Node 50 is connected to the output terminal of amplifier 42 and to terminal 40.

In the circuit of FIG. 2, when the analog signal V 0 is input to the terminal 31, the analog input signal V IN output to the terminal 39 is expressed by the following equation (2). In addition, the inverted-phase signal V I NB output to the terminal 40 is represented by Expression (3).

Equation (2)

V I N = ((R 1 / R 2) + 1) * V 0

Equation (3)

V I N B = (1+ (R 4 / R 5)-((R 1 * R 4) / (R 2 * R 3))) N V 0

By appropriately selecting the resistance values R1 to R5 according to the equations (2) and (3), the negative-phase signal VINB becomes a negative-phase signal of the analog input signal VIN.

In the circuit of FIG. 1, if it is defined that ΔV = VRH—VRL, the reference potential V1 generated at the node 17 is (3/4) * AV + VRL. Similarly, the reference potential V2 generated at the node 18 is (274) * AV + VRL, and the reference potential V3 generated at the node 19 is (1Z4) * AV + VRL. Here, attention is focused on the comparator 5 and the comparator 10. For example, when the analog input signal VIN fluctuates in the comparator 5, the comparator 5 It is assumed that a current i flows from the inverting input terminal IM to the node 17 when the parasitic capacitance of the inverting input terminal IM occurs. The current i is a transient current, and flows through the resistance dividing circuit 1 as an alternating current. That is, the current i flows through the combined resistance in which r and 3 r are connected in parallel.

On the other hand, in the comparator 10, the parasitic capacitance of the inverting input terminal IM of the comparator 10 is charged and discharged due to the fluctuation of the negative-phase signal VINB, and the current i ′ flows. Here, the comparator 5 and the comparator 10 have the same circuit configuration, and the potential relationship between the analog input signal VIN and the reference potential V1 in the comparator 5 and the negative-phase signal VINB in the comparator 10 and the reference The potential relationship with the potential V3 is opposite to each other. Therefore, current i, has the same magnitude as current i and flows in the opposite direction to current i. That is, the current i ⁵ will be flowing to the inverting input terminal IM of the comparator 1 0 from the node 1-9, the current i with respect to the combined capacitance connected between r and 3 r in parallel flows also reverse. Thus, the fluctuation of the reference potential caused by the flow of the current i is offset by the current i,. Similar phenomena hold between the comparator 6 and the comparator 9 and between the comparator 7 and the comparator 8. Therefore, the fluctuations of the reference voltages V1 to V3 are canceled out, and the accurate reference potentials V1 to V3 can be compared with the analog input signal VIN.

Output signals from the comparators 5 to 7 are input to the encoder 2. Here, the comparators 5 to 7 generally have the same performance. That is, the comparators 5 to 7 need to have the same circuit configuration. Further, as described above, the circuit configurations of the comparators 5 to 7 and the comparators 8 to 10 that operate in the opposite phase to the comparators 5 to 7 need to be the same. From the above, it is preferable that the circuit configurations of all the comparators 5 to 10 be the same. The output signals from the actual use comparators 5 to 7 are thermometer codes, converted by the encoder 2, and output to the terminals 20 and 21 as 2-bit digital values. FIG. 3 shows the variation of the reference voltage V1 in the 2-bit parallel A / D converter circuit device shown in FIG. 1 by using the conventional 2-bit parallel A / D converter without the comparators 8 to 10. Comparison with the case of fluctuation of reference voltage V1 in circuit device This is the result of a simulation performed to perform the simulation. Here, the resistance value r is 10 MΩ, and the parasitic capacitance value C 0 (the capacitance value of the parasitic capacitance 1 16 in FIG. 6) is 2.28 fF. In addition, the potential VRH from the high-potential power supply is 838 mV, the potential VRL from the low-potential power supply is 812 mV, and the analog input signal VIN is a sine wave (center potential 82 5 mV, amplitude 13 mV, frequency 13 kHz). The negative-phase signal VI NB is obtained by inverting the analog input signal VIN with respect to the central potential of 825 mV. The potential VRH from the high-voltage power supply, the potential VRL from the low-voltage power supply, the analog input signal VIN, and the negative-phase signal VI NB are illustrated in FIG.

In FIG. 3, the change 61 of the reference potential VI in the 2-bit A / D converter circuit device of FIG. 1 is shown in comparison with the change 62 of the reference potential V1 in the conventional AZD conversion circuit device. ing. As can be seen from this figure, the amount of change in the reference potential V1 in the 2-bit A / D conversion circuit device shown in FIG. 1 is significantly reduced as compared with the case of the prior art.

According to the parallel-type A / D conversion circuit device of the embodiment described above, two comparators 5 to 7 and two comparators 8 to 10 are provided at each of the nodes 17 to 19 in the resistance dividing circuit 1. Connect as a pair. Further, the comparators 5 to 7 and the comparators which are located symmetrically with respect to the node 18 having the same resistance value when viewed from the power supply on the high potential side and the power supply on the low potential side in the resistance dividing circuit 1 The circuit configurations of 10 to 8 are the same. By inputting input signals having phases opposite to each other with respect to the central potential V2, which is the reference potential output to the node 18, to the comparators 5 to 7 and the comparators 8 to 10, the reference potential changes. Can be reduced. This enables fast and accurate A / D conversion.

In the parallel A / D conversion circuit device using the resistance division circuit 1, the resistance division circuit 1 has a large number of resistance elements 12 to 15. In the parallel type A / D converter circuit device according to the prior art, in order to reduce the fluctuation of the reference potential due to the charging / discharging current to the parasitic capacitance existing at the input terminals of the comparators 5 to 7, the resistance in the resistance dividing circuit 1 A method of reducing the resistance values of the elements 12 to 15 is given. However, the resistance element 1 in the resistance division circuit 1 Decreasing the resistance values of 2 to 15 increases the current flowing through the resistance elements, which leads to an increase in power consumption by the resistance elements 12 to 15. Therefore, it is not realistic to reduce the resistance values of the resistance elements 12 to 15 in the resistance division circuit 1.

The time during which the reference potential fluctuates is determined by a time constant determined by the resistance values of the resistance elements 12 to 15 in the resistance division circuit 1 and the capacitance value of the parasitic capacitance ₍ the resistance element 1 2 in the resistance division circuit 1). As described above, the time constant increases because the resistance value needs to be increased as described above, so that the fluctuation time of the reference potential becomes longer, and in the parallel A / D conversion circuit device according to the related art, According to the present invention, it is possible to suppress the fluctuation of the reference potential without reducing the resistance values of the resistance elements 12 to 15 in the resistance division circuit 1. That is, the parallel AZD conversion circuit device of the present invention can provide a high-speed and accurate comparison operation.

Also, in the prior art, in a parallel A / D conversion circuit device, or when a larger number of resistance elements connected to a resistance division circuit are connected, the current flows through the parasitic capacitance of each comparator. The potential fluctuation of the reference potential due to the current flowing through many resistance elements may be large. The present invention is effective when applied to such a case, and can effectively suppress the potential fluctuation of the reference potential in a multi-bit parallel A / D conversion circuit device to which a large number of resistance elements are connected. Even when a large number of resistance elements are connected and have a large resistance value and thus have a large time constant with respect to the parasitic capacitance, high-speed operation can be performed by suppressing potential fluctuations at the reference potential. In addition, the present invention is effective when applied to a multi-bit parallel A / D conversion circuit device that requires a high-speed A / D conversion operation.

Here, the resistance elements 12 to 15 in the resistance division circuit 1 in FIG. 1 are an example of a resistance element row, and divide a potential between a potential VRH and a potential VRL given by a power supply to generate a resistance element. Reference potentials V1 to V3 are generated at connection nodes 17 to 19 of 12 to 15 respectively. Comparators 5 to 7 are examples of first comparator And the comparators 8 to 10 are examples of the second comparator. The comparators 5 and 10, 6 and 9, and 7 and 8 have equivalent circuit configurations. As a result, the charging and discharging of the parasitic capacitance of the input terminal of each comparator becomes symmetrical with each other, and the fluctuation of the reference potential caused by the charging and discharging becomes equal. The fluctuation of the reference potential can be suppressed by the symmetric and equivalent fluctuation amount.

The resistance elements 12 to 15 in the resistance division circuit 1 are arranged symmetrically as the center connection point 18 at the point where the resistance value is the same when viewed from the high-potential side power supply or the low-potential side power supply. It is desirable to be done. Thereby, a reference potential symmetric with respect to the reference potential generated at the center connection point 18 can be generated at two connection points symmetrically positioned with respect to the center connection point 18.

FIG. 2 shows an example of the signal input unit. By inputting the analog signal V 0, the comparators 5 to 7 and the comparators 8 to 10 have opposite phases to each other. The phase signal VINB can be supplied. <The negative phase signal VINB is a signal obtained by folding back the analog input signal VIN with respect to the center potential V2 that is equidistant from the potential VRH and the potential VRL. Here, the fold of the analog input signal VIN with respect to the center potential V 2 means that the potential difference from the center potential V 2 to the analog input signal VIN is equal to the potential on the opposite side of the center potential V 2 from the analog input signal VIN. Is to invert. That is, the analog input signal VIN and the negative-phase signal VINB have a potential difference equal to each other with respect to the central potential V2 and are in a reverse-phase relationship. Accordingly, input signals having a phase opposite to each other with respect to the center potential V 2 can be input to the comparators 5 to 7 and the comparators 8 to 10 <Non-inversion of the comparators 5 to 7 The analog input signal VIN is input to the input terminal IP. On the other hand, the non-inverter input terminals IP of the comparators 8 to 10 receive the inverted-phase signal VΓΝ. Reference potentials V1 to V3 generated at nodes 17 to 19 are applied to the inverting input terminals IM of the comparators 5 to 7 and the comparators 8 to 10. Here, the reference potentials V1 to V3 generated at the nodes 17 to 19 may be input to the non-inverting input terminals IP of the comparators 5 to 7 and the comparators 8 to 10. In this case, comparators 5 to 7 The analog input signal VIN is input to the inverting input terminal IM, and the negative-phase signal VINB is input to the inverting input terminals IM of the comparators 8 to 10.

As a result, the potential relationship of the input signal with respect to the symmetrical reference potential becomes opposite in phase between the comparators 5 to 7 and the comparators 10 to 8 at the symmetrical positions. 7 through 7 and the comparators 10 through 8 at the symmetric positions, the fluctuation of the reference potential due to the charging and discharging of the parasitic capacitance can be offset.

Only the outputs from the comparators 5 to 7 are input to the encoder 2. The outputs from the comparators 5 to 7 and the outputs from the comparators 8 to 10 have an inverse relationship to each other. Therefore, the outputs from the comparators 8 to 10 may be input to the encoder 2 instead of the outputs from the comparators 5 to 7. In general, all the comparators and the circuit configuration of the comparators are the same.

Note that the present invention is not limited to the above-described embodiment, and it goes without saying that various improvements and modifications can be made without departing from the spirit of the present invention. In the embodiment, the parallel type A / D conversion circuit device has been described. However, the present invention can be applied to A / D conversion circuit devices other than the parallel type. For example, the present invention can be applied to a parallel section of a serial-parallel AZD conversion circuit device.

Further, in the present embodiment, the circuit configuration of each comparator is assumed to be the same. However, in addition to the case where the circuit configuration of each comparator is completely the same, even if the circuit configuration of each comparator is not the same, the same The current i flowing out and in due to the parasitic capacitance of the input terminal of the comparator when the analog input signal is input may be the same.

Even if the comparators 5 to 10 are not the same, the pair of comparators (5 and 10, 6 and 9, 7 and 8) located at symmetrical positions that cancel the fluctuation of the reference potential is the same, or Any equivalent circuit configuration may be used. Industrial applicability

According to the present invention, an equivalent comparator is provided at a symmetric position of the resistance dividing circuit. Accordingly, it is possible to provide an A / D conversion circuit device capable of performing a high-speed and accurate comparison operation by canceling a potential fluctuation of a reference potential caused by charging / discharging a parasitic capacitance existing in an input stage of a comparator.

Claims

The scope of the claims

1. A resistance element row in which at least two resistance elements connecting two voltage sources are connected in series, at least one reference potential generated at a connection point of the resistance element row, and a first input signal A / D conversion circuit device comprising at least one first comparator to which

And at least one second comparator provided for each of the first comparators, the at least one reference potential input to the first comparator and the second input signal being input to the first comparator. A / D conversion circuit device.

2. The first comparator and the second comparator have an equivalent circuit configuration, and the first comparator is configured such that, from among the connection points of the resistor element row, any one of the two voltage sources The connection point at a predetermined position is connected to a center connection point having the same resistance value, and the second comparator is connected to a connection point at a position symmetrical to the predetermined position with respect to the center connection point. The A / D conversion circuit device according to claim 1, wherein

3. The resistive element array is characterized in that equivalent resistive elements are arranged at symmetrical positions with respect to a center connection point having the same resistance value from any of the two voltage sources among the connection points. The A / D conversion circuit according to claim 1 or 2.

4. A signal input unit that receives a source input signal to output an in-phase input signal that is in phase with the source input signal and an in-phase input signal that is in phase opposite to the source input signal, and the in-phase input signal is the first input signal. 2. The A / A converter according to claim 1, wherein the input signal is input to the first comparator as the second input signal, and the negative-phase input signal is input to the second comparator as the second input signal. 3. D conversion circuit device,

5. The parallel A / D according to claim 4, wherein the opposite-phase input signal is a signal obtained by folding the in-phase input signal with respect to a center potential generated at the center connection point. Conversion circuit device.

6. The parallel signal according to claim 4, wherein the in-phase input signal is an analog signal, and the anti-phase input signal is an inverted analog signal. Type A / D conversion circuit device.

7. Both the input terminal of the first comparator to which the first input signal is input and the input terminal of the second comparator to which the second input signal is input. Inverting input terminal or non-inverting terminal The A / D conversion circuit device according to claim 1, wherein the A / D conversion circuit device is an input terminal.

8. The parallel A / D conversion circuit device according to claim 1, wherein a comparison result is output from one of the first comparator and the second comparator.

9. The A / D conversion circuit device according to claim 1, wherein each of the at least one first comparator and the at least one first comparator has an equivalent circuit configuration.