WO2004064151A3 - Electronic device and method of manufacturing a substrate - Google Patents

Electronic device and method of manufacturing a substrate Download PDF

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Publication number
WO2004064151A3
WO2004064151A3 PCT/IB2003/006345 IB0306345W WO2004064151A3 WO 2004064151 A3 WO2004064151 A3 WO 2004064151A3 IB 0306345 W IB0306345 W IB 0306345W WO 2004064151 A3 WO2004064151 A3 WO 2004064151A3
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
electronic device
semiconductor element
manufacturing
semiconductor
Prior art date
Application number
PCT/IB2003/006345
Other languages
French (fr)
Other versions
WO2004064151A2 (en
Inventor
Veen Nicolaas J A Van
Samber Marc A De
Arendonk Anton P M Van
Johannus W Weekamp
Original Assignee
Koninkl Philips Electronics Nv
Veen Nicolaas J A Van
Samber Marc A De
Arendonk Anton P M Van
Johannus W Weekamp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv, Veen Nicolaas J A Van, Samber Marc A De, Arendonk Anton P M Van, Johannus W Weekamp filed Critical Koninkl Philips Electronics Nv
Priority to AU2003292484A priority Critical patent/AU2003292484A1/en
Publication of WO2004064151A2 publication Critical patent/WO2004064151A2/en
Publication of WO2004064151A3 publication Critical patent/WO2004064151A3/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/142Metallic substrates having insulating layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05568Disposition the whole external layer protruding from the surface
    • HELECTRICITY
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05573Single external layer
    • HELECTRICITY
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    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L2224/05599Material
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    • H01L2224/10Bump connectors; Manufacturing methods related thereto
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    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399Material
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/10Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
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    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/07802Adhesive characteristics other than chemical not being an ohmic electrical conductor
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    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
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    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
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    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]
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    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

Provided is an electronic device (1) with a semiconductor element (5) and a substrate (3) of a material chosen from the group of AlSi, AlSiC, AlSiGe and the like. These materials are provided by providing preferably crystalline particles of a semiconductor material in a thermally conducting matrix material, after which the material is adequately strengthened by a heat treatment. The semiconductor element (5) is a digital integrated circuit with a large number of first contact pad (32) by preference. In such applications, thermal mismatch can easily lead to breakdown of the packaged device. This is prevented through the use of the substrate (3) of the invention.
PCT/IB2003/006345 2003-01-13 2003-12-10 Electronic device and method of manufacturing a substrate WO2004064151A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003292484A AU2003292484A1 (en) 2003-01-13 2003-12-10 Electronic device and method of manufacturing a substrate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP03075079 2003-01-13
EP03075079.8 2003-01-13

Publications (2)

Publication Number Publication Date
WO2004064151A2 WO2004064151A2 (en) 2004-07-29
WO2004064151A3 true WO2004064151A3 (en) 2005-01-20

Family

ID=32695601

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2003/006345 WO2004064151A2 (en) 2003-01-13 2003-12-10 Electronic device and method of manufacturing a substrate

Country Status (3)

Country Link
AU (1) AU2003292484A1 (en)
TW (1) TW200504897A (en)
WO (1) WO2004064151A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101099925B1 (en) 2003-10-10 2011-12-28 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Electronic device and carrier substrate for same
JP6392010B2 (en) * 2014-07-03 2018-09-19 株式会社アドバンテスト Test carrier
CN108746637B (en) * 2018-06-26 2021-01-08 中南大学 Aluminum silicon/aluminum silicon carbide gradient composite material and preparation method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5774336A (en) * 1996-02-20 1998-06-30 Heat Technology, Inc. High-terminal conductivity circuit board
US5886407A (en) * 1993-04-14 1999-03-23 Frank J. Polese Heat-dissipating package for microcircuit devices
EP0938137A2 (en) * 1998-02-24 1999-08-25 Sumitomo Electric Industries, Ltd. Member for semiconductor device and method for producing the same
US6262477B1 (en) * 1993-03-19 2001-07-17 Advanced Interconnect Technologies Ball grid array electronic package
US6300161B1 (en) * 2000-02-15 2001-10-09 Alpine Microsystems, Inc. Module and method for interconnecting integrated circuits that facilitates high speed signal propagation with reduced noise

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6262477B1 (en) * 1993-03-19 2001-07-17 Advanced Interconnect Technologies Ball grid array electronic package
US5886407A (en) * 1993-04-14 1999-03-23 Frank J. Polese Heat-dissipating package for microcircuit devices
US5774336A (en) * 1996-02-20 1998-06-30 Heat Technology, Inc. High-terminal conductivity circuit board
EP0938137A2 (en) * 1998-02-24 1999-08-25 Sumitomo Electric Industries, Ltd. Member for semiconductor device and method for producing the same
US6300161B1 (en) * 2000-02-15 2001-10-09 Alpine Microsystems, Inc. Module and method for interconnecting integrated circuits that facilitates high speed signal propagation with reduced noise

Also Published As

Publication number Publication date
TW200504897A (en) 2005-02-01
WO2004064151A2 (en) 2004-07-29
AU2003292484A8 (en) 2004-08-10
AU2003292484A1 (en) 2004-08-10

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