WO2004063836A2 - Procede et systeme de croisement de domaines d'horloge et d'adaptation de format au moyen de protocole de transfert synchrone - Google Patents

Procede et systeme de croisement de domaines d'horloge et d'adaptation de format au moyen de protocole de transfert synchrone Download PDF

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WO2004063836A2
WO2004063836A2 PCT/IB2004/001190 IB2004001190W WO2004063836A2 WO 2004063836 A2 WO2004063836 A2 WO 2004063836A2 IB 2004001190 W IB2004001190 W IB 2004001190W WO 2004063836 A2 WO2004063836 A2 WO 2004063836A2
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data
signal
upstream
input
downstream
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PCT/IB2004/001190
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English (en)
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WO2004063836A3 (fr
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Didier Velez
Sophie Rolland
Jean-Pierre Le Glanic
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Thomson Licensing S.A.
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Publication of WO2004063836A3 publication Critical patent/WO2004063836A3/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention relates to the optimization of a data processing chain using synchronous handshake protocol by operating frequency and data format adaptation, including a pseudo synchronous clock domain crossing mechanism.
  • the data processing path is a chain of several blocks. Each block performs a specific processing task on input data coming from the preceding or upstream block and provides output data to the next or downstream block.
  • the transfer of data between the upstream and downstream blocks is controlled by a handshake protocol that is based on two signals: (1 ) a Ready to Send (RTS) signal sent from the upstream block to the downstream block to indicate that the upstream block is ready to transfer data to the downstream block, and (2) a Ready To Receive (RTR) signal sent from the downstream block to the upstream block to indicate that the downstream block is ready to accept data from the upstream block.
  • RTS Ready to Send
  • RTR Ready To Receive
  • the data is moved from the upstream block to the downstream block when both signals are true.
  • FIG. 1 is a block diagram of an exemplary conventional synchronous Ready To Send and Ready To Receive (“RTS/RTR”) handshake scheme 10.
  • RTS/RTR synchronous Ready To Send and Ready To Receive
  • the first handshake channel 1 6 is configured to carry a Ready To Send (“RTS") handshake signal, which is active to indicate that upstream block 12 is prepared to send at least one word of data over a data bus 20 to downstream block 14.
  • the second handshake channel 18 is configured to carry a Ready To Receive (“RTR”) handshake signal, which is active to indicate that downstream block 14 is prepared to accept at least one word of data from upstream block 12 via the data bus 20.
  • RTS Ready To Send
  • RTR Ready To Receive
  • each block has its own control and relies on the RTS/RTR signal to know if data are received/sent. There is no necessity to have a top-level controller. During each clock cycle for which a handshake has occurred, one word of data is transferred from upstream block 12 to downstream block 14 over the data bus 20.
  • each block has a required input minimum bandwidth. In other words, each block has to be fed with enough data so that it can process and send the required amount of data to the next block in a certain period of time.
  • the present invention provides a method and system that allows the exchange of data between different clock domains and in the desired format using a synchronous handshake protocol.
  • the present invention provides a method and system that allows the blocks in a data stream to use the synchronous handshake interface without requiring the blocks to have the same clock frequency or data word length.
  • the present invention provides a method for optimizing a data processing chain using synchronous handshake protocol by adapting the operating frequency and the data format between an upstream block that has an upstream operating frequency and an upstream data format and a downstream block that has a downstream operating frequency and a downstream data format.
  • the upstream block generates an upstream RTS signal and an upstream clock signal
  • the downstream block generates a downstream RTR signal and a downstream clock signal.
  • the method of the present invention comprises the steps of: receiving the upstream RTS signal, the upstream clock signal, the downstream RTR signal and the downstream clock signal; generating an upstream adaptation RTR signal when ready to receive data from the upstream block; receiving data from the upstream block in the upstream data format when the upstream RTS signal and the upstream adaptation RTR signal are active; transforming the data from the upstream data format into the downstream data format; generating a downstream adaptation RTS signal when ready to send data to the downstream block; and sending the data to the downstream block in the downstream data format when the downstream RTR signal and the downstream adaptation RTR signal are active.
  • the adaptation block comprises a speed adaptation block and a format adaptation block.
  • the speed and format adaptation block can be utilized in any order.
  • the speed adaptation block receives the upstream RTS signal and the upstream clock from the upstream block, and the downstream clock from the downstream block; and the said format adaptation block receives the downstream RTR signal and the downstream clock from the downstream block.
  • the speed adaptation block generates an upstream adaptation RTR signal when it is ready to receive data from the upstream block, and generate an adaptation RTS signal when it is ready to send data to the format adaptation block.
  • the format adaptation block generates an adaptation RTR signal when it is ready to receive data from the speed adaptation block, and generates a downstream adaptation RTS signal when it is ready to send data to the downstream block.
  • the speed adaptation block receives data from the upstream block in the upstream data format when the upstream RTS and upstream adaptation RTR signals are active, and sends data to the format adaptation block in the upstream data format when the adaptation RTS and the adaptation RTR signals are active.
  • the format adaptation block transforms the data from the upstream data format into the downstream data format, and sends the data to the downstream block in the downstream data format when the downstream adaptation RTS and the downstream RTR signals active.
  • a speed adaptation block optimizes a data processing chain using synchronous handshake protocol by adapting the operating frequency between an upstream block, having an upstream operating frequency and generating an upstream RTS signal and an upstream clock signal; and a downstream block, having a downstream operating frequency and generating a downstream RTR signal and a downstream clock signal.
  • the speed adaptation apparatus includes a data pipeline that receives data words from the upstream block and sends data words to the downstream block, a counter that generates a COUNT signal that indicates the number of data words in said the pipeline, a RTR assembly that receives the COUNT signal and generates an upstream adaptation RTR signal when the data pipeline is ready to receive data from the upstream block, a RTS assembly that receives the COUNT signal and generates a downstream adaptation RTS signal when the data pipeline is ready to send data to the downstream block, an upstream handshake assembly that generates an input handshake signal when both the upstream RTS signal and the upstream adaptation RTR signal are active, and a downstream handshake assembly that generates an output handshake signal when both the downstream RTR signal and the downstream adaptation RTS signal are active.
  • the data word is received by the data pipeline when the IN_HS signal is generated, and the data word is sent from the data pipeline (200) when the OUT_HS signal is generated.
  • a data stream implemented in accordance with the present invention will respect the handshake protocol with adjacent upstream and downstream blocks; can support different clock speeds for each individual block; can support different data formats for each individual block; allows blocks to exchange and process data using lower possible clock speeds which reduces power dissipation, and allows easy adaptation of the data format from block to block.
  • FIG. 1 is a block diagram of a conventional synchronous Ready To Send and Ready To Receive (“RTS/RTR”) handshake scheme
  • FIG. 2 is a block diagram of an exemplary RTS/RTR handshake scheme with an adaptation block according to the present invention
  • FIG. 3 is a block diagram of an exemplary RTS/RTR handshake scheme with an adaptation block comprising a speed adaptation block followed by a format adaptation block;
  • FIG. 4 is a block diagram of an exemplary RTS/RTR handshake scheme with an adaptation block comprising a format adaptation block followed by a speed adaptation block;
  • FIG. 5 is a block diagram of an exemplary RTS/RTR handshake scheme with an adaptation block comprising a speed adaptation block
  • FIG. 6 is a block diagram of an exemplary speed adaptation block shown in FIGS. 3-5 for use when the upstream clock frequency is slower than the downstream clock frequency;
  • FIG. 7 is a first waveform diagram for the speed adaptation block shown in FIG. 6 when the ratio of the clock frequencies is 2;
  • FIG. 8 is a second waveform diagram for the speed adaptation block shown in FIG. 6 when the ratio of the clock frequencies is 2;
  • FIG. 9 is a block diagram of an exemplary speed adaptation block shown in FIGS. 3-5 for use when the upstream clock frequency is faster than the downstream clock frequency;
  • FIG. 10 is a waveform diagram for the speed adaptation block shown in FIG. 9 when the ratio of the clock frequencies is 4;
  • FIG. 1 1 is a waveform diagram for the speed adaptation block shown in FIG. 9 when the ratio of the clock frequencies is 2;
  • FIG. 2 is a block diagram of an exemplary adaptation block handshake scheme 50 according to the present invention.
  • an upstream block 52 is connected to a downstream block 54 through an intervening adaptation block 56.
  • a first handshake channel 58 is configured to carry an UPSTREAM READY TO SEND ("RTS") handshake signal from the upstream block 52 to the adaptation block 56.
  • the UPSTREAM RTS handshake signal is used to indicate that the upstream block 52 is prepared to send at least one word of data over an upstream data bus 62 to the adaptation block 56.
  • a second handshake channel 64 is configured to carry a DOWNSTREAM RTS signal from the adaptation block 56 to the downstream block 54.
  • the DOWNSTREAM RTS signal is used to indicate that the adaptation block 56 is prepared to send at least one word of data over a downstream data bus 68 to the downstream block 54.
  • a third handshake channel 66 is configured to carry a DOWNSTREAM READY TO RECEIVE ("RTR") handshake signal from the downstream block 54 to the adaptation block 56.
  • the DOWNSTREAM RTR handshake signal is used to indicate that the downstream block 54 is prepared to accept at least one word of data from the adaptation block 56 over the downstream data bus 68.
  • a fourth handshake channel 60 is configured to carry an UPSTREAM RTR signal from the adaptation block 56 to the upstream block 52.
  • the UPSTREAM RTR signal is used to indicate that the adaptation block 56 is prepared to receive at least one word of data over the upstream data bus 62 from the upstream block 52.
  • FIG. 3 is a top-level block diagram of one embodiment of the adaptation block 56 of FIG. 2.
  • the adaptation block 56 is implemented by a speed adaptation block 80 followed by a format adaptation block 82.
  • the speed adaptation block 80 is used when the upstream block 52 and the downstream block 54 run at different clock speeds.
  • the speed adaptation block 80 has both an upstream clock input 90 and a downstream clock input 92 and the ratio between the different clock speeds is a parameter of the speed adaptation block 80.
  • the speed adaptation block 80 transfers data downstream while respecting the handshake protocol of both the upstream block 52 and the downstream block 54.
  • the speed adaptation block 80 acts as a small buffer in passing data from the upstream block 52 to the downstream block 54.
  • the format adaptation block 82 is used when the upstream block 52 and the downstream block 56 have different data word lengths.
  • the ratio between the word lengths is a parameter of the format adaptation block 82.
  • the format adaptation block 82 When the data word length of the downstream block 54 is longer than the data word length of the upstream block 52, the format adaptation block 82 combines several successive words of data from the upstream block 52 to form a single word to pass to the downstream block 54.
  • the format adaptation block 82 segments one data word from the upstream block 52 into several separate data words to pass to the downstream block 54.
  • the format adaptation block 82 functions in a single clock domain.
  • the adaptation block 56 can be implemented by the speed adaptation block 80 alone, the format adaptation block 82 alone, or a combination of speed adaptation blocks 80 and format adaptation blocks 82, depending upon the speed and data requirements of the upstream block 52 and the downstream block 54.
  • the speed adaptation block 80 adapts differing clock speeds.
  • the format adaptation block 82 adapts differing data formats. These blocks can be inserted in virtually any order. However, the maximum bandwidth of the chain can be impacted depending on this order. As will be shown below, to maximize bandwidth, it is preferable to put the format adaptation block 82 in the higher frequency clock domain so it can perform format adaptation at the higher clock frequency.
  • FIG. 3 shows an embodiment of the adaptation block 56 in which the speed adaptation block 80 is upstream of the format adaptation block 82.
  • the first handshake channel 58, the second handshake channel 64, the third handshake channel 66, the fourth handshake channel 60, the upstream data bus 62 and the downstream data bus 68 are shown again in FIG. 3.
  • the speed adaptation block 80 and the format adaptation block 82 are coupled by a first adaptation handshake channel 84, a second adaptation handshake channel 86 and a first adaptation data bus 88.
  • the first adaptation handshake channel 84 is configured to carry an ADAPTATION RTS handshake signal that indicates when the speed adaptation block 80 is prepared to send at least one word of data over the first adaptation data bus 88 to the format adaptation block 82.
  • the second adaptation handshake channel 84 is configured to carry a ADAPTATION RTR signal that indicates when the format adaptation block 82 is prepared to receive at least one word of data over the first adaptation data bus 88 from the speed adaptation block 80.
  • the upstream clock input 90 of the speed adaptation block 80 receives the clock signal of the upstream block 52
  • the downstream clock input 92 of the speed adaptation block 80 receives the clock signal of the downstream block 54.
  • the format adaptation block 82 has a single clock input 94 that, since the format adaptation block 82 is on the downstream side of the speed adaptation block 80, receives the clock signal of the downstream block 54.
  • FIG. 4 shows an alternative embodiment of the adaptation block 56 in which the format adaptation block 82 is upstream of the speed adaptation block 80.
  • the format adaptation block 82 and the speed adaptation block 80 are coupled by a third adaptation handshake channel 104, a fourth adaptation handshake channel 106 and a second adaptation data bus 108.
  • the third adaptation handshake channel 104 is configured to carry an ADAPTATION RTS handshake signal that indicates when the format adaptation block 82 is prepared to send at least one data word over the second adaptation data bus 108 to the speed adaptation block 80.
  • the fourth adaptation handshake channel 104 is configured to carry an ADAPTATION RTR signal that indicates when the speed adaptation block 80 is prepared to receive at least one data word over the second adaptation data bus 108 from the format adaptation block 82.
  • the speed adaptation block 80 receives the clock inputs of both the upstream block 52 and the downstream block 54 at the upstream clock input 90 and the downstream clock input 92, respectively. Since the format adaptation block 82 is on the upstream side of the speed adaptation block 80, the clock input 94 of the format adaptation block 82 receives the clock signal of the upstream block 52.
  • the order of the speed adaptation block 80 and the format adaptation block 82 in the adaptation block 56 can impact the maximum bandwidth of the data stream from the upstream block 52 to the downstream block 54.
  • One case where this occurs is when the upstream block 52 runs at a faster clock frequency and has a shorter data word length than the downstream block 54: for example, when the upstream block 52 runs at a F MHz clock speed and the downstream block 54 runs at a slower F/N MHz clock speed, and the upstream block 52 processes length W data words and the downstream block 54 processes length N*W words.
  • the upstream block 52 can send a data word of length W on the upstream data bus 62 up to once every clock cycle of the upstream clock.
  • the upstream block 52 sends the UPSTREAM RTS signal on the first handshake channel 58.
  • the speed adaptation block 80 acts as a buffer between the clock domains of the upstream block 52 and the downstream block 54.
  • the buffer of the speed adaptation block 80 is not full, it sends the UPSTREAM RTR signal on the fourth handshake channel 60.
  • a data word of length W will be transferred from the upstream block 52 to the speed adaptation block 80.
  • the format adaptation block 82 works in the slower clock domain of the downstream block 54. Since there are N clock cycles of the upstream clock (F MHz) for every one clock cycle at the downstream clock (F/N MHz), the format adaptation block 82 can not accept more than one data word every N clock cycles of the upstream clock. Thus, once the buffer of the speed adaptation block 80 is full, the speed adaptation block 80 can not accept more than one data word of size W every N clock cycles of the upstream clock. When both the ADAPTATION RTS and the ADAPTATION RTR signals are active, a handshake occurs and a data word of size W is sent on the adaptation data bus 88 from the speed adaptation block 80 to the format adaptation block 82.
  • the format adaptation block 82 combines N successive data words of size W received from the speed adaptation block 80 into a single data word of size N*W to pass to the downstream block 54.
  • the format adaptation block 82 running at the slower downstream clock speed, needs at least N*N clock cycles of the upstream clock to receive N data words to form one data word of length N*W to pass to the downstream block 54.
  • the format adaptation block 82 is ready to send out a word of length N*W on the downstream data bus 68, it sends the DOWNSTREAM RTS signal on the second handshake channel 64.
  • the downstream block 54 can accept up to one data every downstream clock cycle When the downstream block 54 is ready to receive a data word on the downstream data bus 68, it sends a DOWNSTREAM RTR signal on the fourth handshake channel 66. When both the DOWNSTREAM RTS and the DOWNSTREAM RTR signals are active, a handshake occurs and a data word of length N*W is transferred from the format adaptation block 82 to the downstream block 54 via the downstream data bus 68. Therefore, in this case with the adaptation block 56 shown in FIG. 3, the maximum throughput is one data word of length N*W every N"N clock cycles of the faster upstream clock, or a frequency of f/N*N MHz.
  • the upstream block 52 can send a data word of length W on the upstream data bus 62 up to once every clock cycle of the upstream clock.
  • the upstream block 52 sends the UPSTREAM RTS signal on the first handshake channel 58.
  • the format adaptation block 82 works in the faster upstream clock domain and combines N successive data words of size W received from the upstream block 52 into a single data word of size N*W to pass downstream.
  • the format adaptation block 82 can accept up to one data word every upstream clock cycle.
  • a data word of length W is transferred from the upstream block 52 to the format adaptation block 82. It takes at least N cycles of the upstream clock for the format adaptation block 100 to assemble a word of length N*W to send out over the adaptation data bus 108.
  • the format adaptation block 82 is ready to send out a word of length N*W on the adaptation data bus 108, it sends the ADAPTATION RTS signal on the third adaptation handshake channel 104.
  • the downstream block 54 can accept up to one data word of length N*W every N clock cycles of the upstream clock.
  • the speed adaptation block 80 once its buffer is full, can accept up to one data word of size N*W every N clock cycles of the upstream clock.
  • the speed adaptation block 80 sends the ADAPTATION RTR signal on the fourth adaptation handshake channel 106.
  • the speed adaptation block 80 sends the ADAPTATION RTR signal on the fourth adaptation handshake channel 106.
  • both the ADAPTATION RTS and the ADAPTATION RTR signals are active, a handshake occurs and a data word of size N*W is sent on the adaptation data bus 108 from the format adaptation block 82 to the speed adaptation block 80.
  • the speed adaptation block 80 When the speed adaptation block 80 is ready to send a data word downstream, it sends a DOWNSTREAM RTS signal along the third handshake channel 64 to the downstream block 54.
  • the downstream block 54 When the downstream block 54 is ready to receive a data word of length N*W on the downstream data bus 68, it sends a DOWNSTREAM RTR signal on the fourth handshake channel 66.
  • both the DOWNSTREAM RTS and the DOWNSTREAM RTR signals are active, a handshake occurs and a data word of length N*W is transferred from the speed adaptation block 80 to the downstream block 54 via the downstream data bus 108. Therefore, in this case with the adaptation block 56 shown in FIG. 4, the maximum throughput is one data word of length N*W every N clock cycles of the faster upstream clock, or at a frequency of f/N MHz.
  • the embodiment shown in Fig. 3 can support a bandwidth of up to one data word of length N*W at a frequency of f/(N*N) MHz, while the embodiment shown in Fig. 4 can support a bandwidth up to N times faster of one word of length N*W at a frequency of f/N MHz,.
  • the order of the speed adaptation block 80 and the format adaptation block 82 in the adaptation block 56 impacts the maximum data bandwidth is when the upstream block 52 runs at a slower clock frequency and has a longer data word length than the downstream block 54: for example, the upstream block 52 runs at a clock speed of F/N MHz and the downstream block 54 runs at a faster clock speed of F MHz; and the upstream block 52 processes data words of length N*W and the downstream block 54 processes data words of length W.
  • the upstream block 52 can send up to one data word of length N*W to the speed adaptation block 80 at up to once every clock cycle of the upstream clock
  • the speed adaptation block 80 can send up to one data word of length N*W to the format adaptation block 82 at up to once every clock cycle of the upstream clock.
  • the format adaptation block 82 operates in the faster clock domain of the downstream block 54, and segments one data word of length N*W received from the speed adaptation block 80 into N data words of length W to send to the downstream block 54.
  • the downstream block 54 can accept up to one data word of length N each clock cycle of the faster downstream clock.
  • the format adaptation block 82 can segment a data word of length N*W received from the speed adaptation block 80 and send the resulting N data words of length W to the downstream block 54 at up to once every N clock cycles of the faster downstream clock which corresponds to one clock cycle of the upstream clock. Therefore, in this case with the adaptation block 56 shown in FIG. 3, the maximum throughput is one data word of length N*W every N clock cycles of the faster downstream clock, or at a frequency of f/N MHz.
  • the upstream block 52 can send up to one data word of length N*W to the format adaptation block 82 each upstream clock cycle.
  • the format adaptation block 82 operates in the slower upstream clock domain, and segments one data word of length N*W into N data words of size W to pass downstream.
  • the format adaptation block 82 can send up to one data word of length W on the adaptation data bus 108 every clock cycle of the slower upstream clock.
  • the downstream block 54 can accept up to one data word of length W each clock cycle of the faster downstream clock, thus the speed adaptation block 80 can accept up to one data word of length W every clock cycle of the faster downstream clock.
  • the speed adaptation block 80 can only receive one data word of length W from the format adaptation block 82 once every clock cycle of the slower upstream clock. Therefore, in this case with the adaptation block 56 shown in FIG. 4, the maximum throughput is one data word of length W every clock cycle of the slower upstream clock, or one data word of length N*W every N clock cycles of the slower upstream clock.
  • the embodiment of the adaptation block 56 shown in Fig. 3 supports a data bandwidth of up to one data word of length N*W at a frequency of f/N MHz, while the embodiment shown in Fig. 4 only supports a bandwidth N times slower of one word of length N*W at a frequency of f/(N*N) MHz.
  • FIG. 5 shows an alternative embodiment of the adaptation block 56 implemented by only the speed adaptation block 80.
  • FIG. 6 is a block diagram of the exemplary speed adaptation block 80 shown in FIGS. 3-5 for use when the upstream block 52 has a slower clock frequency, F MHz, and the downstream block 54 has a higher clock frequency F*N MHz, the ratio between the clock speeds, N, is an integer positive number.
  • the speed adaptation block 80 is implemented by synchronous digital logic circuitry and logic blocks as discussed herein. However, it is noted that in alternative embodiments the speed adaptation block 80 may be implemented by any other suitable hardware, software, or combination thereof.
  • the speed adaptation block 80 shown in FIG. 6 for connecting a low speed clock to domain to a high speed clock domain includes a data pipeline 200 that can hold up to two data words, a counter 240, an upstream AND gate 250, a downstream AND gate 260, a RTS assembly 300 and a RTR assembly 350.
  • the upstream AND gate 250 has an input 252 coupled to the first handshake channel 58 that carries the UPSTREAM RTS signal sent by the upstream block 52, an input 254 coupled to the fourth handshake channel 60 that carries the UPSTREAM RTR signal generated in the speed adaptation block 80, and an output 256 that carries the input handshake (IN HS) signal.
  • the IN_HS signal indicates when data is received on the upstream data bus 62.
  • the downstream AND gate 260 has an input 262 coupled to the second handshake channel 64 that carries the DOWNSTREAM RTS signal generated in the speed adaptation block 80, an input 264 coupled to the third handshake channel 66 that carries the DOWNSTREAM RTR signal sent by the downstream block 54, and an output 266 that carries the output handshake (OUT_HS) signal.
  • OUT_HS output handshake
  • the counter 240 keeps track of the number of data words stored in the pipeline 200.
  • the counter 240 has an input 242 coupled to the IN_HS signal generated by the upstream AND gate 250, an input 244 coupled to the OUTJHS signal generated by the downstream AND gate 260, an input 246 coupled to the downstream clock input 92, an input 245 coupled to the downstream reset input 96, and an output 248 that contains the counter value (COUNT) signal.
  • the counter 240 counts up and down between 0 and 2*N.
  • the faster downstream clock received at input 246 increments the counter value by 1 .
  • the IN_HS signal received at input 242 increases the counter value, and the OUTJHS signal received at input 244 decreases the counter value.
  • the IN_HS signal increases the counter value by 1 and the OUTJHS signal decreases the counter value by N.
  • the value of the counter output 248 is less than N, there are no data words stored in the pipeline 200.
  • the value of the counter output 248 is greater than or equal to N but less than 2*N, there is one data word stored in the pipeline 200.
  • the value of the counter output 248 equals 2*N, there are two data words stored in the pipeline 200.
  • the RTS assembly 300 and the RTR assembly 350 generate the RTS and the RTR signals of the speed adaptation block 80, respectively.
  • the RTS and RTR signals are generated synchronously in order to break any combinational path.
  • the RTR signal is asserted as long as the pipeline 200 is not full (the counter output 248 is less than 2*N); and the RTS signal is asserted as long as the pipeline 200 is not empty (the counter output 248 is greater than or equal to N).
  • the RTR assembly 350 includes a logic block 330 and a flip-flop 340.
  • the logic block 330 includes an input 332 coupled to the counter output 248 carrying the COUNT signal, an input 334 coupled to the output of the AND gate 260 that carries the OUT_HS signal, an input 336 coupled to the output of the AND gate 250 that carries the IN_HS signal, and an output 338 carrying the RTR signal coupled to an input 342 of the flip-flop 340.
  • the flip-flop 340 includes the input 342 coupled to the output of the logic block 330, a clock input 344 coupled to the upstream clock input 90, a reset input 346 coupled to the upstream reset input 94, and an output 348 coupled to the fourth handshake channel 60 that carries the UPSTREAM RTR signal.
  • the logic block 330 of the RTR assembly 350 implements the following function which defines the RTR signal at the output 338:
  • the flip-flop 340 operates as follows. When the upstream reset signal at the reset input 346 is active, the output 348 is held to a "0" value. When the upstream reset signal is not active, the value at the output 348 is set on the rising edge of the upstream clock received at the clock input 344 to the value of the RTR signal received at input 342 from the RTR logic block 330. The value at the output 348 is the UPSTREAM RTR signal generated and used by the speed adaptation block 80 and sent to the upstream block 52.
  • the RTS assembly 300 includes a logic block 31 0 and a flip-flop 320.
  • the logic block 31 0 includes an input 31 2 coupled to the output of the AND gate 260 that carries the OUTJHS signal, an input 314 coupled to the output of the AND gate 250 that carries the INJHS signal, an input 31 6 coupled to the counter output 248 carrying the COUNT signal, and an output 31 8 carrying the RTS signal coupled to an input 322 of the flip-flop 320.
  • the flip-flop 320 includes the input 322 coupled to the output of the logic block 31 0, a clock input 324 coupled to the downstream clock input 92, a reset input 326 coupled to the downstream reset input 96, and an output 328 coupled to the second handshake channel 64 that carries the DOWNSTREAM RTS signal.
  • the logic block 31 0 of the RTS assembly 300 implements the following function which defines the RTS signal at the output 31 8:
  • the flip-flop 320 operates as follows. When the downstream reset signal at the reset input 326 is active, the output 328 is held to a "0" value. When the downstream reset signal is not active, the value at the output 328 is set on the rising edge of the downstream clock received at the clock input 324 to the value of the RTS signal received at input 322 from the RTS logic block 31 0. The value at the output 328 is the DOWNSTREAM RTS signal generated and used by the speed adaptation block 80 and sent to the downstream block 54.
  • the data pipeline 200 is formed by a first data register 21 0, a second data register 220, a multiplexer 230, an OR gate 270, a first logic block 280, and a multiplexer logic block 290.
  • the second data register 220 has a data input 222 coupled to the upstream data bus 62, an enable input 224 coupled to the INJHS signal from the output of the AND gate 250, a clock input 226 coupled to the upstream clock input 90, and a data output 228 coupled to a second input 234 of the multiplexer 230.
  • the INJHS signal received at the enable input 224 is active, the value at the data output 228 is set on the rising edge of the upstream clock received at the clock input 226 to the value received at the data input 222 on the upstream data bus 62 from the upstream block 52.
  • the multiplexer logic block 290 has an input 292 coupled to the counter output 248 and an output 294 coupled to a selector input 236 of the multiplexer 230.
  • the output 294 of the multiplexer logic block 290 is active when the COUNT signal received at the input 292 has a value of "2*N", otherwise the output 294 is not active.
  • the multiplexer 230 has a first data input 232 coupled to the upstream data bus 62, the second data input 234 coupled to the data output 228 of the second data register 220, the selector input 236 coupled to the output 294 of the multiplexer logic block 290, and a data output 238 coupled to a data input 21 2 of the first data register 21 0.
  • the output 294 of the multiplexer logic block 290 received at the selector input 224 is not active, the value received from the upstream data bus 62 at the input 232 is passed through the multiplexer 230 to the data output 238, and when the output 294 of the multiplexer logic block 290 is active, the value received from the second data register 220 at the input 234 is passed through the multiplexer 230 to the data output 238.
  • the first logic block 280 has an input 282 coupled to the counter output 248 and an output 284 coupled to an input 272 of the OR gate 270.
  • the output 284 of the first logic block 280 is active when the COUNT signal received at the input 282 has a value less than "N", otherwise the output 284 is not active.
  • the OR gate 270 has the input 272 coupled to the output 284 of the first logic block 280, an input 274 coupled to the OUTJHS signal output by the AND gate 260, and an output 278 coupled to an enable input 21 4 of the first data register 21 0.
  • the output 278 of the OR gate 270 is active when either of the output 284 of the first logic block 280 or the OUTJHS signal are active, otherwise the output 278 is not active.
  • the first data register 21 0 has the data input 21 2 coupled to the output 238 of the multiplexer 230, the enable input 21 4 coupled to the output 278 of the OR gate 270, a clock input 21 6 coupled to the downstream clock input 92, and a data output 21 8 coupled to the downstream data bus 68.
  • the output 278 of the OR gate 270 received at the enable input 21 4 is active, the value at the data output 21 8 is set on the rising edge of the downstream clock received at the clock input 21 6 to the value received at the data input 21 2 from the multiplexer 230.
  • the pipeline 200 acts as a first-in-first-out (FIFO) queue; the input coming from the upstream data bus 62 and being stored in either the first data register 21 0 or the second data register 220, and the output being put on the downstream data bus 68 by the first data register 210.
  • the multiplexer 230 selects, depending on the number of data words stored the pipeline 200, the source of the data word to be stored in the first data register 210.
  • the counter 240 keeps track of the number of data words stored in the pipeline 200. When the pipeline 200 is empty, the counter output 248 will be less than
  • the INJHS signal will enable the second data register 220, and on the upstream clock cycle the word on the upstream data bus 62 will be stored in the second data register 220.
  • the output 284 of the first logic block 280 will be active, causing the output of the OR gate 270 to be active, which will enable the first data register 210.
  • the selector input 236 of the multiplexer 230 will cause the multiplexer 230 to pass the data word on the upstream data bus 62 to the multiplexer output 238.
  • the data word at the multiplexer output 238 will be stored in the first data register 210.
  • the word on the upstream data bus 62 is stored in both the first data register 210 and the second data register 220.
  • the pipeline 200 When the pipeline 200 has only one data word stored in it, that word is stored in the first data register 210 and the COUNT signal is greater than or equal to N but less than 2*N.
  • the RTR logic output 338 is set to a "0" value according to the equation given above, then, on the rising edge of the upstream clock, the RTR flip-flop output 348 will be made inactive causing the output of the upstream AND gate 250, which is the IN_HS signal, to become inactive. Otherwise, two different things can occur when the IN_HS signal is active depending on whether the OUT_HS signal is active. First, if the INJHS is active and the OUTJHS signal is not active the following will occur.
  • the INJHS signal will enable the second data register 220, and on the upstream clock cycle the word on the upstream data bus 62 will be stored in the second data register 220.
  • both inputs to the OR gate 270 will be inactive, causing the output 278 of the OR gate 270 to be inactive, which will not enable the first data register 210.
  • the word on the upstream data bus 62 is stored in the second data register 220 and the word in the first data register 210 is unchanged.
  • the OUT_HS signal means the data word on the downstream bus 68, at the output 218 of the first data register 210, is being transferred to the downstream block 54.
  • the INJHS signal will enable the second data register 220, and on the upstream clock cycle the word on the upstream data bus 62 will be stored in the second data register 220.
  • the OUTJHS signal at the input 274 of the OR gate 270 will cause the output 278 of the OR gate 270 to be active, which will enable the first data register 210.
  • the selector input 236 of the multiplexer 230 will cause the multiplexer 230 to pass the data word on the upstream data bus 62 to the multiplexer output 238.
  • the data word at the multiplexer output 238 will be stored in the first data register 210.
  • the word on the downstream bus 68 is passed to the downstream block 54, and the word on the upstream data bus 62 is stored in both the second data register 220 and the first data register 210.
  • the counter output 248 will be equal to 2*N.
  • the output 348 of the RTR assembly 350 will remain inactive until the OUT_HS signal becomes active, which will keep input 254 of the input AND gate 250 inactive, preventing an IN_HS signal from occurring.
  • the selector input 236 will cause the multiplexer 230 to pass the data word stored in the second data register 220 to the multiplexer output 238.
  • the OUTJHS signal becomes active the contents of the first data register 210 are transferred to the downstream block 54 on the downstream data bus 68 and, with the downstream clock cycle, the first data register 210 will store the data word at the multiplexer output 238 and the counter 240 will decrement the count value by N causing the output 338 of the RTR logic block 330 to go active.
  • the word on the downstream bus 68 is passed to the downstream block 54, and the next data word from the second data register 220 is transferred to the first data register 210, leaving one word stored in the pipeline 200. Then on the next upstream clock cycle the output 348 of the RTR assembly 350 will go active causing the INJHS signal to become active.
  • FIG. 9 is a block diagram of the exemplary speed adaptation block 80 shown in FIGS. 3-5 for use when the upstream block 52 has a faster clock frequency, F*N MHz, and the downstream block 54 has a slower clock frequency F MHz, where the ratio between the clock speeds, N, is an integer positive number.
  • the speed adaptation block 80 is implemented by synchronous digital logic circuitry and logic blocks as discussed herein. However, it is noted that in alternative embodiments the speed adaptation block 80 may be implemented by any other suitable hardware, software, or combination thereof.
  • a data pipeline 400 that can hold up to two data words, a counter 410, an upstream AND gate 420, a downstream AND gate 430, a RTS assembly 440 and a RTR assembly 470.
  • the upstream AND gate 420 has an input 422 coupled to the first handshake channel 58 that carries the UPSTREAM RTS signal sent by the upstream block 52, an input 424 coupled to the fourth handshake channel 60 that carries the UPSTREAM RTR signal generated in the speed adaptation block 80, and an output 426 that carries the input handshake (INJHS) signal.
  • the IN_HS signal is active, otherwise the INJHS signal is not active.
  • the IN HS signal indicates when data is transferred on the upstream data bus 62.
  • the downstream AND gate 430 has an input 432 coupled to the second handshake channel 64 that carries the DOWNSTREAM RTS signal generated in the speed adaptation block 80, an input 434 coupled to the third handshake channel 66 that carries the DOWNSTREAM RTR signal sent by the downstream block 54, and an output 436 that carries the output handshake (OUT_HS) signal.
  • OUT_HS output handshake
  • the counter 41 0 keeps track of the number of data words stored in the pipeline 400.
  • the counter 41 0 has an input 41 2 coupled to the INJHS signal generated by the upstream AND gate 420, an input 41 4 coupled to the OUT_HS signal generated by the downstream AND gate 430, an input 41 6 coupled to the upstream clock input 90, an input 41 5 coupled to the upstream reset input 94, and a counter output 41 8 containing the counter value (COUNT) signal.
  • the counter 410 counts up and down between 0 and 2*N. The faster upstream clock received at input 41 6 increments the counter value by 1 .
  • the IN_HS signal received at input 41 2 increases the counter value, and the OUTJHS signal received at input 41 4 decreases the counter value.
  • the IN_HS signal increases the counter value by N and the OUTJHS signal decreases the counter value by 1 .
  • the value at the counter output 41 8 is less than N, there are no data words stored in the pipeline 400.
  • the value at the counter output 41 8 is greater than or equal to N but less than 2*N, there is one data word stored in the pipeline 400.
  • the value at the counter output 418 is equal to 2*N, there are two data words stored in the pipeline 400.
  • the RTS assembly 440 and the RTR assembly 470 generate the RTS and the RTR signals of the speed adaptation block 80, respectively.
  • the RTS and RTR signals are generated synchronously. In general, the RTR signal will be asserted as long as the pipeline 400 is not full, and the RTS signal will be asserted as long as the pipeline 400 is not empty.
  • the RTR assembly 470 includes a logic block 480 and a flip-flop 490.
  • the logic block 480 includes an input 482 coupled to the counter output 418 carrying the COUNT signal, an input 484 coupled to the output of the AND gate 430 carrying the OUTJHS signal, an input 486 coupled to the output of the AND gate 420 carrying the INJHS signal, and an output 488 carrying the RTR signal coupled to an input 492 of the flip-flop 490.
  • the flip-flop 490 includes the input 492 coupled to the output of the logic block 490, a clock input 494 coupled to the upstream clock input 90, a reset input 496 coupled to the upstream reset input 94, and an output 498 coupled to the fourth handshake channel 60 that carries the UPSTREAM RTR signal.
  • the flip-flop 490 operates as follows. When the upstream reset signal at the reset input 496 is active, the output 498 is held to a "0" value. When the upstream reset signal is not active, the value at the output 498 is set on the rising edge of the upstream clock received at the clock input 494 to the value of the RTR signal received at input 492 from the RTR logic block 480. The value at the output 498 is the UPSTREAM RTR signal generated and used by the speed adaptation block 80 and sent to the upstream block 52.
  • the RTS assembly 440 includes a logic block 450 and a flip-flop 460.
  • the logic block 450 includes an input 452 coupled to the output of the AND gate 430 that carries the OUTJHS signal, an input 454 coupled to the output of the AND gate 420 that carries the INJHS signal, an input 456 coupled to the counter output 41 8 that carries the COUNT signal, and an output 458 carrying the RTS signal coupled to an input 462 of the flip-flop 460.
  • the flip-flop 460 includes the input 462 coupled to the output of the logic block 450, a clock input 464 coupled to the downstream clock input 92, a reset input 466 coupled to the downstream reset input 96, and an output 468 coupled to the second handshake channel 64 that carries the DOWNSTREAM RTS signal.
  • the logic block 450 of the RTS assembly 440 implements the following function which defines the RTS signal at the output 468:
  • the flip-flop 460 operates as follows. When the downstream reset signal at the reset input 466 is active, the output 468 is held to a "0" value. When the downstream reset signal is not active, the value at the output 468 is set on the rising edge of the downstream clock received at the clock input 464 to the value of the RTS signal received at input 462 from the RTS logic block 450. The value at the output 468 is the DOWNSTREAM RTS signal generated and used by the speed adaptation block 80 and sent to the downstream block 54.
  • the data pipeline 400 is formed by a first data register 51 0, a second data register 520, a third data register 530, a multiplexer 540, an OR gate 560, and a first logic block 550.
  • the third data register 530 is only needed if N, the ratio of the clock speeds, is greater than 2.
  • the second data register 520 has a data input 522 coupled to the upstream data bus 62, an enable input 524 coupled to the INJHS signal, a clock input 526 coupled to the upstream clock input 90, and a data output 528 coupled to a data input 532 of the third data register 530 and coupled to a second input 544 of the multiplexer 540.
  • the INJHS signal received at the enable input 524 is active, the value at the data output 528 is set on the rising edge of the upstream clock received at the clock input 526 to the value received at the data input 522 on the upstream data bus 62 from the upstream block 52.
  • the third data register 530 has the data input 532 coupled to the output 528 of the second data register 520, an enable input 534 coupled to the INJHS signal, a clock input 536 coupled to the upstream clock input 90, and a data output 538 coupled to a third input of the multiplexer 540.
  • the value at the data output 538 is set on the rising edge of the upstream clock received at the clock input 536 to the value received at the data input 532 on the upstream data bus 62 from the upstream block 52.
  • the multiplexer 540 has a first data input 542 coupled to the upstream data bus 62, the second data input 544 coupled to the data output 528 of the second data register 520, the third data input 544 coupled to the data output 538 of the third data register 530, a selector input 545 coupled to the counter output 418, and a data output 548 coupled to a data input 51 2 of the first data register 510.
  • the selector input 545 When the selector input 545 has a value of "0" or “1 ", the value received from the upstream data bus 62 at the input 542 is passed through to the data output 548; when the selector input 545 has a value of "N” or “N + 1 ", the value received from the second data register 520 at the input 544 is passed through to the data output 548; and for any other value of the selector input 545, the value received from the third data register 530 at the input 546 is passed through to the data output 548.
  • the first logic block 550 has an input 552 coupled to the counter output 418 and an output 554 coupled to an input 562 of the OR gate 560.
  • the output 554 is active when the COUNT signal received at the input 552 does not equal "2*N", otherwise the output 554 is not active.
  • the OR gate 560 has the input 562 coupled to the output 554 of the first logic block 550, an input 564 coupled to the OUT_HS signal, and an output 568 coupled to an enable input 514 of the first data register 510.
  • the output 568 of the OR gate 560 is active when either of the output 554 of the first logic block 550 or the OUTJHS signal are active, otherwise the output 568 is not active.
  • the first data register 510 has the data input 512 coupled to the output 548 of the multiplexer 540, the enable input 514 coupled to the output 568 of the OR gate 560, a clock input 516 coupled to the downstream clock input 92, and a data output 518 coupled to the downstream data bus 68.
  • the enable input 514 When the enable input 514 is active, the value at the data output 518 is set on the rising edge of the downstream clock received at the clock input 51 6 to the value received at the data input 512 from the multiplexer 540.
  • the pipeline 400 acts as a first-in-first-out (FIFO) queue; the input coming from the upstream data bus 62 and being stored in the data registers 510, 520 or 530, and the output being put on the downstream data bus 68 by the first data register 510.
  • the multiplexer 540 selects, depending on the number of data words stored in the pipeline 400, the source of the data word to be stored in the first data register 510.
  • the counter 410 keeps track of the number of data words stored in the pipeline 400.
  • the third data register 530 is only necessary when the frequency ratio between the upstream and downstream clock domains is greater than 2. When the frequency ratio is greater than 2, in some cases a data word can not be stored in the first data register 510 because there is no rising edge of the downstream clock. In this case, the two incoming data words are stored in the second and third data registers 520 and 530 of the pipeline 500.

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Abstract

L'invention concerne un procédé permettant d'optimiser une chaîne de traitement de données au moyen d'un protocole de transfert synchrone par adaptation de la fréquence de fonctionnement et du format de données entre un bloc d'amont, qui présente une fréquence de fonctionnement d'amont et un format de données d'amont, et un bloc d'aval, qui présente une fréquence de fonctionnement d'aval et un format de données d'aval. Le bloc d'amont génère un signal RTS d'amont et un signal d'horloge d'amont, et le bloc d'aval génère un signal RTS d'aval et un signal d'horloge d'aval. Le procédé de l'invention comprend les étapes consistant: à recevoir le signal RTS d'amont, le signal d'horloge d'amont, le signal RTS d'aval et le signal d'horloge d'aval; à générer un signal RTR d'adaptation d'amont lorsque des données sont prêtes à être reçues en provenance du bloc d'amont; à recevoir des données en provenance du bloc d'amont au format de données d'amont lorsque le signal RTS d'amont et le signal RTR d'adaptation d'amont sont actifs; à transformer les données du format de données d'amont au format de données d'aval; à générer un signal RTS d'adaptation d'aval lorsque des données sont prêtes à être envoyées au bloc d'aval; et à envoyer les données au bloc de données d'aval au format de données d'aval lorsque le signal RTR d'aval et le signal RTR d'adaptation d'aval sont actifs.
PCT/IB2004/001190 2003-01-16 2004-01-16 Procede et systeme de croisement de domaines d'horloge et d'adaptation de format au moyen de protocole de transfert synchrone WO2004063836A2 (fr)

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006137044A2 (fr) 2005-06-24 2006-12-28 Nxp B.V. Flot de donnees a synchronisation automatique entre des circuits de fabricants et consommateurs utilisant des adresses
US20080301351A1 (en) * 2007-06-04 2008-12-04 Samsung Electronics Co., Ltd Communication method of host apparatus capable of connecting with device by using wireless universal serial bus and wireless connection system including host apparatus and device
US8095719B2 (en) * 2009-05-07 2012-01-10 Ours Technology Inc. Data communication systems and bridges
US8102867B2 (en) * 2009-05-07 2012-01-24 Ours Technology Inc. Bridges and computing devices with bridges
US8161207B1 (en) * 2006-06-22 2012-04-17 Marvell International Ltd. Common block interface for data and control with handshake protocol
CN113726467A (zh) * 2021-07-29 2021-11-30 黎兴荣 电子产品数据传输方法、系统、存储介质及程序产品
CN114024893A (zh) * 2021-11-18 2022-02-08 群联电子股份有限公司 时钟重整电路模块、信号传输系统及信号传输方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5771359A (en) * 1995-10-13 1998-06-23 Compaq Computer Corporation Bridge having a data buffer for each bus master
US5978878A (en) * 1996-09-26 1999-11-02 Vlsi Technology Selective latency reduction in bridge circuit between two busses

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5771359A (en) * 1995-10-13 1998-06-23 Compaq Computer Corporation Bridge having a data buffer for each bus master
US5978878A (en) * 1996-09-26 1999-11-02 Vlsi Technology Selective latency reduction in bridge circuit between two busses

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
"EISA Specification Version 3.12 -- Paragraph 2.1: Signal Descriptions" 31 December 1992 (1992-12-31), BCPR SERVICES, INC. , XP002300649 page 16, line 13 - line 21 *
"PCI Local Bus Specification Revision 2.2 -- Chapter 2: Signal Definition" 18 December 1998 (1998-12-18), , XP002300650 page 7 page 11 *

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006137044A2 (fr) 2005-06-24 2006-12-28 Nxp B.V. Flot de donnees a synchronisation automatique entre des circuits de fabricants et consommateurs utilisant des adresses
WO2006137044A3 (fr) * 2005-06-24 2007-07-26 Nxp Bv Flot de donnees a synchronisation automatique entre des circuits de fabricants et consommateurs utilisant des adresses
US8543746B2 (en) 2005-06-24 2013-09-24 Nxp B.V. Self-synchronizing data streaming between address-based producer and consumer circuits
US8161207B1 (en) * 2006-06-22 2012-04-17 Marvell International Ltd. Common block interface for data and control with handshake protocol
US8443121B1 (en) 2006-06-22 2013-05-14 Marvell International Ltd. Common block interface for data and protocol with handshake
US20080301351A1 (en) * 2007-06-04 2008-12-04 Samsung Electronics Co., Ltd Communication method of host apparatus capable of connecting with device by using wireless universal serial bus and wireless connection system including host apparatus and device
US8386658B2 (en) * 2007-06-04 2013-02-26 Samsung Electronics Co., Ltd Communication method of host apparatus capable of connecting with device by using wireless universal serial bus and wireless connection system including host apparatus and device
US8095719B2 (en) * 2009-05-07 2012-01-10 Ours Technology Inc. Data communication systems and bridges
US8102867B2 (en) * 2009-05-07 2012-01-24 Ours Technology Inc. Bridges and computing devices with bridges
TWI426743B (zh) * 2009-05-07 2014-02-11 Ours Technology Inc 資料通信系統及橋接器
CN113726467A (zh) * 2021-07-29 2021-11-30 黎兴荣 电子产品数据传输方法、系统、存储介质及程序产品
CN114024893A (zh) * 2021-11-18 2022-02-08 群联电子股份有限公司 时钟重整电路模块、信号传输系统及信号传输方法

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