WO2004061604A2 - Optimisation de la frequence d'horloge d'un processeur dans un lecteur de disque dur visant a reduire au minimum la consommation d'energie et a maximiser les performances - Google Patents

Optimisation de la frequence d'horloge d'un processeur dans un lecteur de disque dur visant a reduire au minimum la consommation d'energie et a maximiser les performances Download PDF

Info

Publication number
WO2004061604A2
WO2004061604A2 PCT/US2003/041094 US0341094W WO2004061604A2 WO 2004061604 A2 WO2004061604 A2 WO 2004061604A2 US 0341094 W US0341094 W US 0341094W WO 2004061604 A2 WO2004061604 A2 WO 2004061604A2
Authority
WO
WIPO (PCT)
Prior art keywords
processor
clock
code
servo
current command
Prior art date
Application number
PCT/US2003/041094
Other languages
English (en)
Other versions
WO2004061604A3 (fr
Inventor
Thorsten Schmidt
Original Assignee
Matsushita Electric Industrial Co. Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/413,198 external-priority patent/US7089432B2/en
Priority claimed from US10/413,017 external-priority patent/US7072138B2/en
Application filed by Matsushita Electric Industrial Co. Ltd. filed Critical Matsushita Electric Industrial Co. Ltd.
Priority to AU2003300305A priority Critical patent/AU2003300305A1/en
Publication of WO2004061604A2 publication Critical patent/WO2004061604A2/fr
Publication of WO2004061604A3 publication Critical patent/WO2004061604A3/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3215—Monitoring of peripheral devices
    • G06F1/3221—Monitoring of peripheral devices of disk drive devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3268—Power saving in hard disk drive
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B21/00—Head arrangements not specific to the method of recording or reproducing
    • G11B21/02—Driving or moving of heads
    • G11B21/08—Track changing or selecting during transducing operation
    • G11B21/081—Access to indexed tracks or parts of continuous track
    • G11B21/083—Access to indexed tracks or parts of continuous track on discs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B5/00—Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor
    • G11B5/48—Disposition or mounting of heads or head supports relative to record carriers ; arrangements of heads, e.g. for scanning the record carrier to increase the relative speed
    • G11B5/54—Disposition or mounting of heads or head supports relative to record carriers ; arrangements of heads, e.g. for scanning the record carrier to increase the relative speed with provision for moving the head into or out of its operative position or across tracks
    • G11B5/55—Track change, selection or acquisition by displacement of the head
    • G11B5/5521—Track change, selection or acquisition by displacement of the head across disk tracks
    • G11B5/5526—Control therefor; circuits, track configurations or relative disposition of servo-information transducers and servo-information tracks for control thereof
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention relates to the design of hard disk drives to minimize power consumption while maintaining performance levels. More particularly, the present invention relates a technique for minimizing power consumption by one or more processors controlling the disk drive.
  • a hard disk drive assembly is a mass-storage device from which data may be read and/or written.
  • the hard disk drive includes one or more randomly accessible rotatable storage media, or disks upon which data is encoded.
  • the data is encoded as bits of information using magnetic field reversals grouped in tracks on the magnetic hard surface of rotating disks.
  • a transducer head supported by an actuator arm is used to read data from or write data to the disks.
  • a voice control motor (NCM) attached to the actuator controls positioning of the actuator, and thus the transducer head position over a disk. Data read from the disk or written to the disk is provided through circuitry to a processor.
  • NCM voice control motor
  • Servo position data read from the disk is processed by the processor, enabling the processor to provide servo current command signals to control the NCM for proper positioning of a transducer head relative to a disk
  • the system is typically set to operate at a low power level. With a low power, overall performance is typically sacrificed in return for maximizing battery life. For non-portable hard disk drives not requiring batteries, system power levels are not a significant issue and the system power levels can be set high to maximize performance.
  • the operation frequency, and thus power consumption can be linearly adjusted by reducing the clock rate. Adjusting both clock rate and system voltage level can produce approximately cubic reductions in power consumption.
  • the processor clock rate is set to facilitate a compromise between reducing power to maintain battery life and maintaining a desired level of system performance.
  • disk drive processor speed is changed during run time to optimize the trade-off between minimizing power consumption and maximizing performance.
  • Changing processor speed satisfies the general desire to keep the processor frequency low so that the power consumption is low, while maintaining some critical operations at a fast run time because they significantly affect system performance.
  • processor clock speed is modified such that different parts of code running on the processor execute at different speeds.
  • processor speed for executing certain code is related to how much the code affects performance of the drive.
  • Code that is critical to performance is set to run faster than code that is not critical to performance.
  • One example of critical code is the code that starts from the assertion of the servo interrupt until the output of the servo current control signal from the processor to the NCM controller.
  • the processor clock speed is maximized.
  • an ASIC containing the processor is selected which provides the ability to switch clock rates of the processor during processor run time.
  • critical code is the code processed in a bottleneck between when the disk drive processor receives a command to transfer data, and when the processor starts the execution of a seek command.
  • the seek command requires the actuator to move the head from the current track to a different track, and requires some time for the processor to generate, in part because the processor typically has to generate an appropriate destination from the transfer data command. This can result in a code bottleneck between the receipt of a transfer data command and start of the seek command.
  • Fig. 1 shows a block diagram of components of a hard disk drive configured to minimize power consumption in accordance with the present invention
  • Fig. 2 illustrates the subdivision of tracks programmed on a hard disk into servo sectors
  • Fig. 3 shows a timing diagram illustrating the time from the start of the servo interrupt to the sending of the current command
  • Fig. 4 shows a diagram illustrating the time from the start of the servo interrupt to the sending of the current command as well as the time from the sending of the current command to the end of the servo interrupt.
  • Fig. 1 shows a block diagram of components of a hard disk drive system configured to minimize power consumption in accordance with the present invention.
  • the hard disk drive includes a rotating disk 2 containing a magnetic medium for storing data in defined tracks. Data is written to or read from the storage medium using a transducer or read/write head 4 provided on an actuator
  • the actuator movement is controlled by a voice control motor (NCM) 8 made up of a magnet and a coil configured for receiving an external control signal.
  • NCM voice control motor
  • NCM driver 10 receives current command signals from a processor 12, enabling the NCM driver 10 to apply an amount of current to the coil of the NCM 8 to position the actuator 6 over a desired track of the rotating disk 2.
  • the disk 2 contains multiple tracks where data is stored.
  • the data is read from or written to the rotating disk 2 using the transducer head 4.
  • the analog data read is provided through a read/write (R/W) pre-amplifier 14.
  • the amplified read data is provided to the R/W channel 16, which includes circuitry to convert the data from analog to digital and decode the digital data to provide to the hard disk controller (HDC) 34.
  • the R/W channel 16 further converts data received from the HDC to be written from digital to analog for providing through the R/W preamps 14 to transducer head 4.
  • the data read includes servo data provided in digital form from the HDC 34 to the processor 12.
  • Servo data provided to the processor 12 includes information indicating track positioning of the transducer head 4 over the rotating disk 2.
  • the track positioning information indicates the track the transducer head 4 is placed over, as well as any misalignment of the transducer head 4 relative to a track.
  • Servo data is recorded periodically along each track on the rotating disk 4 between other non-servo data.
  • the real-time servo control algorithm is typically run on an interrupt basis on the processor, with the interrupt being triggered, for example by servo demodulation hardware typically provided in the HDC 34.
  • the interrupt causes the processor to cease other functions it is performing and deal with the servo position data.
  • the processor 12 determines track misalignment and computes a current command which is sent to the NCM driver 10 to correct for the track misalignment.
  • This interrupt is typically initiated approximately when all the servo position information contained in the servo wedge is read into the ASIC 20. It is well known that reducing the time between the position information written on the disk and the subsequent current command improves servo performance. Thus, enhancing the processor performance during the time from the start of the interrupt to the sending of the current command at the expense of additional power consumption is typically desirable.
  • the processor 12 executes code which generates a target position consistent with the desired read or write data and sends a request to the servo code to move from the current position to the new target position.
  • the request to move the head from one location to another is typically called a seek. Because it improves performance to minimize the time from the receipt of the read or write command to the start of the seek, enhancing processor performance during execution of this code at the expense of additional power consumption is typically desirable.
  • Processor 12 executes instructions acquired from a stored control program to control disk drive functions.
  • the control program is embedded in flash memory, or other non-volatile memory and then either executed directly, or loaded into a random access memory RAM 19 connected to the processor 12 and executed.
  • Various firmware routines are stored in memory locations for controlling the operation of the actuator 7 and spindle motor 30.
  • control programs include the instructions the processor 12 executes, and tables, parameters or arguments used during the execution of these programs.
  • the processor 12 also communicates with the HDC 34 which has access to components external to the hard disk drive system through an advanced technology attachment (ATA) interface bus 20.
  • ATA advanced technology attachment
  • the ATA bus 20 is also referred to as an integrated drive electronics (IDE) bus, and although specifically shown as an ATA bus, may be another type of external component interface, such as an SCSI, in accordance with the present invention.
  • IDE integrated drive electronics
  • the HDC 34 further provides access to additional DRAM memory 36. Control programs for the processor may reside in DRAM 36, or in RAM 19 directly accessible by the processor.
  • ASICs application specific integration circuits
  • FIG. 1 the ASIC 26 integrates the processor 12, RAM 19, R/W channel 16, HDC 34, DRAM 36, and ATA interface bus 20 all onto a single chip.
  • the chip for disk drive control is often referred to as a system on a chip (SOC).
  • SOC system on a chip
  • components such as the NCM driver 10 and the processor 12 are shown to be included on the single ASIC 26, it is understood that the present invention contemplates that the components may similarly be included as separate non-integrated circuits, or the processing functions can be distributed to other components such as the HDC 34.
  • a single processor 12 is shown, it is understood that the functions of processor 12 can be divided among multiple processors when desirable.
  • a crystal oscillator 30 is provided external to the ASIC 26. Although a crystal oscillator is shown, other types of oscillators may be used.
  • An oscillator input signal is typically provided to one or more phase locked loops (PLLs) on an ASIC.
  • PLLs include frequency dividers to convert the frequency from the oscillator to the desired frequency for individual components on the ASIC. For the ASIC 26 illustrated in Fig. 1, four such PLLs 21 -24 are shown.
  • the PLLs 21-23 are shown providing a clock signal to the processor 12. Note that although the PLLs 21-23 are shown connected directly to the processor 12, many configurations are possible. For instance, the PLLs can be provided indirectly through the HDC 34 to the processor 12. The HDC 34 can then include a multiplexer controlled by the processor to select one of the PLL outputs to provide to the processor 12 at a time. In accordance with the present invention, code executing on the processor can select one of the desired clock signals depending on the frequency of operation desired. Code stored in the RAM 19, or other memory if present, selects different clock signals as desired.
  • a single PLL such as PLL 21, could be configured to provide the clock signal to the processor 12, with control signals provided to the PLL 21 to control its frequency division to selectively provide different clock signal frequencies to the processor 12.
  • Multiple PLLs may, however, be desirable because of the time period required for a PLL to stabilize after its frequency divider is reset.
  • the clock signal frequency of the processor 12 is varied during processor run time to minimize power consumption, while maximizing performance.
  • clock frequency of the processor is reduced, power provided to the processor is also significantly reduced.
  • clock speed of the processor 12 is not reduced when performance critical code is executed by the processor 12.
  • the performance critical code where clock speed is maximized is code starting from initial receipt of a servo interrupt until code is executed by the processor 12 causing a resulting current command signal to be sent to the NCM driver 10.
  • the increased power consumption of the processor 12 from the start of the interrupt to the sending of the current command is considered desirable because it reduces phase loss due to control delays, improving overall servo performance.
  • Fig. 2 illustrates a number of data tracks 51-53 programmed on a rotating disk.
  • the tracks 51-53 are subdivided, such as between lines 61 and 62, to form servo sectors, such as sector 63, where servo data is written on a track.
  • the servo sectors such as sector 63, occur periodically around the tracks 51-53.
  • the servo data read from servo sectors is received periodically, with equal time periods between reception of the servo sector bursts.
  • the servo wedges may not extend linearly from inner diameter (ID) to outer diameter (OD), but may be curved slightly in order to adjust for the trajectory of the head as it sweeps across the disk.
  • Fig. 3 shows a timing diagram illustrating a performance critical portion of the servo interrupt, namely the time from the start of the interrupt to the sending of the current command.
  • Different such critical servo interrupt portions are executed periodically during time periods 71 and 72.
  • the processor 12 typically receives a servo interrupt associated with a servo sector every time period ⁇ .
  • the period ⁇ is typically in the range of 20 to 200 ⁇ sec, and is influenced by the number of tracks per inch (TPI) which are recorded on the disk.
  • TPI tracks per inch
  • some systems can have multiple servo interrupts for each servo sector, using a commonly known concept called multi-rate control.
  • the processor 12 executes other non- servo interrupt code.
  • a first fast clock signal can be provided to the processor 12 between the start of the servo interrupt and the sending of the current command to improve disk drive performance, while a second slower clock signal can be provided to processor 12 when the rest of the servo interrupt code is executing to minimize power consumption by the processor 12.
  • the faster clock reduces the time between the position data written on the disk passing under the head, and output of the servo control to the actuator. This means that phase loss due to control delay is reduced, a factor in improving servo performance.
  • the clock can run slower at other times, including potentially the rest of the servo interrupt.
  • Fig. 4 is a timing diagram that divides the servo interrupt into two sections.
  • the first part, 81 illustrates the servo code execution time from the start of the interrupt to the sending of the current command. This is timing critical code and includes determining position and computing the current command signal.
  • the second part, 82 illustrates the servo code execution time from the output of the current command signal from the processor to the end of the servo interrupt. Processor speed is essential during the first part 81, but processor speed during the second part 82 is not as essential. Thus, after servo current command is sent from processor 12 to the NCM driver 10, processor speed is reduced in one embodiment of the present invention to minimize power consumption during the rest of the interrupt 82.
  • processor speed is again increased.
  • Code running as part of the interrupt increases and decreases the processor clock frequency as appropriate.
  • the interrupt portion 81 is shown as approximately one quarter of the total servo interrupt, the relative time in portion 81 and 82 can vary significantly.
  • the portion 81 accounts for a significant phase loss in the control system at the servo open loop crossover frequency (approximately 1 to 5 degrees), so increasing clock speed during the portion 81 provides a significant performance improvement with only a small increase in power.
  • processor power consumption is linearly reduced.
  • two or more different clock speeds may be used to optimize the tradeoff between minimizing power consumption and maximizing performance.
  • the processor speed is maximized when performance critical code is executed that is, in time, between the receipt of a read or write command through the host interface, such as the ATA interface, to code that is executed to cause a seek request to be sent.
  • performance critical code is executed that is, in time, between the receipt of a read or write command through the host interface, such as the ATA interface, to code that is executed to cause a seek request to be sent.
  • One aspect of the disk drive performance is to reduce the time between the receipt of the read or write command and the completion of such a command. The time from the receipt of the command and the start of the seek is a critical component of this overall time and thus performance. Consequently, increasing the processor clock frequency during the execution of this code can provide a significant increase in disk drive performance.
  • the system in accordance with the present invention contemplates use of a very low clock speed for a sleep mode when the drive is basically inoperative, hi accordance with the present invention, it is contemplated that clock signals with faster speeds be provided to the processor during processing of some code when design considerations dictate that speed is preferable over processor power consumption.
  • the present invention is described for use with hard disk drives for recording in magnetic media, it is understood that principles in accordance with the present invention can be used with optical disk drives.

Abstract

Selon cette invention, la fréquence d'horloge du processeur dans un lecteur de disque dur est surveillée pendant la durée d'exécution afin que le compromis entre la réduction au minimum de la consommation d'énergie et la maximisation des performances soit optimisé. La fréquence d'horloge du processeur est augmentée pendant le traitement de codes plus critiques de performances pour le système de lecteur de disque tandis que la fréquence d'horloge du processeur est réduite pendant le traitement de codes moins critiques de performances. On peut citer, comme exemple de code plus critique pour lequel la fréquence d'horloge du processeur est augmentée, le code exécuté par le processeur depuis le début d'une servo interruption jusqu'à l'obtention de la servo commande de courant produite du processeur à l'unité de commande de l'actionneur. Pour modifier la fréquence d'horloge du processeur, un ASIC renfermant le processeur de lecteur de disque est sélectionné, lequel permet de commuter les fréquences d'horloge du processeur pendant la durée d'exécution.
PCT/US2003/041094 2002-12-27 2003-12-22 Optimisation de la frequence d'horloge d'un processeur dans un lecteur de disque dur visant a reduire au minimum la consommation d'energie et a maximiser les performances WO2004061604A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003300305A AU2003300305A1 (en) 2002-12-27 2003-12-22 Optimizing processor clock frequency in a hard disk drive to minimize power consumption while maximizing performance

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US43668002P 2002-12-27 2002-12-27
US43675202P 2002-12-27 2002-12-27
US60/436,752 2002-12-27
US60/436,680 2002-12-27
US10/413,198 US7089432B2 (en) 2002-12-27 2003-04-14 Method for operating a processor at first and second rates depending upon whether the processor is executing code to control predetermined hard drive operations
US10/413,198 2003-04-14
US10/413,017 US7072138B2 (en) 2002-12-27 2003-04-14 Apparatus for optimizing processor clock frequency in a hard disk drive to minimize power consumption while maximizing performance
US10/413,017 2003-04-14

Publications (2)

Publication Number Publication Date
WO2004061604A2 true WO2004061604A2 (fr) 2004-07-22
WO2004061604A3 WO2004061604A3 (fr) 2004-12-23

Family

ID=32719476

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/041094 WO2004061604A2 (fr) 2002-12-27 2003-12-22 Optimisation de la frequence d'horloge d'un processeur dans un lecteur de disque dur visant a reduire au minimum la consommation d'energie et a maximiser les performances

Country Status (2)

Country Link
AU (1) AU2003300305A1 (fr)
WO (1) WO2004061604A2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1746603A3 (fr) * 2005-07-22 2010-04-07 STMicroelectronics, Inc. Partitionnement des systèmes électroniques pour disque dur

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5586308A (en) * 1994-10-19 1996-12-17 Advanced Micro Devices, Inc. Clock control unit responsive to a power management state for clocking multiple clocked circuits connected thereto
US5691948A (en) * 1995-06-08 1997-11-25 Fujitsu Limited Memory apparatus

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5586308A (en) * 1994-10-19 1996-12-17 Advanced Micro Devices, Inc. Clock control unit responsive to a power management state for clocking multiple clocked circuits connected thereto
US5691948A (en) * 1995-06-08 1997-11-25 Fujitsu Limited Memory apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1746603A3 (fr) * 2005-07-22 2010-04-07 STMicroelectronics, Inc. Partitionnement des systèmes électroniques pour disque dur

Also Published As

Publication number Publication date
AU2003300305A1 (en) 2004-07-29
AU2003300305A8 (en) 2004-07-29
WO2004061604A3 (fr) 2004-12-23

Similar Documents

Publication Publication Date Title
US8111476B2 (en) Disk drive spin control
US7089432B2 (en) Method for operating a processor at first and second rates depending upon whether the processor is executing code to control predetermined hard drive operations
US20050174678A1 (en) Stepping power consumption levels in a hard disk drive to maximize performance while minimizing power consumption
US6657811B1 (en) Mobile device and disk drive having a seek current profile responsive to an environment signal
US6122131A (en) Adaptively-controlled disk drive assembly
US8433937B1 (en) Automated transitions power modes while continuously powering a power controller and powering down a media controller for at least one of the power modes
KR101340715B1 (ko) 데이터 저장 드라이브, 데이터 처리 시스템 및 데이터 저장 드라이브의 구동 방법
US6067206A (en) Method and apparatus to compensate for servo wedge rotational offset after a head switch
JP2578297B2 (ja) 直接アクセス記憶装置とその動作方法
US20050144491A1 (en) Variable power consumption levels in a hard disk drive
US7072138B2 (en) Apparatus for optimizing processor clock frequency in a hard disk drive to minimize power consumption while maximizing performance
JPH0973705A (ja) 磁気記録装置
JP2002298307A (ja) データ記憶装置、書き込み電流制御回路および書き込み電流の制御方法
US20090015960A1 (en) Magnetic disk drive and magnetic disk medium
US6785080B1 (en) Method and apparatus for providing a variable rate oversampling digital filter for resonance compensation in disk drive servo control systems
US7468590B1 (en) Method and apparatus for initializing operation of a disk drive
US6332196B1 (en) Disk storage apparatus and power supply control method for the same
JPH09288804A (ja) 磁気記録装置の記録電流制御回路及び方法
WO2004061604A2 (fr) Optimisation de la frequence d'horloge d'un processeur dans un lecteur de disque dur visant a reduire au minimum la consommation d'energie et a maximiser les performances
US6747832B2 (en) Disk apparatus and head position control method
JPH11317035A (ja) ディスク記憶装置及び同装置に適用するヘッド位置決め制御システム
CN108665908B (zh) 磁盘装置、控制器以及寻道方法
US20100268972A1 (en) Method and apparatus for controlling clock frequency
JPH06342345A (ja) ディスクドライブ及び磁気ディスクのフォーマット方法
JP2003108314A (ja) データ記憶装置、コンピュータ装置、書き込みデータの処理装置および書き込みデータの処理方法

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): BW GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 20038A9562X

Country of ref document: CN

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP

WWW Wipo information: withdrawn in national office

Country of ref document: JP