WO2004055991A1

WO2004055991A1 - Ad conversion arrangement

Info

Publication number: WO2004055991A1
Application number: PCT/IB2003/005513
Authority: WO
Inventors: Wilfred A. M. Snijders
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2002-12-17
Filing date: 2003-11-26
Publication date: 2004-07-01
Also published as: AU2003282295A1

Abstract

AD-conversion arrangement comprising a plurality of ADC-subcircuits which receive the analog input signal in parallel and whose digital outputs are multiplexed to a common digital output. The ADC-subcircuits are switched successively and cyclically between sample mode and hold- and conversion mode. The ADC-subcircuits may be operated sub-Nyquist because aliasing products are cancelled by the multiplexing of the digital outputs.

Description

AD conversion arrangement

The invention relates to an analog to digital (AD) conversion arrangement. On AD conversion arrangements increasingly higher standards with respect to resolution and sample rates are set. For example, state of the art AD-converters, such as the converter AD9433 of Analog Devices, may operate at sample rates up to 125 MHz with a resolution of 12 bits per sample. With such AD-converters signals with a baseband up to about 60 MHz may conveniently be converted without aliasing problems. It is well known that the Nyquist- frequency of the converter, i.e. half its sample rate, should be higher than the highest baseband frequency in order to avoid folding of upper sideband frequencies, generated by the sampling process, into the baseband (aliasing). However, for many applications the state of the art converters are not appropriate. For instance, for the digitization of GSM-telephony signal bands nowadays 12-bit DA-converters with a maximum sample rate of 500 MHz are preferred. Another example is the transmission of a large plurality of TV-signals through glass- fiber cables. Nowadays for this purpose the whole band of TV-signals from 100 MHz to 800 MHz is applied to an analog laser to generate the modulated light-beam radiated through the fiber. In order to avoid intermodulation between the TV-signals, a perfectly linear analog laser is required and this is a very expensive device. A more suitable solution would be to first convert the whole band of TV signals into a 12 bits digital signal with 2 GHz sample rate and then apply the 24 bit/sec bit stream to a digital laser.

It is the object of the present invention to provide an analog to digital conversion arrangement with substantially increased maximum sample rate, and the analog to digital conversion arrangement according to the invention is therefore characterized in that the arrangement comprises a plurality of ADC-subcircuits, each of said plurality of ADC- subcircuits comprising a signal input connected to a common input for receiving an analog signal to be converted, a switch-signal input connected to a clock-controlled switch-pulse generator for switching the ADC-subcircuits in cyclical succession between a sample mode and a hold- and converting mode and a digital signal output, and that an output multiplexer controlled by said switch-pulse generator is provided for coupling the output signals of the ADC-subcircuits to a common output cyclically and synchronously with said switching of the ADC-subcircuits. The AD conversion arrangement of the present invention has the ability to convert at a high sampling rate while using ADC-subcircuits that have a relatively low sampling rate. When f_s represents the desired sampling rate that is required to properly convert the analog input signal and when M is the number of ADC-subcircuits used in the arrangement, the sampling rate of each individual ADC-subcircuit is only f_s M. This means that each of the individual ADC-subcircuits operates sub-Nyquist and consequently produces aliasing distortion in its output signal. The invention is based on the recognition that, by multiplexing the digital output signals of the respective ADC-subcircuits, the aliasing distortions of these output signals substantially cancel each other out. For a proper cancellation of the aliasing distortion it is of importance that the sampling instants of the successive ADC-subcircuits are spaced at equidistant moments, which are l/f_s apart from each other. This means that the ADC-subcircuits have to be switched by clock-phases that are equally shifted with respect to each other, whereby the sampling moment of each of the ADC-subcircuits is l/f_s apart from the sampling moment of the previous ADC-subcircuit in the sampling succession.

It has to be noted that it is already known per se from US-patent 4,611,194 to successively, but not cyclically, operate a plurality of ADC-subcircuits that receive the input signal in parallel. However, this arrangement is not clock-controlled. The input signal consists of irregularly occurring pulses and, upon the occurrence of such a pulse, each of the ADC-subcircuits determines the digital value of the pulse at only one sampling instant while the sampling instants of all ADC-subcircuits are regularly spaced apart from each other. Subsequently the calculated digital values are compared to determine the peak value or the mean value of the pulse. Therefore this known arrangement does not serve to convert the analog pulses to their digital equivalents. From applicants' prior European patent application 02079885.6 (NL021141) a real clock-controlled analog to digital converter is known that contains a plurality of sample and hold circuits that receive the analog input signal in parallel. The sample and hold circuits operate cyclically to sample the input signal and the analog hold level is subsequently multiplexed to a plurality of ADC-subcircuits each of which generate a part of the bits of the digital output sample. Consequently each of the sample and hold circuits and each of the ADC-subcircuits operates at the required sample rate of the digital output signal while the bit-resolution of the digital output signal is equal to the sum of the bit resolutions of the ADC-subcircuits. In contradistinction, in the analog to digital conversion arrangement of the present invention each of the ADC-subcircuits should have the required bit resolution (e.g. 12 bits) and the sample rate of the arrangement is equal to the sample rate of each of the ADC- subcircuits multiplied by the number of ADC-subcircuits.

One complete cycle carried out by each ADC-subcircuit consists of a sampling time during which a new sample of the analog input signal is taken, a conversion time during which the digital value of the analog sample is calculated and a read-out time during which the calculated digital value is read out to the common digital output. Preferably the analog to digital conversion arrangement according to the present invention is characterized in that said output multiplexer couples the output signal of any ADC-subcircuit to the common output during the sample mode of said ADC-subcircuit. This leaves maximum time for the evaluation of the analog sample and the calculation of the digital value during the conversion time.

In practice the connections between the clock-controlled switch-pulse generator and the switch inputs of the various ADC-subcircuits may be different in layout, so that the switch pulses arrive at the ADC-subcircuits with different delay. This implies that the period (theoretically l/f_s) between the sampling instants of two successive ADC-subcircuits is not uniform, as a result of which the aliasing distortion generated by the ADC-subcircuits is not completely cancelled. This problem may be solved by a clock-controlled master switch in the common input to the analog signal inputs of the ADC-subcircuits for advancing the sampling instants of all the ADC-subcircuits thereby making sure that the actual sampling instants of these ADC-subcircuits are uniformly spaced. This measure has already been proposed per se in applicants' above-mentioned prior-filed European patent application 02079885.6 (NL021141), which is incorporated herein by reference.

The analog to digital conversion arrangement of the present invention may be implemented in a single monolithic integrated circuit. However, the invention is also useful to construct a high rate analog to digital arrangement by means of a plurality of commercially available lower rate ADC-chips in which case the arrangement comprises a plurality of analog to digital conversion monolithic integrated circuits, each of said monolithic integrated circuits comprising one ADC-subcircuit.

The invention will be described with reference to the accompanying figures. Herein shows:

Fig. 1 a circuit diagram of an AD conversion arrangement according to the present invention and Fig. 2 a timing diagram for explaining the operation of the AD conversion arrangement of Fig. 1.

The AD conversion arrangement of Fig. 1 shows a plurality of M ADC- subcircuits Ai to A_M- Each of the ADC-subcircuits has an analog signal input Ii to IM, a switch-signal input Si to S and a digital signal output Oi to O_M. A common analog signal input I is connected through a master-switch W, whose operation will be explained afterwards, to each of the inputs Ii to I of the ADC-subcircuit. The switch-signal inputs Si to S_M are connected to a switch-pulse generator P, which is controlled by a clock-pulse supplied by a clock-pulse generator G. The digital signal outputs Oi to O_M are connected to a clock-pulse controlled multiplexer Q that multiplexes the digital outputs of the ADC- subcircuit to a common digital output R.

In Fig. 2 curve C_\ shows the switch-signal that is generated in the switch-pulse generator P and that is applied to the switch-signal input S₁ of the ADC-subcircuit Ai.

Similarly other curves C₂...C_M of this figure show the switch signals that are applied to the switch-signal inputs of the ADC-subcircuits A₂ to A_M respectively. In this figure the unavoidable slopes of the switch-signals are drawn as steep edges for clarity reasons. Each of the switch-signals is high during the sampling time τ_s and low during a hold- and conversion time τ_c = (M-l)τ_s. Consequently the total period of the signal equals τ_s+ τ_c = M.τ_s and the sample rate of the particular ADC-subcircuit is 1/M.τ_s. When the switch-signal is high the ADC-subcircuit is in its sample mode during which the value of the analog input signal is loaded in a sample and hold capacitance of the ADC-subcircuit. The sampling time ends at the sampling instant and it is the value of the input signal at this instant that is held in the said capacitance during the entire hold and conversion time.

During the hold and conversion time τ_c = (M-l)τ_s, when the switch signal is low, the analog signal value at the sample instant is evaluated and converted into a corresponding digital value with the required bit-resolution, e.g. 12 bits. Subsequently, when the AD-converter output is stable, the digital value is outputted through the digital signal output of the ADC-subcircuit and through the multiplexer Q applied to the common digital output R. The other ADC-subcircuits operate in exactly the same way be it that the operation of each DC-subcircuit is shifted in time by τ_s with respect to its predecessor.

The multiplexer Q is controlled by the switch pulse generator P through a control lead S_Q SO that the outputs of the ADC-subcircuits A_\ ...AM are cyclically and synchronously connected to the common output R. The outputting of the digital value to the common output R may take place during the last part of the hold and conversion time of the ADC-subcircuit, but preferably this is done during the next sampling time of the subcircuit because this gives the subcircuit maximal time to achieve a stable digital output signal. It may be clear from the above that with the described arrangement the digital signal at the output R contains a new digital value after each sampling time τ_s. Therefore the sample rate of the arrangement is l/τ_s, which is a factor M higher than the sample rate 1/Mτ_s of each individual ADC-subcircuit. The baseband of the analog input signal should be smaller than the Nyquist frequency fs/2 = l/2τ_s however usually the baseband of the analog input signal will be broader than the Nyquist frequency fs/2M = l/2Mτ_s of the ADC- subcircuits. This means that the ADC-subcircuits will produce aliasing distortion, but these aliasing distortions of the ADC-subcircuits cancel each other out in the output R of the multiplexer. For a proper cancellation thereof it is of importance that the sampling instants of the subcircuits are spaced at equidistant moments. This requires a careful layout of the circuitry of the switch-pulse generator, of the subcircuits and of the interconnections between the switch pulse generator and the subcircuits.

To assist in making the sampling instants of the subcircuits more equidistant, the master switch W is included in the arrangement of Fig. 1. The master switch is controlled by the waveform Cw of Fig. 2 generated by the switch-pulse generator P. The switch W is open when the waveform Cw is low and closed when this waveform is high. The master switch operates in series with the sample and hold switches of the ADC-subcircuits and, because it opens just before the end of the sampling time of each of the subcircuits, its effect is that it advances the sampling instant of the subcircuits, whereby any unequal distances between the sampling instants of the subcircuits are replaced by the regularly spaced sampling instants generated by the master switch.

Claims

CLAIMS :

1. AD-conversion arrangement characterized in that the arrangement comprises a plurality of ADC-subcircuits (A^ ..A_M), each of said plurality of ADC-subcircuits comprising a signal input (Iι ...I_M) connected to a common input (I) for receiving an analog signal to be converted, a switch-signal input (Si ...S_M) connected to a clock-controlled switch-pulse generator (P) for switching the ADC-subcircuits in cyclical succession between a sample mode and a hold- and converting mode and a digital signal output (Oi ...O_M), and that an output multiplexer (Q) controlled by said switch-pulse generator (P) is provided for coupling the output signals of the ADC-subcircuits (Ai ...A_M) to a common output (R) cyclically and synchronously with said switching of the ADC-subcircuits.

2. An AD-conversion arrangement as claimed in claim 1 characterized in that said output multiplexer (Q) couples the output signal of any ADC-subcircuit (Ai ...A_M) to the common output (R) during the sample mode of said ADC-subcircuit.

3. An AD-conversion arrangement as claimed in claim 1 characterized by a clock-controlled master switch (W) in the common input to the analog signal inputs of the ADC-subcircuits (Ai ...A_M) for advancing the sampling instants of all the ADC-subcircuits.

4. An AD-conversion arrangement as claimed in claim 1 characterized in that the arrangement comprises a plurality of analog to digital conversion monolithic integrated circuits, each of said monolithic integrated circuits comprising one ADC-subcircuit.