WO2004055665A1 - Procede de division entiere ou de reduction modulaire securise contre les attaques a canaux caches - Google Patents
Procede de division entiere ou de reduction modulaire securise contre les attaques a canaux caches Download PDFInfo
- Publication number
- WO2004055665A1 WO2004055665A1 PCT/FR2003/003681 FR0303681W WO2004055665A1 WO 2004055665 A1 WO2004055665 A1 WO 2004055665A1 FR 0303681 W FR0303681 W FR 0303681W WO 2004055665 A1 WO2004055665 A1 WO 2004055665A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- division
- modular reduction
- random number
- bits
- during
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/535—Dividing only
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/002—Countermeasures against attacks on cryptographic mechanisms
- H04L9/003—Countermeasures against attacks on cryptographic mechanisms for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/30—Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy
- H04L9/3006—Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy underlying computational problems or public-key parameters
- H04L9/302—Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy underlying computational problems or public-key parameters involving the integer factorization problem, e.g. RSA or quadratic sieve [QS] schemes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/72—Indexing scheme relating to groups G06F7/72 - G06F7/729
- G06F2207/7219—Countermeasures against side channel or fault attacks
- G06F2207/7223—Randomisation as countermeasure against side channel attacks
- G06F2207/7233—Masking, e.g. (A**e)+r mod n
- G06F2207/7238—Operand masking, i.e. message blinding, e.g. (A+r)**e mod n; k.(P+R)
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/72—Indexing scheme relating to groups G06F7/72 - G06F7/729
- G06F2207/7219—Countermeasures against side channel or fault attacks
- G06F2207/7223—Randomisation as countermeasure against side channel attacks
- G06F2207/7257—Random modification not requiring correction
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/04—Masking or blinding
Definitions
- -n ⁇ is the complement to 1 (also called negation) 10 ( of the variable ⁇ .
- TRUE is a constant, equal to 1 in an example.
- lsb (a) is the least significant bit of the number -a, also called least significant bit of a.
- the random number p can be modified each time the process is executed, or simply after a number
- the result of the whole division carried out. with. the number masked in the form a + b * p is equal to a div b + p.
- we remove from the result of the whole division the contribution made by the random number p to find the expected result of the whole division on the number a, i.e. a div b .
- the result of the operation (a + b * p) mod b is equal to a mod b, expected result of the modular reduction- on the number a. -
- the invention also relates to an electronic component comprising means for implementing a method according to the invention, as described above.
- Means of Calculation programmed include multiple registers for storing the numbers a and b.
- the invention relates to a smart card comprising a component having the characteristics described above.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Analysis (AREA)
- Computational Mathematics (AREA)
- Computing Systems (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Computer Security & Cryptography (AREA)
- Signal Processing (AREA)
- Computer Networks & Wireless Communication (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Storage Device Security (AREA)
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/537,300 US7639796B2 (en) | 2002-12-11 | 2003-12-11 | Method for secure integer division or modular reduction against hidden channel attacks |
EP03813170A EP1579312A1 (fr) | 2002-12-11 | 2003-12-11 | Procede de division entiere ou de reduction modulaire securise contre les attaques a canaux caches |
AU2003296823A AU2003296823A1 (en) | 2002-12-11 | 2003-12-11 | Method for secure integer division or modular reduction against hidden channel attacks |
JP2004559820A JP4378480B2 (ja) | 2002-12-11 | 2003-12-11 | 隠れたチャネル攻撃に対して安全に整数除算またはモジュラ換算する方法 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR02/15623 | 2002-12-11 | ||
FR0215623A FR2848753B1 (fr) | 2002-12-11 | 2002-12-11 | Procede de division entiere ou de reduction modulaire securise contre les attaques a canaux caches |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2004055665A1 true WO2004055665A1 (fr) | 2004-07-01 |
Family
ID=32338660
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/FR2003/003681 WO2004055665A1 (fr) | 2002-12-11 | 2003-12-11 | Procede de division entiere ou de reduction modulaire securise contre les attaques a canaux caches |
Country Status (7)
Country | Link |
---|---|
US (1) | US7639796B2 (fr) |
EP (1) | EP1579312A1 (fr) |
JP (1) | JP4378480B2 (fr) |
CN (1) | CN1723436A (fr) |
AU (1) | AU2003296823A1 (fr) |
FR (1) | FR2848753B1 (fr) |
WO (1) | WO2004055665A1 (fr) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11411713B2 (en) * | 2019-05-03 | 2022-08-09 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Masking method and system for cryptography |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2838210B1 (fr) * | 2002-04-03 | 2005-11-04 | Gemplus Card Int | Procede cryptographique protege contre les attaques de type a canal cache |
FR2847402B1 (fr) * | 2002-11-15 | 2005-02-18 | Gemplus Card Int | Procede de division entiere securise contre les attaques a canaux caches |
FR2895609A1 (fr) * | 2005-12-26 | 2007-06-29 | Gemplus Sa | Procede cryptographique comprenant une exponentiation modulaire securisee contre les attaques a canaux caches, cryptoprocesseur pour la mise en oeuvre du procede et carte a puce associee |
FR2897964B1 (fr) * | 2006-02-28 | 2017-01-13 | Atmel Corp | Procede de calcul numerique incluant la division euclidienne |
US8280041B2 (en) * | 2007-03-12 | 2012-10-02 | Inside Secure | Chinese remainder theorem-based computation method for cryptosystems |
JP4603022B2 (ja) * | 2007-08-02 | 2010-12-22 | 株式会社スクウェア・エニックス | 暗号化データ作成装置、および暗号化データ作成プログラム |
US8553877B2 (en) * | 2007-10-01 | 2013-10-08 | Blackberry Limited | Substitution table masking for cryptographic processes |
TWI517655B (zh) * | 2013-05-23 | 2016-01-11 | 晨星半導體股份有限公司 | 密碼裝置以及密鑰保護方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0682327A2 (fr) * | 1994-05-09 | 1995-11-15 | Yeda Research And Development Company, Ltd. | Méthode et dispositif pour variantes économiques en mémoire de schémas de chiffrage et d'identification à cléf publique, pour application aux cartes à IC |
DE19963407A1 (de) * | 1999-12-28 | 2001-07-12 | Giesecke & Devrient Gmbh | Tragbarer Datenträger mit Zugriffsschutz durch Nachrichtenverfremdung |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5077793A (en) * | 1989-09-29 | 1991-12-31 | The Boeing Company | Residue number encryption and decryption system |
-
2002
- 2002-12-11 FR FR0215623A patent/FR2848753B1/fr not_active Expired - Fee Related
-
2003
- 2003-12-11 US US10/537,300 patent/US7639796B2/en not_active Expired - Fee Related
- 2003-12-11 JP JP2004559820A patent/JP4378480B2/ja not_active Expired - Lifetime
- 2003-12-11 EP EP03813170A patent/EP1579312A1/fr not_active Withdrawn
- 2003-12-11 CN CN200380105308.2A patent/CN1723436A/zh active Pending
- 2003-12-11 WO PCT/FR2003/003681 patent/WO2004055665A1/fr active Application Filing
- 2003-12-11 AU AU2003296823A patent/AU2003296823A1/en not_active Abandoned
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0682327A2 (fr) * | 1994-05-09 | 1995-11-15 | Yeda Research And Development Company, Ltd. | Méthode et dispositif pour variantes économiques en mémoire de schémas de chiffrage et d'identification à cléf publique, pour application aux cartes à IC |
DE19963407A1 (de) * | 1999-12-28 | 2001-07-12 | Giesecke & Devrient Gmbh | Tragbarer Datenträger mit Zugriffsschutz durch Nachrichtenverfremdung |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11411713B2 (en) * | 2019-05-03 | 2022-08-09 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Masking method and system for cryptography |
Also Published As
Publication number | Publication date |
---|---|
JP2006509261A (ja) | 2006-03-16 |
JP4378480B2 (ja) | 2009-12-09 |
FR2848753B1 (fr) | 2005-02-18 |
US20060023873A1 (en) | 2006-02-02 |
AU2003296823A1 (en) | 2004-07-09 |
EP1579312A1 (fr) | 2005-09-28 |
CN1723436A (zh) | 2006-01-18 |
US7639796B2 (en) | 2009-12-29 |
FR2848753A1 (fr) | 2004-06-18 |
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