WO2004053926A3 - A method for depositing a metal layer on a semiconductor interconnect structure - Google Patents
A method for depositing a metal layer on a semiconductor interconnect structure Download PDFInfo
- Publication number
- WO2004053926A3 WO2004053926A3 PCT/EP2003/050958 EP0350958W WO2004053926A3 WO 2004053926 A3 WO2004053926 A3 WO 2004053926A3 EP 0350958 W EP0350958 W EP 0350958W WO 2004053926 A3 WO2004053926 A3 WO 2004053926A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- depositing
- interconnect structure
- liner layer
- metal layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76844—Bottomless liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76865—Selective removal of parts of the layer
Abstract
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU2003300263A AU2003300263A1 (en) | 2002-12-11 | 2003-12-08 | A method for depositing a metal layer on a semiconductor interconnect structure |
JP2004558112A JP4767541B2 (en) | 2002-12-11 | 2003-12-08 | Method for depositing a metal layer on a semiconductor interconnect structure |
EP03799543A EP1570518A2 (en) | 2002-12-11 | 2003-12-08 | A method for depositing a metal layer on a semiconductor interconnect structure |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/318,605 US6949461B2 (en) | 2002-12-11 | 2002-12-11 | Method for depositing a metal layer on a semiconductor interconnect structure |
US10/318,605 | 2002-12-11 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2004053926A2 WO2004053926A2 (en) | 2004-06-24 |
WO2004053926A3 true WO2004053926A3 (en) | 2004-11-25 |
Family
ID=32506404
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2003/050958 WO2004053926A2 (en) | 2002-12-11 | 2003-12-08 | A method for depositing a metal layer on a semiconductor interconnect structure |
Country Status (8)
Country | Link |
---|---|
US (1) | US6949461B2 (en) |
EP (1) | EP1570518A2 (en) |
JP (1) | JP4767541B2 (en) |
KR (1) | KR100702549B1 (en) |
CN (1) | CN100461369C (en) |
AU (1) | AU2003300263A1 (en) |
TW (1) | TWI236099B (en) |
WO (1) | WO2004053926A2 (en) |
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US7122462B2 (en) * | 2003-11-21 | 2006-10-17 | International Business Machines Corporation | Back end interconnect with a shaped interface |
KR100573897B1 (en) * | 2003-12-30 | 2006-04-26 | 동부일렉트로닉스 주식회사 | Method for fabricating semiconductor |
KR100564801B1 (en) * | 2003-12-30 | 2006-03-28 | 동부아남반도체 주식회사 | Method for fabricating semiconductor |
KR100538444B1 (en) * | 2003-12-31 | 2005-12-22 | 동부아남반도체 주식회사 | Method for fabricating via hole and trench |
JP4393244B2 (en) * | 2004-03-29 | 2010-01-06 | キヤノン株式会社 | Imprint device |
US8432037B2 (en) | 2004-06-10 | 2013-04-30 | Renesas Electronics Corporation | Semiconductor device with a line and method of fabrication thereof |
JP4832807B2 (en) | 2004-06-10 | 2011-12-07 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
JP4786680B2 (en) * | 2004-06-10 | 2011-10-05 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
US7115522B2 (en) * | 2004-07-09 | 2006-10-03 | Kabushiki Kaisha Toshiba | Method for manufacturing semiconductor device |
JP2006216787A (en) * | 2005-02-03 | 2006-08-17 | Renesas Technology Corp | Semiconductor device and its fabrication process |
JP4830421B2 (en) * | 2005-06-28 | 2011-12-07 | 東京エレクトロン株式会社 | Metal film forming method and film forming apparatus |
JP2007109736A (en) * | 2005-10-11 | 2007-04-26 | Nec Electronics Corp | Semiconductor device and method of manufacturing same |
JP2007109894A (en) * | 2005-10-13 | 2007-04-26 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
US7312531B2 (en) * | 2005-10-28 | 2007-12-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and fabrication method thereof |
US20070126120A1 (en) * | 2005-12-06 | 2007-06-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device |
KR100721620B1 (en) | 2005-12-28 | 2007-05-23 | 매그나칩 반도체 유한회사 | Method for manufacturing a semiconductor device |
US7528066B2 (en) * | 2006-03-01 | 2009-05-05 | International Business Machines Corporation | Structure and method for metal integration |
JP2007311771A (en) * | 2006-04-21 | 2007-11-29 | Sanyo Electric Co Ltd | Semiconductor device and method of manufacturing the same |
DE102006035645B4 (en) * | 2006-07-31 | 2012-03-08 | Advanced Micro Devices, Inc. | Method for forming an electrically conductive line in an integrated circuit |
JP2008041700A (en) * | 2006-08-01 | 2008-02-21 | Tokyo Electron Ltd | Method and apparatus of forming film, and recording medium |
US7666781B2 (en) * | 2006-11-22 | 2010-02-23 | International Business Machines Corporation | Interconnect structures with improved electromigration resistance and methods for forming such interconnect structures |
DE102007004860B4 (en) * | 2007-01-31 | 2008-11-06 | Advanced Micro Devices, Inc., Sunnyvale | A method of making a copper-based metallization layer having a conductive overcoat by an improved integration scheme |
JP5103914B2 (en) * | 2007-01-31 | 2012-12-19 | 富士通セミコンダクター株式会社 | Semiconductor device manufacturing method and semiconductor device |
US20090001584A1 (en) * | 2007-06-26 | 2009-01-01 | Sang-Chul Kim | Semiconductor device and method for fabricating the same |
KR100870271B1 (en) * | 2007-06-28 | 2008-11-25 | 주식회사 하이닉스반도체 | Metal layer of semiconductor and forming method thereof |
US7892968B2 (en) * | 2008-01-21 | 2011-02-22 | International Business Machines Corporation | Via gouging methods and related semiconductor structure |
JP2010040772A (en) * | 2008-08-05 | 2010-02-18 | Rohm Co Ltd | Method of manufacturing semiconductor device |
US8337675B2 (en) | 2009-01-26 | 2012-12-25 | Spts Technologies Limited | Method of plasma vapour deposition |
US8487386B2 (en) * | 2009-06-18 | 2013-07-16 | Imec | Method for forming MEMS devices having low contact resistance and devices obtained thereof |
CN102376632B (en) * | 2010-08-19 | 2013-10-30 | 中芯国际集成电路制造(上海)有限公司 | Method for forming structure of semiconductor device |
DE102010063294B4 (en) * | 2010-12-16 | 2019-07-11 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | A method of manufacturing metallization systems of semiconductor devices comprising a copper / silicon compound as a barrier material |
US8368053B2 (en) * | 2011-03-03 | 2013-02-05 | International Business Machines Corporation | Multilayer-interconnection first integration scheme for graphene and carbon nanotube transistor based integration |
CN102361006B (en) * | 2011-10-25 | 2016-08-24 | 上海集成电路研发中心有限公司 | A kind of preparation method of low stress tantalum nitrogen film |
US9536777B2 (en) | 2013-03-13 | 2017-01-03 | Taiwan Semiconductor Manufacutring Company, Ltd. | Interconnect apparatus and method |
CN104051423B (en) * | 2013-03-13 | 2018-02-16 | 台湾积体电路制造股份有限公司 | Interconnection means and method |
US9293392B2 (en) | 2013-09-06 | 2016-03-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC interconnect apparatus and method |
US9305886B2 (en) * | 2013-12-18 | 2016-04-05 | Globalfoundries Singapore Pte. Ltd. | Integrated circuits having crack-stop structures and methods for fabricating the same |
CN105098068A (en) * | 2014-05-22 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacturing method thereof and electronic device |
CN104362139B (en) * | 2014-09-23 | 2018-02-02 | 上海华力微电子有限公司 | Diffusion impervious layer, semiconductor devices and its manufacture method of copper-connection |
US9431603B1 (en) * | 2015-05-15 | 2016-08-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | RRAM device |
US10332790B2 (en) | 2015-06-15 | 2019-06-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fin field effect transistor (FinFET) device structure with interconnect structure |
US9536826B1 (en) | 2015-06-15 | 2017-01-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fin field effect transistor (finFET) device structure with interconnect structure |
US9786603B1 (en) * | 2016-09-22 | 2017-10-10 | International Business Machines Corporation | Surface nitridation in metal interconnects |
TWI697032B (en) * | 2016-10-24 | 2020-06-21 | 聯華電子股份有限公司 | Method of fabricating semiconductor device |
CN108063117B (en) * | 2016-11-09 | 2020-12-01 | 中芯国际集成电路制造(上海)有限公司 | Interconnect structure and method of forming the same |
CN109346436A (en) * | 2018-09-20 | 2019-02-15 | 德淮半导体有限公司 | The method for manufacturing semiconductor device |
Citations (1)
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US20020142590A1 (en) * | 2001-03-28 | 2002-10-03 | Wei Pan | Method of barrier metal surface treatment prior to Cu deposition to improve adhesion and trench filling characteristics |
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US5933753A (en) * | 1996-12-16 | 1999-08-03 | International Business Machines Corporation | Open-bottomed via liner structure and method for fabricating same |
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-
2002
- 2002-12-11 US US10/318,605 patent/US6949461B2/en not_active Expired - Lifetime
-
2003
- 2003-11-27 TW TW092133341A patent/TWI236099B/en not_active IP Right Cessation
- 2003-12-08 WO PCT/EP2003/050958 patent/WO2004053926A2/en active Application Filing
- 2003-12-08 AU AU2003300263A patent/AU2003300263A1/en not_active Abandoned
- 2003-12-08 JP JP2004558112A patent/JP4767541B2/en not_active Expired - Lifetime
- 2003-12-08 CN CNB2003801055872A patent/CN100461369C/en not_active Expired - Lifetime
- 2003-12-08 KR KR1020057008286A patent/KR100702549B1/en active IP Right Grant
- 2003-12-08 EP EP03799543A patent/EP1570518A2/en not_active Withdrawn
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020142590A1 (en) * | 2001-03-28 | 2002-10-03 | Wei Pan | Method of barrier metal surface treatment prior to Cu deposition to improve adhesion and trench filling characteristics |
Non-Patent Citations (1)
Title |
---|
YAMAGISHI H ET AL: "TEM/SEM INVESTIGATION AND ELECTRICAL EVALUATION OF A BOTTOMLESS I-PVD TA(N) BARRIER IN DUAL DAMASCENE", ADVANCED METALLIZATION CONFERENCE. PROCEEDINGS OF THE CONFERENCE, XX, XX, 2 October 2000 (2000-10-02), pages 279 - 285, XP008012016 * |
Also Published As
Publication number | Publication date |
---|---|
WO2004053926A2 (en) | 2004-06-24 |
AU2003300263A1 (en) | 2004-06-30 |
KR100702549B1 (en) | 2007-04-04 |
CN1947236A (en) | 2007-04-11 |
CN100461369C (en) | 2009-02-11 |
TWI236099B (en) | 2005-07-11 |
JP4767541B2 (en) | 2011-09-07 |
US20040115928A1 (en) | 2004-06-17 |
US6949461B2 (en) | 2005-09-27 |
KR20050086476A (en) | 2005-08-30 |
EP1570518A2 (en) | 2005-09-07 |
JP2006518927A (en) | 2006-08-17 |
AU2003300263A8 (en) | 2004-06-30 |
TW200421542A (en) | 2004-10-16 |
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