WO2004053716A3 - Dataflow-synchronized embedded field programmable processor array - Google Patents

Dataflow-synchronized embedded field programmable processor array Download PDF

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Publication number
WO2004053716A3
WO2004053716A3 PCT/IB2003/005623 IB0305623W WO2004053716A3 WO 2004053716 A3 WO2004053716 A3 WO 2004053716A3 IB 0305623 W IB0305623 W IB 0305623W WO 2004053716 A3 WO2004053716 A3 WO 2004053716A3
Authority
WO
WIPO (PCT)
Prior art keywords
array
field programmable
programmable processor
dataflow
embedded field
Prior art date
Application number
PCT/IB2003/005623
Other languages
French (fr)
Other versions
WO2004053716A2 (en
Inventor
Geoffrey F Burns
Krishnamerthy Vaidyanathan
Original Assignee
Koninkl Philips Electronics Nv
Geoffrey F Burns
Krishnamerthy Vaidyanathan
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv, Geoffrey F Burns, Krishnamerthy Vaidyanathan filed Critical Koninkl Philips Electronics Nv
Priority to EP03775666A priority Critical patent/EP1573573A2/en
Priority to AU2003283685A priority patent/AU2003283685A1/en
Priority to JP2005502339A priority patent/JP2006510128A/en
Publication of WO2004053716A2 publication Critical patent/WO2004053716A2/en
Publication of WO2004053716A3 publication Critical patent/WO2004053716A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8023—Two dimensional arrays, e.g. mesh, torus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)

Abstract

An embedded field programmable processor includes a two-dimensional array of processing cells for performing mathematical operations whose timing depends on the inflow of operands. An array interface reconfigurably connects paths for the inflow to respective cells on the array periphery. The array is preferably of the systolic type and is preferably implemented with nearest neighbor inter-cell connections.
PCT/IB2003/005623 2002-12-12 2003-11-28 Dataflow-synchronized embedded field programmable processor array WO2004053716A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP03775666A EP1573573A2 (en) 2002-12-12 2003-11-28 Dataflow-synchronized embedded field programmable processor array
AU2003283685A AU2003283685A1 (en) 2002-12-12 2003-11-28 Dataflow-synchronized embedded field programmable processor array
JP2005502339A JP2006510128A (en) 2002-12-12 2003-11-28 Data flow synchronous embedded field programmable processor array

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US43297102P 2002-12-12 2002-12-12
US60/432,971 2002-12-12
US47516603P 2003-06-02 2003-06-02
US60/475,166 2003-06-02

Publications (2)

Publication Number Publication Date
WO2004053716A2 WO2004053716A2 (en) 2004-06-24
WO2004053716A3 true WO2004053716A3 (en) 2005-03-17

Family

ID=32511684

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2003/005623 WO2004053716A2 (en) 2002-12-12 2003-11-28 Dataflow-synchronized embedded field programmable processor array

Country Status (5)

Country Link
EP (1) EP1573573A2 (en)
JP (1) JP2006510128A (en)
KR (1) KR20050091715A (en)
AU (1) AU2003283685A1 (en)
WO (1) WO2004053716A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004044976A1 (en) * 2004-09-16 2006-03-30 Siemens Ag Computer device with reconfigurable architecture
CN112738777B (en) * 2020-12-24 2022-04-08 山东高云半导体科技有限公司 Near field communication device and method, readable storage medium and processor

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1991019268A1 (en) * 1990-05-29 1991-12-12 Wavetracer, Inc. Virtual processing address and instruction generator for parallel processor array
EP0639816A2 (en) * 1993-08-20 1995-02-22 Actel Corporation Field programmable digital signal processing array integrated circuit
US5892962A (en) * 1996-11-12 1999-04-06 Lucent Technologies Inc. FPGA-based processor
WO2000077652A2 (en) * 1999-06-10 2000-12-21 Pact Informationstechnologie Gmbh Sequence partitioning in cell structures
US20020133688A1 (en) * 2001-01-29 2002-09-19 Ming-Hau Lee SIMD/MIMD processing on a reconfigurable array
US6457116B1 (en) * 1997-10-31 2002-09-24 Broadcom Corporation Method and apparatus for controlling contexts of multiple context processing elements in a network of multiple context processing elements

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1991019268A1 (en) * 1990-05-29 1991-12-12 Wavetracer, Inc. Virtual processing address and instruction generator for parallel processor array
EP0639816A2 (en) * 1993-08-20 1995-02-22 Actel Corporation Field programmable digital signal processing array integrated circuit
US5892962A (en) * 1996-11-12 1999-04-06 Lucent Technologies Inc. FPGA-based processor
US6457116B1 (en) * 1997-10-31 2002-09-24 Broadcom Corporation Method and apparatus for controlling contexts of multiple context processing elements in a network of multiple context processing elements
WO2000077652A2 (en) * 1999-06-10 2000-12-21 Pact Informationstechnologie Gmbh Sequence partitioning in cell structures
US20020133688A1 (en) * 2001-01-29 2002-09-19 Ming-Hau Lee SIMD/MIMD processing on a reconfigurable array

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
CALLAHAN T J ET AL: "THE GARP ARCHITECTURE AND C COMPILER", COMPUTER, IEEE COMPUTER SOCIETY, LONG BEACH., CA, US, US, vol. 33, no. 4, April 2000 (2000-04-01), pages 62 - 69, XP000948675, ISSN: 0018-9162 *
CUCCHIARA R ET AL: "RECONFIGURING THE BOUNDARIES OF A MESH-CONNECTED ARRAY OF PROCESSORS WITH RUN-TIME PROGRAMMABLE LOGIC", MICROPROCESSORS AND MICROSYSTEMS, IPC BUSINESS PRESS LTD. LONDON, GB, vol. 17, no. 2, January 1993 (1993-01-01), pages 67 - 73, XP000355541, ISSN: 0141-9331 *
HARBAUM T ET AL: "DESIGN OF A FLEXIBLE COPROCESSOR UNIT", PROCEEDINGS OF THE EUROMICRO CONFERENCE, XX, XX, September 1999 (1999-09-01), pages 335 - 342, XP000879556 *

Also Published As

Publication number Publication date
JP2006510128A (en) 2006-03-23
EP1573573A2 (en) 2005-09-14
AU2003283685A1 (en) 2004-06-30
WO2004053716A2 (en) 2004-06-24
KR20050091715A (en) 2005-09-15

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