WO2004046933A1

WO2004046933A1 - Memory controller and cache replacement control method

Info

Publication number: WO2004046933A1
Application number: PCT/JP2002/012137
Authority: WO
Inventors: Manabu Nakao
Original assignee: Fujitsu Limited
Priority date: 2002-11-20
Filing date: 2002-11-20
Publication date: 2004-06-03
Also published as: JPWO2004046933A1; JP3940148B2

Abstract

A memory controller comprising a single-port LRU RAM (26) holding replacement way information on replacement of a cache memory (a cache tag RAM (22) and a cache data RAM (23)), an LRU replacement way selecting section (27) for selecting a way to be replaced by an LRU algorithm depending on the replacement way information on the single-port LRU RAM (26), a random replacement way selecting section (105) for selecting a way to be replaced randomly without using the replacement way information, a hit decision section (102) for carrying out hit decision about first and second requests simultaneously made for an access to a cache memory by a CPU (10), and an arbiter section (104) for, if the hit decisions about the first and second requests are both cache misses, allowing the LRU replacement way selecting section (27) to select a way in response to the first request and allowing the random replacement way selecting section (105) to select a way in response to the second request.

Description

Description Memory control device and cache replacement control method

The present invention relates to a memory control device and a cache replacement control method, and more particularly, to a memory control device and a cache replacement control method capable of coping with a plurality of simultaneous accesses and improving a cache performance while reducing a mounting area. It is. Background art

FIG. 8 is a block diagram showing a configuration of a conventional cache memory device 20. The cache memory device 20 shown in this figure is a device provided with a cache memory in order to fill a speed difference between a CPU (Central Processing Unit) 10 and a main storage device 30. This cache memory includes a cache tag RAM (Random Access Memory) 22 and a cache data RAM 23 described later.

The CPU 10 issues a request for reading or writing data to the cache memory device 20 and reads / writes data from the cache memory or the main storage device 30.

The main storage device 30 has a characteristic that it has a large capacity and an access time is slower than that of the cache memory (the cache tag RAM 22 and the cache data RAM 23). The main storage device 30 stores all data used by the CPU 10.

The cache memory (the cache tag RAM 22 and the cache data RAM 23) stores a part (frequently used data) of all the data stored in the main storage device 30. The cache memory is, for example, an SRAM (Static Random Access Memory). If the access time is shorter than that of the main storage device 30, It has such characteristics.

Further, from the viewpoint of storage capacity, the storage capacity of the cache memory is smaller than that of the main storage device 30.

Here, in the cache memory device 20, a set associative method is adopted as a data storage method. In this set-associative method, as shown in Fig. 9, the cache memory (cache tag; AM22 and cache data RAM23) is divided into a plurality of ways (way 0 and way 1), and each way is Is a method in which data is stored in a determined line. In the cache tag RAM 22 shown in the figure, for example, the address a is stored in the line N of the way 0, and the address b is stored in the line N of the way 1.

In the cache data RAM 23, for example, data A is stored in line N of way 0, and data B is stored in line N of way 1. In the cache tag RAM 22 and the cache data RAM 23, the address “a” corresponds to the data A, and the address “b” corresponds to the data B on a one-to-one basis.

Returning to FIG. 8, the cache tag unit 21 receives a request (address) from the CPU 10 and includes a cache tag RAM 22 and a hit determination unit 24. The cache tag RAM 22 stores an address (tag) corresponding to data stored in the cache data RAM 23 (see FIG. 9). The hit determination unit 24 compares the address from the CPU 10 with the address of the cache tag RAM22, and if they match, determines the hit determination result as "cache hit". A “cache hit” means that data corresponding to the address exists in the cache data RAM 23.

On the other hand, if the address from the CPU 10 does not match the address of the cache tag RAM 22, the hit determination unit 24 determines the hit determination result as "cache miss". In the case of "cache miss", the data corresponding to the address is Flash data RAM23 does not exist.

"In the case of a cache miss J, the data corresponding to the address is read from the main storage device 30, the data is replaced (rewritten) by the cache data RAM 23, and then passed to the CPU 10. In order to replace the data, it is necessary to flush data of a certain way in the cache data RAM 23. Then, data from the main storage device 30 is stored in the way.

Here, in the conventional cache memory device 20, as an algorithm for selecting a way to be replaced (hereinafter, referred to as a replace way) from a plurality of ways, a way in which the least used data is stored is stored. LRU (Last Recently Used) method is adopted.

The hit determination unit 24 notifies the hit determination result to the single port LRU • RAM 26 and the cache data RAM 23.

The replace unit 25 has a function of selecting a way to be replaced in the cache data RAM 23 (see FIG. 9) when the hit determination result is “cache miss”. It is composed of a replacement way selection unit 27.

The single-port LRU / RAM 26 has one input port, and when replacing data in the cache data RAM 23, stores the replacement way information indicating the replacement way selected by the LRU method described above. Specifically, as shown in FIG. 9, the single-port LRU 'RAM 26 stores replacement way information corresponding to the replacement way number (0) for each line. In the figure, the replacement way information indicating the way 0 as the replacement way is stored in the line N.

That is, in the cache data RAM 23, the data A stored in the way 0 (line N) is the least used data.

Returning to FIG. 8, the LRU replacement way selecting unit 27 is provided with a plurality of memory units in the cache memory (the cache tag RAM 22 and the cache data RAM 23). After referring to the single-port LRU / RAM 26 from among the rays and selecting a replacement way by the LRU method, an LRU replacement request (including an address) is issued to the main storage device 30.

The main storage device 30 reads data from an address corresponding to the LRU replacement request, stores the data in a replacement way (line) of the cache data RAM 23, and executes a replacement process.

Next, the operation of the conventional cache memory device 20 will be described with reference to the flowchart shown in FIG. In step SA1, the hit determination unit 24 determines whether or not there is a request from the CPU 10 (conventionally, a data read is explained as an example). In this case, the determination result is “No”, and the determination is made. repeat.

Then, when there is a request from the CPU 10, the hit determination unit 24 sets the determination result of step SA1 to “Yes”. In step S A2, the hit judging unit 24 accesses the cache tag RAM 22 and compares the address from the CPU 10 with the address of the cache tag RAM 22 to make a hit judgment.

In step SA3, the hit determination unit 24 determines whether or not a cache hit has occurred. If the determination result in step SA3 is “Yes”, that is, if the hit determination result is “cache hit”, data is transferred from the cache data RAM 23 to the CPU 10 in step SA4.

That is, when the hit determination result (cache hit) is notified from the hit determination unit 24 to the cache data RAM 23, the data stored in the corresponding address of the cache data RAM 23 is read, and this data is transferred to the CPU 10. Is done.

On the other hand, if the result of the determination in step SA3 is “No”, that is, if the result of the hit determination is “cache miss”, in step SA5, the hit determination unit 24 replaces the replacement unit 25 (single-port LRU RAM26 ) And the cache data RAM 23 are notified of the hit determination result (“cache miss”). In step SA 6, the LRU replacement way selection unit 27 receives the hit determination result (“cache miss”), refers to the single-port LRU * RAM 26, and replaces the replacement data in the cache data RAM 23 based on the LRU method described above. Select

In step SA7, the LRU replacement way selection unit 27 issues an LRU replacement request (including an address) corresponding to the replacement way selected in step S A6 to the main storage device 30.

In step S A8, the main storage device 30 receives the LRU replacement request and reads data from the address. In step SA9, the main storage device 30 transfers the read data to the cache data RAM 23.

In step SA10, a replacement process is performed in which data is stored (replaced) in the rib raceway (line) selected by the LRU replacement way selection unit 27. In step SA4, the data is transferred from the cache data RAM 23 to the CPU 10.

Here, in recent years, there are many cases in which a superscalar system in which a microprocessor executes a plurality of processes simultaneously is adopted. In the superscalar method, a cache memory device capable of processing a plurality of requests according to a plurality of processes is required.

Conventionally, in response to the above needs, for example, instead of the single report LRU.RAM 26 shown in FIG. It is configured to be able to do it.

FIG. 11 is a block diagram showing a configuration of a conventional cache memory device 40 provided with the above-described multi-port LRU / RAM. In this figure, parts corresponding to the respective parts in FIG. 8 are denoted by the same reference numerals.

In FIG. 11, a cache memory device 40 is provided instead of the cache memory device 20 shown in FIG. In the cache memory device 40, instead of the cache tag unit 21 and the replacement unit 25 shown in FIG. A cache tag section 41 and a replacement section 43 are provided.

The cache tag unit 41 can receive a plurality of requests (addresses) from the CPU 10, that is, a first request (address) and a second request (address). It consists of a hit decision unit 42.

The hit determination unit 42 performs a hit determination by comparing the address corresponding to the first request from the CPU 10 with the address of the cache tag RAM 22, and notifies the first hit determination result.

Further, the hit determination unit 42 compares the address corresponding to the second request from the CPU 10 with the address of the cache tag RAM 22, performs a hit determination, and notifies the second hit determination result. .

The replace unit 43 selects a way to be replaced in the cache data RAM 23 (see FIG. 9) in parallel when both the first hit determination result and the second hit determination result are “cache miss”. It has a multi-port LRU / RAM 44, a first LRU replacement way selection unit 45, and a second LRU replacement way selection unit 46.

The multi-port LRU / RAM 44 has two input ports corresponding to the first hit judgment result (first request) and the second hit judgment result (second request), respectively. When the data is to be replaced by the replacement method, the replacement information indicating the replacement way selected by the above-mentioned LRU method is stored.

The first LRU replacement way selection unit 45 is provided corresponding to the first hit determination result (cache miss), and selects one of a plurality of ways in the cache memory (cache tag RAM22 and cache data RAM23). After referring to the multiport LRU / RAM 44 and selecting the first replacement way by the LRU method, a first LRU replacement request (including an address) is issued to the main storage device 30. The second LRU replacement way selection unit 46 is provided corresponding to the second hit determination result (cache miss), and selects a plurality of ways in the cache memory (cache tag RAM 22 and cache data RAM 23). After referring to the multiport LRU / RAM 44 and selecting the second replacement way by the LRU method, a second LRU replacement request (including an address) is issued to the main storage device 30.

The main storage device 30 reads out the first data and the second data from the addresses corresponding to the first LRU replacement request and the second LRU replacement request, and stores them in the first data of the cache data RAM 23. They are stored in the replacement way (line) and the second replacement way (line), respectively, and the replacement processing is executed in parallel.

By the way, as described above, in the conventional cache memory device 40 (see FIG. 11), a multi-port LRU / RAM 44 having two input ports is provided to support a plurality of simultaneous requests from the CPU 10. .

However, when the multi-port LRU / RAM44 is adopted, there is a problem that the mounting area is increased compared to the single-port LRU / RAM26 (see FIG. 8), and the demand for miniaturization cannot be met. .

Therefore, in the cache memory device 20 shown in FIG. 8, when there are a plurality of simultaneous requests from the CPU 10, one of the requests is processed first, and then the other request is processed again. Can be considered. This configuration has the advantage that the LRU replacement way is selected in order in response to a plurality of simultaneous requests, so that the cache memory hit rate does not decrease.

However, in a configuration in which pipeline processing is performed, when the other request is processed again, the processing returns to the first stage of the pipeline, so that a considerable amount of time is required before the other request is processed. It has the disadvantage that it takes time. Such a delay in processing time causes a decrease in cache performance when large-scale data is used, such as in scientific and technological operations and transaction processing. Also, when handling large-scale data, in many cases, data is stored in the cache memory and immediately replaced without being used. There is a need to bring the data as soon as possible.

The present invention has been made in view of the above, and an object of the present invention is to provide a memory control device and a cache replacement control method capable of coping with a plurality of simultaneous accesses and improving a cache performance while reducing a mounting area. And Disclosure of the invention

In order to achieve the above object, the present invention relates to a memory control device provided between a higher-level device and a main storage device and configured to control a cache memory having a multi-way configuration. Replacement way information holding means for holding way information; first rib race way selection means for selecting a first way to be replaced based on the replacement way information of the replacement way information holding means. A second replacement way selecting means for selecting a second way to be replaced without using the replacement way information, and a first request for accessing the cache memory issued simultaneously from the host device. Determination means for performing a hit determination for each of the second request and the second request If the hit determinations corresponding to the first request and the second request are both cache misses, the first replacement bay selecting means may correspond to the first request and Arbitration means for selecting the one way and causing the second replacement way selection means to select the second way in response to the second request. Also, the present invention provides a cache replacement device provided between a higher-level device and a main storage device and applied to a cache memory device having a cache memory of a multi-layer configuration. A first replacement way selection step of selecting a first way to be replaced based on replacement way information stored in the replacement way information holding means and related to replacement of the cache memory. A second rib raceway selecting step of selecting a second way to be replaced without using the replacement pay information, and a first request for accessing the cache memory issued simultaneously from the higher-level device. A hit determination step of performing a hit determination for each of the first request and the second request; and if the hit determinations corresponding to the first request and the second request are both cache misses, the first request Correspondingly, the first way is selected in the first replacement Together thereby, and a mediation step of selecting the second way in the said to correspond to second request the second replace-way selection process, characterized in containing Mukoto.

According to the powerful invention, when the hit judgments corresponding to the first request and the second request are both cache misses, the first way is selected according to the first request and However, since the second way to be replaced is selected without using the replacement way information in response to the second request, a single port replacement way information holding means can support multiple simultaneous accesses. The cache performance can be improved while reducing the mounting area. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a block diagram showing the configuration of the first embodiment according to the present invention. FIG. 2 is a diagram for explaining the operation of the replacement unit 103 shown in FIG. FIG. 4 is a flowchart for explaining the operation of the first embodiment. FIG. 4 is a block diagram showing the configuration of the second embodiment according to the present invention. FIG. FIG. 6 is a diagram for explaining the operation of the replacement unit 201, FIG. 6 is a diagram for explaining the operation of the hit state determination unit 202 shown in FIG. 4, and FIG. FIG. 8 is a flowchart for explaining the operation of the second embodiment. FIG. 8 shows a conventional cache memory device 20. FIG. 9 is a block diagram showing the configuration of the cache tag RAM22, cache data RAM23 and single-port LRU / RAM26 shown in FIG. 8, and FIG. 10 is a block diagram showing the configuration of FIG. Is a flowchart for explaining the operation of the cache memory device 20 shown in FIG. 1, and FIG. 11 is a block diagram showing a configuration of a conventional cache memory device 40. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, Embodiments 1 and 2 according to the present invention will be described in detail with reference to the drawings.

(Embodiment 1)

FIG. 1 is a block diagram showing a configuration of a first embodiment according to the present invention. In this figure, the same reference numerals are given to parts corresponding to the respective parts in FIG. In FIG. 1, a cache memory device 100 is provided instead of the cache memory device 20 shown in FIG.

In the cache memory device 100, a cache tag unit 101 and a replacement unit 103 are provided instead of the cache tag unit 21 and the replacement unit 25 shown in FIG.

The cache tag unit 101 is capable of receiving a plurality of requests (addresses) from the CPU 10, that is, a first request (address) and a second request (address). It consists of 02.

Further, the CPU 10 may issue the first request and the second request at the same time, or may issue the first request (or the second request) alone.

The hit determination unit 102 performs a hit determination by comparing an address corresponding to the first request from the CPU 10 with the address of the cache tag RAM 22, and notifies the first hit determination result. Also, the hit determination unit 102 compares the address corresponding to the second request from the CPU 10 with the address of the cache tag RAM 22, performs a hit determination, and notifies the second hit determination result. .

As shown in FIG. 2, the replacement unit 103 determines a way to be replaced in the cache data RAM 23 (see FIG. 9) according to the first request from the CPU 10 and the presence or absence of the second request. It has a function to select by LRU method (LRU method, random method).

Here, as described above, the LRU method is a method of selecting a way in which the least used data is stored from a plurality of ways in the cache memory (the cache tag RAM 22 and the cache data RAM 23). is there. On the other hand, the random method is a method of randomly selecting a way from a plurality of ways in the cache memory (the cache tag RAM 22 and the cache data RAM 23).

The replacement unit 103 includes a single-port LRU / RAM 26 (see FIG. 9), an arbitration unit 104, a random replacement way selection unit 105, and an LRU replacement way selection unit 27.

As described above, the single-port LRU.RAM26 (see Fig. 9) has one input port, and when replacing data in the cache data RAM 23, the replacement way selected by the LRU method is used. Replacement information to be stored is stored.

The arbitration unit 104 arbitrates the processing of the first request and the processing of the second request according to the presence or absence of the first request and the second request from the CPU 10, as shown in FIG.

That is, as shown in FIG. 2, if neither the first request nor the second request is present (= 0), no processing is performed. When there is only the first request (= 1), that is, when only the first hit determination result is input from the hit determination unit 102, the arbitration unit 104 processes the first request by the LRU method The first hit judgment result is passed to the single-port LRU · RAM26 in order to perform this. Also, when there is only the second request (= 1), that is, when only the second hit determination result is input from the hit determination unit 102, the arbitration unit 104 converts the second request by the LRU method. The second hit determination result is passed to the single-port LRU-RAM 26 for processing.

Also, when both the first request and the second request are present at the same time (= 1), that is, both the first hit determination result and the second hit determination result are input from the hit determination unit 102 at the same time. In this case, the arbitration unit 104 should process the first request by the LRU method, pass the first hit determination result to the single-port LRURAM26, and process the second request by the random method. Hand over to random replacer selection unit 105.

The LRU replacement way selection unit 27 refers to the single-port LRU / RAM 26 from a plurality of ways in the cache memory (the cache tag RAM 22 and the cache data RAM 23), selects a replacement layer by the LRU method, A replacement request (including an address) is issued to the main storage device 30. The random replacement way selection unit 105 selects a replacement way from a plurality of ways in the cache memory (the cache tag RAM 22 and the cache data RAM 23) in a random manner, and then stores a replacement request (including an address) in a main memory. Take out to device 30.

The main storage device 30 reads out the first data and the second data from the addresses corresponding to the two replacement requests, stores them in each of the replacement ways (lines) of the cache data RAM 23, and performs the replacement process. Execute

Next, the operation of the first embodiment will be described with reference to the flowchart shown in FIG.

In step SB1, the hit determination unit 102 determines whether or not there is a request from the CPU 10 (in the first embodiment, a case of reading data is described as an example), and in this case, the determination result is “ The judgment is repeated as "No." Then, when there is a first request and a second request from the CPU 10 simultaneously, the hit determination unit 102 sets the determination result of step SB1 to "Yes". In step SB 2, the hit determination unit 102 accesses the cache tag RAM 22, compares each address from the CPU 10 with the address of the cache tag RAM 22, and performs the first request and the second request Hit judgment is performed for each of the above.

In step SB3, the hit determination section 102 determines whether or not a cache hit has occurred. If the determination result of step SB 3 is “Yes”, that is, if the hit determination results are each “cache hit”, in step SB 4, the first data and the second data Data is transferred.

That is, when the first hit determination result (cache hit) and the second hit determination result (cache hit) are notified from the hit determination unit 102 to the cache data RAM 23, they are stored in the corresponding address of the cache data RAM 23. The first data and the second data are read, and the first data and the second data are transferred to the CPU 10.

On the other hand, if the determination result of step SB 3 is “No”, that is, “cache miss”, in step SB 5, the hit determination unit 102 sends the first hit determination result to the arbitration unit 104 of the replacement unit 103. (“Cache miss”) and the second hit determination result (“cache miss”).

In step SB6, the arbitration unit 104 determines whether or not there is a power having a plurality of simultaneous cache misses based on the notified first hit determination result and the second hit determination result. Let the result be "Yes".

Thereafter, Step SB7 to Step SB12 and Step SB13 to Step SB18 are executed in parallel.

That is, in step SB7, the arbitration unit 104 notifies the single-port LRU 'RAM 26 of the first hit determination result ("cache miss"). In step SB8, the LRU replacement way selection unit 27 receives the first hit determination result (“cache miss”), refers to the single-port LRU RAM 26, and based on the LRU method described above, Select the replacement way in.

In step SB9, the LRU replacement way selection unit 27 issues a replacement request to the main storage device 30 corresponding to the replacement way selected in step SB8.

In step SB10, the main storage device 30 reads the first data from the address in response to the replacement request. In step SB11, the main storage device 30 transfers the read first data to the cache data RAM 23.

In step SB12, a rib race process is executed in which the first data is stored (replaced) in the replacement way (line) selected by the LRU replacement way selection unit 27.

On the other hand, in step SB13, the arbitration unit 104 notifies the random replacement way selection unit 105 of the second hit determination result (“cache miss”).

In step SB14, upon receiving the second hit determination result (“cache miss”), the random replacement way selection unit 105 selects a replacement way in the cache data RAM 23 based on the random method described above.

In step SB15, the random replacement way selection unit 105 issues a replacement request to the main storage device 30 corresponding to the replacement way selected in step SB14.

In step SB16, the main storage device 30 receives the replacement request and reads the second data from the address. In step SB17, the main storage device 30 transfers the read second data to the cache data RAM23.

In step SB18, a replacement process is executed in which data is stored (replaced) in the replacement way (line) selected by the random replacement way selection unit 105. In step SB4, the first data and the second data are transferred from the cache data RAM 23 to the CPU 10.

If there is only the first request from the CPU 10, the hit determination unit 102 sets the determination result of step SB1 to “Yes”. In step SB2, the hit determination # 102 accesses the cache tag RAM 22, compares the address from the CPU 10 with the address of the cache tag RAM 22, and performs a hit determination on the first request.

In step SB3, the hit determination section 102 determines whether or not a cache hit has occurred. If the determination result of step SB3 is "Yes", that is, if the hit determination result is "cache hit", data is transferred from the cache data RAM 23 to the CPU 10 in step SB4.

That is, when the first hit determination result (cache hit) is notified from the hit determination unit 102 to the cache data RAM 23, the first data stored in the address of the cache data RAM 23 is read, and the first data is read. Is transferred to the CPU 10.

On the other hand, if the determination result of step SB 3 is “No”, that is, “cache miss”, in step SB 5, the hit determination unit 102 sends the first hit determination result to the arbitration unit 104 of the replacement unit 103. (“Cache miss”).

In step SB6, the arbitration unit 104 determines whether or not there is simultaneous multiple cache misses based on the notified first hit determination result. In this case, the determination result is “NoJ”.

That is, in step SB7, the arbitration unit 104 notifies the single port LRU • RAM 26 of the first hit determination result (“cache miss”).

In step SB8, the LRU replacement way selection unit 27 receives the first hit determination result (“cache miss”), refers to the single-port LRU · RAM 26, and based on the LRU method described above, Select a replacement way.

In step SB10, the main storage device 30 reads the first data from the address in response to the replacement request. In step SB11, the main storage device 30 transfers the read first data to the cache data RAM23.

In step SB4, the first data is transferred from the cache data RAM 23 to the CPU 10.

If there is only the second request from the CPU 10, the hit determination unit 102 sets the determination result in step SB1 to “Yes”. In step SB2, the hit half IJ setting unit 102 accesses the cache tag RAM 22, compares the address from the CPU 10 with the address of the cache tag RAM 22, and performs a hit determination on the second request.

In step S B3, hit determination section 102 determines whether or not a cache hit has occurred. If the determination result of step SB3 is "Yes", that is, if the hit determination result is "cache hit", data is transferred from the cache data RAM 23 to the CPU 10 in step SB4.

That is, when the hit determination unit 1.02 notifies the cache data RAM 23 of the second hit determination result (cache hit), the second data stored in the cache data RAM 23 at the address is read, and the second data is read. Is transferred to the CPU 10.

On the other hand, if the determination result of step SB 3 is “No”, that is, “cache miss”, in step SB 5, the hit determination unit 102 The second hit determination result (“cache miss”) is notified to the arbitration unit 104 of 103.

In step SB6, the arbitration unit 104 determines whether there is a plurality of simultaneous cache misses based on the notified second hit determination result, and in this case, sets the determination result to “No”.

That is, in step SB7, the arbitrating unit 104 notifies the single-port LRU 'RAM 26 of the second hit determination result ("cache miss").

In step SB8, the LRU replacement way selection unit 27 receives the second hit determination result (“cache miss”), refers to the single-port LRU RAM 26, and based on the LRU method described above, Select the replacement way in.

In step SB9, the LRU replacement way selection unit 27 issues a replacement request corresponding to the replacement way selected in step SB8 to the main storage device 30.

At step SB10, the main storage device 30 receives the replacement request and reads the second data from the address. In step SB11, the main storage device 30 transfers the read second data to the cache data RAM23.

In step SB12, a replacement process is executed in which the second data is stored (replaced) in the replacement way (line) selected by the LRU replacement way selection unit 27.

In step SB4, the second data is transferred from the cache data RAM 23 to the CPU 10.

Although the first embodiment has described the configuration in which the LRU replacement way selection unit 27 selects a replacement way by the LRU method when the first request (or the second request) is issued independently, Alternatively, the random replacement way selection unit 105 may be configured to select a replacement way by a random method. As described above, according to the first embodiment, when the hit judgments corresponding to the first request and the second request by the hit judgment unit 102 are both cache misses, the first request is handled. The LRU replacement way selection section 27 selects a way, and in response to the second request, replaces the way to be replaced with a random replacement way without using the replacement way information of the Singno Report LRU RAM 26. Since the selection unit 105 makes the selection, the single port single port LRU / RAM 26 can cope with multiple simultaneous accesses, and the cache performance can be improved while reducing the mounting area.

(Embodiment 2)

In the first embodiment, the CPU 10 issues the first request and the second request at the same time, and caches both the first hit determination result and the second hit determination result. In the case of a miss, an example was described in which the replacement process was executed by the LRU or random method. However, the replacement process is configured to change based on the hit status (frequent cache hits or cache misses). May be. Hereinafter, this configuration example will be described as a second embodiment.

FIG. 4 is a block diagram showing a configuration of a second exemplary embodiment of the present invention. In this figure, parts corresponding to the respective parts in FIG. 1 are denoted by the same reference numerals. In FIG. 4, a cache memory device 200 is provided in place of the cache memory device 100 shown in FIG.

In the cache memory device 200, a replacement unit 201 is provided in place of the replacement unit 103 shown in FIG.

As shown in FIG. 5, the replacement unit 201 stores the cache data RAM 23 according to the first request from the CPU 10, the presence or absence of the second request, and the hit state described later. (See Fig. 9) It has a function to select the way to be replaced by a predetermined method (LRU method, random method).

In the replacement section 201, a hitch is used in place of the arbitration section 104 shown in FIG. A state determination unit 202 and an arbitration unit 203 are provided.

The hit state determination unit 202 receives the hit determination results (the first hit determination result and the second hit determination result) in the hit determination unit 102 and the cache miss by the state transition shown in FIG. Determine if you have a tendency to tend or a cache hit.

Specifically, in the hit state determination unit 202, if the hit determination results (the first hit determination result and the second hit determination result) of the hit determination unit 102 are cache hits, the hit state is one. Transition to the right.

On the other hand, if the hit judgment result (the first hit judgment result and the second hit judgment result) of the hit judging unit 102 is a cache miss, the hit state is shifted left by one.

For example, when the hit state is “0 1” and the hit determination result is a cache hit, the hit state determination unit 202 shifts the hit state to the right and changes “0 1” to “1”. 0 ”. Subsequently, when the hit determination result is a cache hit, the hit state determination unit 202 shifts the hit state to the right, and changes the state from “10” to “11”.

Then, when the hit determination result is a cache miss, the hit state determination unit 202 shifts the hit state to the left, and changes the state from “1 1” to “10”. Subsequently, when the hit determination result is a cache miss, the hit state determination unit 202 shifts the hit state to the left, and sets the hit state to “10” or “01”.

When the hit state is “1 0” or “1 1”, the hit state determination unit 202 determines that the hit determination result is in the ^! Direction of the cache hit, and sets the hit state as “cache hit”. The arbitration unit 203 is notified.

On the other hand, if the hit state is “0 0” or “0 1”, the hit determination result is determined to be a cache miss, and the hit state is notified to the arbitration unit 203 as “cache miss”.

As shown in FIG. 5, the arbitration unit 203 receives the first request from the CPU 10, Arbitration of the processing of the first request and the processing of the second request is performed in accordance with the presence / absence of the second request and the hit state determined by the hit state determination unit 202.

In other words, as shown in FIG. 5, if the hit status is “cache miss” (or “cache hit”) and there is no first request and no second request (= 0), I will not let you.

When the hit state is “cache miss” (or “cache hit”) and only the first request is present (= 1), that is, only the first hit determination result is If input, the arbitration unit 203 passes the first hit determination result to the single-port LRU * RAM 26 so that the first request is processed by the LRU method.

If the hit state is “cache miss” (or “cache hit”) and there is only the second request (= 1), that is, only the second hit determination result is input from the hit determination unit 102. In this case, the arbitration unit 203 passes the second hit determination result to the single-port LRU / RAM 26 in order to process the second request using the LRU method.

If the hit state is “cache miss” and both the first request and the second request are present at the same time (= 1), that is, both the first hit judgment result and the second hit judgment result Are input from the hit determination unit 102 at the same time, the arbitration unit 203 passes the first hit determination result to the single-port LRU.RAM 26 and processes the second request in order to process the first request by the LRU method. Is passed to the random replacement way selection unit 105 in order to process in a random manner.

Here, in the replacement processing by the LRU method, the way most used is selected as the replacement way, so that the cache hit rate is higher than the random method in which the replacement way is randomly selected.

Therefore, when the hit state is a cache miss, the replacement process is executed at a higher speed by a random method than in the case of an improvement in the cache hit rate. The priority is to bring the data from the main storage device 30 as soon as possible. On the other hand, if the hit state is “cache hit” and both the first request and the second request are present at the same time (= 1), that is, the first hit judgment result and the second hit judgment result If both are input from the hit determination unit 102 at the same time, the arbitration unit 203 sets the arbitration unit 203 to process the first request using the LRU method.

Pass the hit judgment result of 1 to single port LRU · RAM26.

In parallel with this, the hit state determination unit 202 re-inputs the second request corresponding to the second hit determination result to the cache tag unit 101. Note that the second request is not processed in a random manner.

For the re-input second request, a replacement procedure is executed by the LRU method.

As described above, when the hit state is a cache hit, priority is given to improving the cache hit ratio by the LRU method rather than performing the replacement process at a high speed.

Next, the operation of the above-described second embodiment will be described with reference to the flowchart shown in FIG.

In step SC1, the hit determination unit 102 determines whether or not there is a request from the CPU 10 (in the second embodiment, a case of reading data is described as an example). In this case, the hit determination unit 102 And repeat the same judgment.

Then, when there is only the first request from the CPU 10, the hit determination unit 102 sets the determination result of step SC1 to “Yes”. In step SC2, the hit determination unit 102 accesses the cache tag RAM 22, compares the address from the CPU 10 with the address of the cache tag RAM 22, and makes a hit determination for the first request.

In step SC3, the hit determination unit 102 determines whether or not a cache hit has been made. In this case, the result of the determination is “Yes”. In step SC4, the first data is transferred from the cache data RAM 23 to the CPU 10. In step SC5, the hit state determination unit 202 updates the hit state based on the first hit determination result (in this case, “cache hit”) corresponding to the first request. For example, when the hit state shown in FIG. 6 is “01”, the hit state determination unit 202 receives the cache hit and changes the hit state from “01” to “10”. As a result, the hit state is set to "cache hit".

Also, when there is a first request and a second request from the CPU 10 at the same time, the hit determination unit 102 sets the determination result of step S C1 to “Yes”. In step SC2, the hit determination unit 102 accesses the cache tag RAM 22, compares each address from the CPU 10 with the address of the cache tag RAM 22, and performs the first request and the second request. A hit judgment is made for each of.

In step S C3, the hit determination unit 102 determines whether or not a cache hit has occurred, and in this case, the determination result is “No”. In step SC6, the hit determination section 102 notifies the arbitration section 203 of the replacement section 201 of the first hit determination result (“cache miss”) and the second hit determination result (“cache miss”).

In step SC7, the arbitration unit 203 determines whether there are multiple cache misses at the same time based on the notified first hit determination result and the second hit determination result. Let the result be "Yes".

Thereafter, steps SC8 to SC13 and steps SC14 to SC21 are executed in parallel.

That is, in step SC8, the arbitration unit 203 notifies the single hit report LRU RAM 26 of the first hit determination result (“cache miss”).

In step SC9, the LRU replacement way selection unit 27 receives the first hit determination result (“cache miss”), refers to the single-port LRU RAM 26, and based on the LRU method described above, Select a replacement way.

In step SC10, the LRU replacement way selection unit 27 issues a replacement request to the main storage device 30 corresponding to the replacement way selected in step SC9.

In step SC11, the main storage device 30 receives the replacement request and reads the first data from the address. In step SC12, the main storage device 30 transfers the read first data to the cache data RAM 23.

In step SC13, a rib race process is executed in which the first data is stored (replaced) in the rib raceway (line) selected by the LRU replacement way selection unit 27.

In step SC4, the first data is transferred from the cache data RAM 23 to the CPU 10.

In step SC5, the hit state determination unit 202 determines, based on the first hit determination result and the second hit determination result corresponding to the first request and the second request (for example, both “cache miss”), Update hit status. In this case, since the hit state shown in FIG. 6 is “10”, the hit state determination unit 202 receives the above two cache misses, and changes the hit state from “10” to “01” to “00”. Transition to. As a result, the hit state is “cache miss”.

On the other hand, in step SC14, the arbitration unit 203 determines whether or not the hit state determined by the hit state determination unit 202 is a cache hit. In this case, the hit state is determined to be a cache hit “10”. Therefore, the judgment result is “Yesj”.

In step SC21, the arbitration unit 203 re-inputs the second request corresponding to the second hit determination result to the cache tag unit 101.

Accordingly, the hit determination unit 102 sets the determination result of step SC1 to “Yes”. In step SC2, the hit determination unit 102 sets the cache tag RAM2 2 is accessed, an address from the CPU 10 and the like (in this case, the re-input second request) is compared with the address of the cache tag RAM 22, and hit judgment is performed for the second request. In this case, the second hit determination result corresponding to the second request is a cache miss.

In step SC3, the hit determination unit 102 determines whether or not a cache hit has been made. In this case, the determination result is “No”. In step SC6, the hit determination unit 102 notifies the arbitration unit 203 of the replacement unit 201 of the second hit determination result (“cache miss”).

In step S C7, the arbitration unit 203 determines whether there are multiple simultaneous cache misses based on the notified second hit determination result, and in this case, sets the determination result to “No”.

In step SC8, the arbitration unit 203 notifies the single-port LRU / RAM 26 of the second hit determination result (“cache miss”).

In step SC9, the LRU replacement way selection unit 27 receives the second hit determination result (“cache miss”), refers to the single-port LRU · RAM 26, and executes the cache data Select the replacement way in RAM23.

In step SC11, the main storage device 30 receives the replacement request and reads the second data from the address. In step SC12, the main storage device 30 transfers the read second data to the cache data RAM23.

In step SC13, a rib race process is executed in which the second data is stored (replaced) in the replacement way (line) selected by the LRU replacement way selection unit 27.

In step SC4, the second data is transferred from the cache data RAM 23 to the CPU 10. Data is transferred. In step SC5, the hit state determination unit 202 updates the hit state based on the second hit determination result (“cache miss”) corresponding to the second request in the same manner as described above. I do. If the result of the determination in step SC14 is S "No", the steps SC15 to SC18 are performed in the same manner as in steps SB13 to SB18 (see Fig. 3). 20 is executed. As described above, according to the second embodiment, if the hit determinations of the hit determination units 102 are both cache misses and the hit status of the hit status determination unit 202 is a cache hit, the first In response to the request, the LRU replacement way selection unit 27 selects the first way, re-inputs the second request to the cache tag unit 101, and the hit determination unit 102 In the case of a replacement, the LRU replacement way selection unit 27 is made to select a way in response to the second request, so priority is given to improving the cache hit rate rather than performing the replacement processing at high speed. Can be done.

Although the first and second embodiments according to the present invention have been described in detail with reference to the drawings, the specific configuration example is not limited to the first and second embodiments, and departs from the gist of the present invention. Even if there is a design change within the range not to be included, it is included in the present invention.

As described above, according to the present invention, when the hit determinations corresponding to the first request and the second request are both cache misses, the first way is selected according to the first request. At the same time, the second way to be replaced is selected without using the replacement way information in response to the second request. This has the effect of improving the cache performance while reducing the mounting area.

Further, according to the present invention, when both the hit judgment is a cache miss and the hit state is a cache hit, the first way is selected in response to the first request, and the second request is made. Re-enter, if the hit judgment is a cache miss, let the first way be selected corresponding to the second request Therefore, there is an effect that it is possible to give priority to improving the cache hit rate rather than performing the replacement processing at high speed. Industrial applicability

As described above, the memory control device and the cache replacement control method according to the present invention are useful for replacing a cache memory.

Claims

The scope of the claims

1. A memory control device that is provided between a host device and a main storage device and controls a cache memory having a multi-way configuration.

Replacement way information holding means for holding replacement way information related to replacement of the cache memory;

First replacement way selection means for selecting a first way to be replaced based on the replacement way information of the replacement way information holding means; andsecond replacement target without using the replacement path information. A second replacement way selection means for selecting a way;

Hit determination means for performing hit determination for each of a first request and a second request issued simultaneously from the higher-level device and accessing the cache memory;

If the hit determinations corresponding to the first request and the second request are both cache misses, the first way is selected by the first replacement way selecting means in accordance with the first request. Arbitration means for causing the second replacement way selection means to select the second way in response to the second request;

A memory control device comprising:

2. There is provided hit state determining means for determining whether the hit state is a cache hit or a cache miss based on the hit determination of the hit determining means,

The arbitration means,

If the hit determinations corresponding to the first request and the second request are both cache misses and the hit state is the cache miss, the first request is made in correspondence with the first request. Replacement way selection means First arbitration means for selecting the first way and causing the second replacement way selection means to select the second way in response to the second request;

When both the hit determination is a cache miss and the hit state is the cache hit, the first replace way selecting means is caused to select the first way in response to the first request, The second request is re-input to the hit determination means, and if the hit determination of the hit determination means is a cache miss, the first replacement way selection means is provided with the first request in response to the second request. Second arbitration means for selecting the way

2. The memory control device according to claim 1, comprising:

3. The first replacement way selection means selects the first way based on a method of purging least used data, and the second replacement way selection means randomly selects the second replacement way. 3. The memory control device according to claim 1, wherein a way is selected.

4. In a cache replacement control method provided between a host device and a main storage device and applied to a cache memory device having a cache memory having a multi-way configuration,

A first replacement way selection step of selecting a first way to be replaced based on replacement way information related to replacement of the cache memory held in replacement way information holding means;

A second replacement way selection step of selecting a second way to be replaced without using the replacement bay information;

A hit determination step of performing a hit determination on each of a first request and a second request issued simultaneously from the higher-level device and accessing the cache memory; If the hit determinations corresponding to the first request and the second request are both cache misses, the first way is selected in the first replacement way selection step in accordance with the first request. An arbitration step of selecting the second way in the second replacement way selection step in response to the second request;

And a cache replacement control method.

5. A hit state determining step of determining whether the hit state is a cache hit or a cache miss based on the hit determination in the hit determining step,

The arbitration step,

If the hit determinations corresponding to the first request and the second request are both cache misses and the hit state is the cache miss, the first replacement is performed in response to the first request. A first arbitration step of selecting the first way in the way selection step, and selecting the second way in the second replacement way selection step in response to the second request;

If both the hit determination is a cache miss and the hit state is the cache hit, the first way is selected in the first replacement way selection step in response to the first request, and The second request is re-entered in the hit determination step. If the hit determination in the hit determination step is a cache miss, the first request is performed in the first replacement way selection step in response to the second request. A second arbitration process to select the way

5. The cache replacement control method according to claim 4, comprising: